CN202794919U - Portable monitoring and debugging system of flight control computer - Google Patents

Abstract

The utility model discloses a portable monitoring and debugging system of a flight control computer and relates to the technical field of aircraft monitoring and debugging. The portable monitoring and debugging system of the flight control computer comprises a PC machine (101), a debugging module (102) and a connecting cable. An FPGA circuit unit (204) of the debugging module is connected with a USB interface circuit unit (202) and a level conversion interface circuit unit, thus the communication between the PC machine and the flight control computer is established, and the PC machine monitors the operation state of a flight control computer system and debugs the flight control computer. When the flight control computer is changed, the PC machine downloads a corresponding FPGA program from the debugging module, modifies the control logic in the FPGA circuit unit, thus the definition of a signal output by the debugging module is corresponding to the definition of a debugging interface signal of the flight control computer. Without changing any hardware, the generality of system design and application expandability are realized. The monitoring and debugging system is suitable for hardware and software joint debugging of the flight control computer system based on a DSP processor, an out-field experiment and other occasions.

Description

A kind of portable monitoring debug system of flight control computer

Technical field

The utility model relates to the monitoring debugging technique field of aircraft, is specifically related to a kind of monitoring debug system of flight control computer.

Background technology

Flight control computer is the core component of tactical flying weapon control system, be used for realizing that integrated information is processed, Guidance Law calculates, pilot control, rudder system control, aim at navigation calculate, the integrated information processing of guidance-ignition etc., its information processing capability directly affects the control performance of tactical flying weapon, generally adopts high performance DSP(digital signal processor) chip finishes heavy information interaction and data processing work.Flight control computer generally is comprised of dsp chip CPU module, clock circuit, program memory ROM, data-carrier store RAM, I/O interface and power module etc. as a complete digital information processing system.

Integrated Development Environment can help the deviser to develop flight control computer application system based on DSP, it can be in the whole life cycle of flight control computer, especially in the development and design stage, for the deviser provides one to monitor flexibly, easily debugging acid, help the problem that exists in deviser's detection hardware circuit and the software program, finish comprehensive to the debugging of flight control computer software, hardware and system.

At present, the flight control computer development system based on DSP mainly contains two kinds of implementations: emulator in-circuit emulation mode and calculating add in board mode.Wherein, emulator in-circuit emulation mode is that the CPU emulation plug with emulator is inserted on the Target Board, utilizes the hardware resource such as CPU, storer of emulator, and the debugging software resource, finishes the debugging to ownership goal plate software and hardware.The emulator of this mode is generally provided by producer, price is comparatively expensive, and the hardware fault that can't get rid of by emulator Target Board, simultaneously, because the high speed requirement artificial head cable of DSP is as far as possible short, this just gives, and monitoring debugging flight control computer system brings great inconvenience in actual uniting and adjustment or outfield experiments.Calculating the add in board mode adopts the most universal PC and compatible thereof to develop DSP, the master-slave mode development system of formation take PC as main frame, take DSP as slave, PC and DSP adopt shared storage mode exchange message, and can utilize software and hardware resources and the peripherals of PC.This master-slave mode development system can not Offhost, need to open computer cabinet during debugging, and the artificial head cable can not be oversize, and these problems have limited its use in the debugging of outfield so that difficulty is carried in its transportation.

Summary of the invention

The invention technical matters to be solved is to utilize the FPGA technology to provide a kind of portable monitoring debug system for flight control computer, this system architecture is compact, and small volume transports easy to carry, and cost economic is suitable for using in On-line combined regulation or the outfield experiments.

The invention is that the technical scheme that its technical matters of solution adopts is:

A kind of portable monitoring debug system of flight control computer comprises PC, debugging module and stube cable, and debugging module is connected between PC and the debugged flight control computer;

Stube cable comprises USB cable, USB-Blaster cable and debugging cable;

Debugging module comprises FPGA circuit unit, JTAG configuration circuit unit, usb circuit unit and level shifter interface circuit unit, wherein, PC is connected by USB cable with the usb circuit unit of debugging module, and realizes communicating by letter between PC and debugging module by the USB interface that USB cable connects; PC is connected by the USB-Blaster cable with the JTAG configuration circuit unit of debugging module, and realizes that by the USB interface that the USB-Blaster cable connects PC is to the compiled FPGA program of debugging module download; The level shifter interface circuit unit of the debugging interface of flight control computer and debugging module is connected by the debugging cable, and by communicating by letter between debugging cable realization flight control computer and debugging module; The FPGA circuit unit links to each other with the level shifter interface circuit unit with the usb circuit unit, sets up communicating by letter of PC and flight control computer, realizes running status and the debugging flight control computer of PC monitoring flight control computer system;

When flight control computer changed, PC was downloaded corresponding FPGA program to debugging module, revised the steering logic in the FPGA circuit unit, made the signal of debugging module output corresponding with the debugging interface signal definition of flight control computer.

Further, debugging module also comprises SRAM circuit unit, EPCS series arrangement circuit unit, power supply and reset circuit unit and clock input and configuration circuit unit.

Further, when PC was communicated by letter with flight control computer, the FPGA circuit unit received the order of PC by the usb circuit unit, to command analysis, and analysis result was sent to flight control computer by the level shifter interface circuit unit; The FPGA circuit unit receives the data that flight control computer returns by the level shifter interface circuit unit, uploads to PC by the usb circuit unit.

Further, the FPGA circuit unit is detail programming order and operation debug command with command determination to command analysis the time.

Further, the detail programming order comprises that ROM reads, ROM writes, RAM reads, RAM writes, I/O reads and data erase.

Further, the operation debug command comprise that the operation of breakpoint setting, breakpoint, single step stop, single step run and debug reset.

Further, when carrying out the detail programming order, debugging module flight control computer processor is set to suspended state; When carrying out the operation debug command, debugging module flight control computer processor is set to the single step state.

In the invention, hardware components only is used for realizing connection and the electric conversion of signal, and the functions such as the monitoring of signal, debugging and demonstration are mainly realized by system software, and this functional software is so that the system development exploitation is flexible, and it is convenient to revise.Simultaneously, by in the debugging module of integrated design, adopting the FPGA circuit unit of configurable connection, when flight control computer adopts different microprocessors, only need to revise the steering logic in the FPGA circuit unit, so that the signal of exporting is corresponding with the interface signal definition of debugged object, and need not to do change on any hardware, thereby the extensibility that reaches the versatility of system and use.

In the invention, PC and debugging module use the USB interface swap data, adopt USB interface be consider that its communication speed is fast, to support that plug and play is connected connection with hot plug simple and easy to use.User monitoring program on the PC realizes the running status of monitoring flight control computer system and transmits the debugging control order to debugging module by USB interface.Flying on the debugging module controlled debugged program and received debugging control order realization to the debugging of flight control computer by USB interface, and uploads debug results to PC.

In the invention, FPGA debugging operations flight control computer processor is realized by program flow, wherein, the detail programming action type comprises that ROM reads, ROM writes, RAM reads, RAM writes, I/O reads with data erase etc., and operation debugging operations type comprises that breakpoint setting, breakpoint operation, single step stop, single step run and debug reset etc.Flight control computer processor internal processes stream mode comprises normal condition, suspended state and single step state, and corresponding detail programming is finished under suspended state, and the operation debugging is finished under the single step state.

Compared with prior art, the monitoring debug system that provides of the invention has the following advantages:

1, system architecture is simple, and volume is small and exquisite, is easy to carry, and is applicable to based on occasions such as the flight control computer system hardware and software uniting and adjustment of dsp processor and outfield experiments.

2, system monitoring debug function software implementation, flexible configuration for different debugged objects, only needs to revise the steering logic in the FPGA circuit unit, and need not to do change on any hardware, thereby the extensibility that reaches the versatility of system and use.

3, PC is communicated by letter with debugging module and is adopted multifunctional high speed USB2.0 control chip, and inside is integrated with the usb protocol engine, works in the synchronization fifo pattern, used the exchange of FIFO mechanism data, thereby improved data transfer speed, alleviated the burden of processor, optimized the resource of FPGA.

4, native system monitoring debug function is complete, is convenient to detect the problem that exists in the hardware circuit of flight control computer and the software program.Wherein, the detail programming action type comprises that ROM reads, ROM writes, RAM reads, RAM writes, I/O reads with data erase etc., and operation debugging operations type comprises that breakpoint setting, breakpoint operation, single step stop, single step run and debug reset etc.

Description of drawings

Accompanying drawing described herein is used to provide the further understanding to the invention, consists of the application's a part.Illustrative examples and explanation thereof are used for explaining the invention, do not consist of the improper restriction to the invention.Give in the accompanying drawing:

Fig. 1 is the flight control computer monitoring debug system structured flowchart of an embodiment of the invention;

Fig. 2 is the monitoring debug system debugging module structural representation of an embodiment of the invention;

Fig. 3 is the debugging module usb circuit schematic diagram of an embodiment of the invention;

Fig. 4 is the interior USB interface state of a control machine transition diagram of the FPGA of an embodiment of the invention;

Fig. 5 is user monitoring program flow diagram on the PC of an embodiment of the invention;

Fig. 6 flies to control the debugged program process flow diagram among the FPAG of an embodiment of the invention.

Embodiment

Below with reference to the drawings and specific embodiments, further specify the invention.

Fig. 1 has provided according to the flight control computer of an embodiment of the invention monitoring debug system and has formed situation, comprising: PC (notebook type) 101, debugging module 102, debugged flight control computer system 103 and stube cable.Wherein, debugging module 102 is connected between PC 101 and the debugged flight control computer system 103, debugging module 102 comprises and the configurable FPGA circuit unit 204 that is connected of debugger object, communicate by letter, download compiled FPGA program by USB-Blaster cable 212 by USB cable 211 between PC 101 and the debugging module 102, adopt between debugging module 102 and the flight control computer 103 and debug cable 213 and be connected.Simultaneously, the system user monitoring software realizes that at PC the FPGA debugging software downloads on the debugging module and moves.

Preferably, carry out data communication by USB cable 211 between PC 101 and the debugging module 102, being positioned at PC 101 ends is A type USB interface, is Type B USB interface 201 and be positioned at debugging module 102 ends; Both download compiled FPGA program by USB-Blaster cable 212, being positioned at PC 101 ends is A type USB interface, and the 10 core JTAG(Joint Test Action Group of debugging module 102 ends and FPGA, joint test action group) interface links to each other.Adopt debugging cable 213 to be connected between debugging module 102 and the debugged flight control computer 103, realize the mutual of address, data and control signal, debugging module 102 ends are 64 core connectors 206 of the double distribution of spacing 1.27mm, and model is JL10B64Z/JL10H64T; Flight control computer 103 ends are the 96 core connectors 301 that spacing 1.27mm three rows distribute, and model is JL10B96Z/JL10H96T.

In the present embodiment, by in the debugging module 102 of integrated design, adopting the FPGA circuit unit 204 of configurable connection, when flight control computer 103 adopts different microprocessors, only need to revise the steering logic in the FPGA circuit unit 204, so that the signal of exporting is corresponding with the interface signal definition of debugged object, and need not to do change on any hardware, thereby the extensibility that reaches the versatility of system and use.

Fig. 2 has provided the monitoring debug system debugging module structural representation according to an embodiment of the invention, comprising: JTAG configuration circuit unit 210, SRAM circuit unit 209, the reset circuit unit in FPGA circuit unit 204, usb circuit unit 202, the FPGA configuration circuit unit is EPCS series arrangement circuit unit 203, power supply and reset circuit unit 208, clock input and configuration circuit unit 205, level shifter interface unit 207.

Preferably, FPGA circuit unit 204 adopts the high performance Cyclone III fpga chip EP3C25Q240C8 of altera corp.This chip has the logical block (LE) of 25K, 66 M9K embedded memory modules, 66 18 * 18 multipliers, 4 phaselocked loops (PLL), the hardware resource that 215 user I/O etc. are abundant.Therefore, its inner embedded multiplier can be used for finishing multiplying at a high speed, has strengthened the digital processing ability of device; In-line memory can be used for carrying out the data transfer operation of cross clock domain, and the dirigibility that has greatly improved system has reduced the complicacy that designs; Numerous user I/O can realize being connected with the flexible of peripheral components.This fpga chip is distributed structure/architecture, and its online programmable characteristic and numerous user I/O provide very big convenience for system development and digital signal processing.

Preferably, FPGA configuration circuit unit comprises that JTAG online programmable configuration, EPCS series arrangement and configuration mode select, the complete layoutprocedure of device with experience reset, 3 processes such as configuration and initialization.The JTAG configuration mode can be realized the online programming to FPGA, namely uses .SOF(SRAM Object File) file disposes FPGA, but its configuration information power down namely loses, and is suitable for the FPGA program debug.Jtag interface is an industrywide standard, use IEEE Std 1149.1 joint boundary scan interface pins, comprise TDI(data inputs) pin, the output of TDO(data) pin, the control of TMS(pattern) pin and TCK(signal clock) pin, the JTAG configuration information is directly produced by Quartus II software, downloads via download cable.Altera FPGA supports that basically JTAG orders to dispose the mode of FPGA, and the JTAG configuration mode is all higher than other any mode priority.EPCS series arrangement mode adopts 16MB series arrangement chip EPCS16, by jtag interface the configuration data .JIC(JTAG Indirect Configuration File of FPGA) file downloads in the EPCS storer, then FPGA can automatically obtain data and dispose FPGA from EPCS when powering on.After this mode disposed, configuration information was stored among the config memory EPCS, and power down is not lost, program Solidification after being suitable for the FPGA program debug and finishing.Configuration mode is selected part by FPGA device pin MSEL[2:0 is set] signal condition, be used for determining configuration mode and electrification reset time.Owing under the JTAG pattern, can ignore the MSEL configuration, in order to guarantee that powering on of configuration information loads automatically, the FPGA configuration mode is set to initiatively series arrangement of Active serial (AS), is about to pin MSEL[2:0] level be set to low/high/low state.

Preferably, SRAM circuit unit 209 adopts chip I S61LV25616AL, for the FPGA digital signal processing provides data temporary.Reset circuit unit 203 produces the active homing pulse that a pulsewidth is not less than 100ms by the manual triggers mode, as the manual asynchronous reset signal of debugging module.Power-supply circuit unit 208 both can power by USB, also can external 5V DC power supply, and for debugging module provides various operating voltage such as 3.3V, 2.5V, 1.2V etc.Clock input circuit unit 205 adopts the active crystal oscillator of 24M, for FPGA provides high precision clock.Level shifting circuit unit 207 adopts level transferring chip 74LVX4245, realizes 3.3V and 5.0V level conversion, has guaranteed the signal level coupling of debugging module and flight control computer system.

Fig. 3 has provided the debugging module usb circuit schematic diagram according to an embodiment of the invention, adopts the multifunctional high speed USB2.0 control chip FT2232H of FTDI company.The FT2232H chip is mainly used to realize the bi-directional conversion of USB serial data format and parallel data form under the effect of internal hardware logic.PC carries out exchanges data by USB interface and FT2232H, and FT2232H then communicates by letter with fpga chip by parallel mode.Circuit employing+3.3V power supply, power end have increased decoupling and shunt capacitance to improve the interference free performance of circuit.Clock circuit adopts a 12MHz crystal oscillator and two 27pF electric capacity to form.Attached a slice eeprom chip 93C46 is used for the memory device parameter information, can be asynchronous serial pattern, synchronization fifo pattern or High Speed Serial with the passage separate configurations of each device.This interface FT2232H is set to the synchronization fifo pattern, only relates to A channel, pin CLKOUT output this moment 60MHz clock, and synchronous other signals, D0～D7 is data line, RXF#, TXE#, RD#, WR#, OE# are read-write control line.Can know by the state of PWREN# whether current USB is in suspended state, under suspended state, cannot carry out read-write operation.

Preferably, FT2232H is the 5th generation USB-to-UART/FIFO device that FTDI company releases, single-chip provides two to support USB2.0 high speed standard and configurable walking abreast/serial line interface, and can be operated under 9 kinds of patterns such as asynchronous serial port, synchronous 245FIFO, synchronous bit wide; Inside is integrated with the usb protocol engine, need not the firmware programs for the USB standard; Driver through the royalty-free of Microsoft certification is provided, has saved the time that exploitation drives; Transmission speed is different because of the difference of configuration mode, and transmission speed is greater than 25MB/s under single channel synchronization fifo pattern.

Preferably, operating system can be asked mounting equipment driving program when USB device is inserted PC, and FTDI company provides USB driver D2XX, can obtain better data transmission performance.PC only need call the function among the dynamic link libraries FT2232H.DLL when writing application program, just can finish the read-write operation to USB interface equipment.

Preferably, the data interaction between FT2232H and the FPGA is to be undertaken by the mode of inquiry, and Fig. 4 has provided according to USB interface state of a control machine transition diagram in the FPGA of an embodiment of the invention.Interface state of a control machine has 6 states, comprise idle condition Idle, read USB fifo status Read_fifo, write USB fifo status Write_fifo, command analysis state Command_check, read Flash state Read_flash and write Flash state Write_flash, its reset signal pattern is asynchronous reset.By inquiry or the state of control signal RXF#, TXE#, the FT2232H device works in the synchronization fifo pattern, carries out exchanges data with Flash storer among the FPGA.USB interface control has been owing to used FIFO mechanism, thereby improves data transfer speed, and alleviates the burden of processor, optimized the resource of FPGA.

Preferably, PC is assigned the duty of debugging control order and monitoring flight control computer processor to debugging module by user program, Fig. 5 has provided according to user monitoring program flow diagram on the PC of an embodiment of the invention, comprises the opening/closing USB device, flies the debug command of control-register journey and flies control operation debug command.Wherein, fly that the debug command of control-register journey comprises that ROM reads, ROM writes, RAM reads, RAM writes, I/O reads, data erase and data check etc.; Fly that control operation debug command comprises that breakpoint setting, breakpoint operation, single step stop, single step run and debug reset etc.Preferably, PC user monitoring program adopts the LabWindows/CVI Development of Software Platform of NI company, to convert executable binary file (BIN file) to the program (asm file) of compilation language compilation, reach FPGA by under the usb communication first, and then by the operation of FPGA write order, send it to flight control computer system.

Preferably, adopt Verilog HDL hardware description language to realize debugging sequential to flight control computer, and then compilation and synthesis download among the FPGA and move in Quartus II SDK (Software Development Kit).Fig. 6 has provided among the FPAG according to an embodiment of the invention and has flown to control the debugged program process flow diagram.FPGA flies to control debugged program acquires PC by USB interface debug command, then debug command is resolved, judge debug command type and corresponding debugging operations, wherein accessible detail programming action type comprises that ROM reads, ROM writes, RAM reads, RAM writes, I/O reads with data erase etc., and operation debugging operations type comprises that breakpoint setting, breakpoint operation, single step stop, single step run and debug reset etc.Corresponding debugging operations is realized by the program flow of operation and control flight control computer processor, its internal processes stream mode comprises normal condition, suspended state and single step state, corresponding detail programming is finished under suspended state, and the operation debugging is finished under the single step state, the flight control computer processor is carried out according to normal sequence under normal mode always continuously.

Preferably, the FPGA debugging module makes it enter suspended state by flight control computer processor HOLD/HOLDA agreement, realizes the detail programming process: the bus control right of at first obtaining processor by the HOLD/HOLDA agreement; Second step is powered the program voltage of EPROM by order from low to high; The blank inspection of the 3rd step EPROM; The programming of the 4th step; The 5th step verification; The 6th step was cancelled the program voltage of EPROM by order from high to low; Abandon at last bus control right.

Preferably, the FPGA debugging module makes it enter the single step state by flight control computer processor STOP waiting status, realizes the operation debug process: the model breakpoint condition, in the breakpoint address writing address storer of setting; Secondly when condition meets, produce immediately the STOP signal, make processor be in waiting status; Then carry out site disposal, the running status of monitoring processor, content and the situation of change of checking related register; Cancel at last the STOP signal, remove the waiting status of processor, recover its normal operation.

Claims (1)

1. the portable monitoring debug system of a flight control computer, comprise PC (101), debugging module (102) and stube cable, debugging module (102) is connected between PC (101) and the debugged flight control computer (103); It is characterized in that:

Stube cable comprises USB cable (211), USB-Blaster cable (212) and debugging cable (213);

Debugging module (102) comprises FPGA circuit unit (204), JTAG configuration circuit unit (210), usb circuit unit (202) and level shifter interface circuit unit (207), wherein, PC (101) is connected by USB cable (211) with the usb circuit unit (202) of debugging module, and realizes communicating by letter between PC (101) and debugging module (102) by the USB interface that USB cable connects; PC (101) is connected by USB-Blaster cable (212) with the JTAG configuration circuit unit (210) of debugging module, and realizes that by the USB interface that the USB-Blaster cable connects PC is to the compiled FPGA program of debugging module download; The level shifter interface circuit unit (207) of the debugging interface of flight control computer and debugging module is connected by debugging cable (213), and by communicating by letter between debugging cable (213) realization flight control computer and debugging module; FPGA circuit unit (204) links to each other with level shifter interface circuit unit (207) with usb circuit unit (202), set up communicating by letter of PC (101) and flight control computer (103), realize running status and the debugging flight control computer of PC monitoring flight control computer system.

2, the portable monitoring debug system of flight control computer according to claim 1 is characterized in that: debugging module also comprises SRAM circuit unit (209), EPCS series arrangement circuit unit (203), power supply and reset circuit unit (208) and clock input and configuration circuit unit (205).

3, the portable monitoring debug system of flight control computer according to claim 1, it is characterized in that: PC (101) and flight control computer (103) are when communicating by letter, FPGA circuit unit (204) receives the order of PC (101) by usb circuit unit (202), to command analysis, and analysis result sent to flight control computer (103) by level shifter interface circuit unit (207); FPGA circuit unit (204) receives the data that flight control computer (103) returns by level shifter interface circuit unit (207), uploads to PC (101) by usb circuit unit (202).

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