CN202750101U - Ethernet message processor - Google Patents
Ethernet message processor Download PDFInfo
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- CN202750101U CN202750101U CN 201220438052 CN201220438052U CN202750101U CN 202750101 U CN202750101 U CN 202750101U CN 201220438052 CN201220438052 CN 201220438052 CN 201220438052 U CN201220438052 U CN 201220438052U CN 202750101 U CN202750101 U CN 202750101U
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- ethernet
- protective circuit
- message processor
- processor
- ethernet message
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Abstract
The utility model discloses an Ethernet message processor used for Ethernet link connection, and the Ethernet message processor comprises a data forwarding module and a processor, and the processor is connected with the data forwarding module; the Ethernet message processor also comprises a protection circuit, the protection circuit comprises at least a node, any single node comprises two Ethernet ports, a relay, and two PHY chips, the two Ethernet ports are correspondingly connected with the two PHY chips through the relay, the two Ethernet ports are also connected, and the two PHY chips are both connected with the data forwarding module. A technical effect is that the Ethernet message processor can guarantee physical layer connection of the Ethernet link not to be flash-broken under conditions of faults, power off, or re-power on, so up-lever businesses are not affected.
Description
Technical field
The utility model relates to a kind of Ethernet message processor for the ethernet link connection.
Background technology
Developing rapidly of Gigabit Ethernet technology is so that the network change is huge, complicated.Network manager need to carry out multiple work in the situation of interrupt network not, comprising: check network performance, get rid of network failure, phase-split network flow etc.Above-mentioned functions is all finished with the Ethernet splitter usually.But general Ethernet splitter has following shortcoming:
The first, the Ethernet splitter breaks down or during power down, the flash phenomenon can appear in the physical layer connection of link, thereby affects upper-layer service;
The second, check network performance, when getting rid of network failure, phase-split network flow, can't make amendment to the data on the network, can't the finishing service operation.
The above-mentioned shortcoming of Ethernet splitter has all seriously restricted the popularization of Ethernet to use.
The utility model content
The purpose of this utility model is in order to overcome the deficiencies in the prior art, a kind of Ethernet message processor is provided, and it has overcome the shortcoming of traditional splitter, can be in the situation of fault or power down, the physical layer connection that guarantees ethernet link the flash phenomenon can not occur, thereby does not affect upper-layer service.
A kind of technical scheme that realizes above-mentioned purpose is: a kind of Ethernet message processor, comprise data forwarding module and processor, and described processor connects described data forwarding module; Described Ethernet message processor also comprises protective circuit; described protective circuit comprises at least one node; any one described node all comprises two Ethernet interfaces, a relay and two PHY chips; described two Ethernet interfaces are connected with described two PHY chips correspondingly by described relay; also connect between described two Ethernet interfaces, described two PHY chips all are connected with described data forwarding module.
Further; on any one node of described protective circuit; described two Ethernet interfaces be connected two PHY chips and connect correspondingly by the first data/address bus that is positioned at described relay, connect by the second data/address bus that is positioned at described relay between described two Ethernet interfaces.
Further, described Ethernet message processor also comprises the protective circuit control module, and described protective circuit control module connects respectively described protective circuit and described processor.
Further, the built-in buffer memory of described protective circuit control module.
Further, described protective circuit control module is connected with each PHY chip with each relay on the described protective circuit by the MIDO bus.
Adopted the technical scheme of a kind of Ethernet message processor of the present utility model; namely increased protective circuit at described Ethernet message processor; this protective circuit comprises at least one node, and each node comprises two Ethernet interfaces, a relay and two PHY chips.Its technique effect is: described Ethernet Message Processing function fault, power down or on again in the situation of electricity, the physical layer that guarantees ethernet link connects the flash phenomenon can not occur, thereby does not affect upper-layer service.
Description of drawings
Fig. 1 is the structural representation of a kind of Ethernet message processor embodiment of the present utility model.
Fig. 2 is the serial connection communication scheme of a kind of Ethernet message processor embodiment of the present utility model.
Fig. 3 is the communication scheme that converges of a kind of Ethernet message processor embodiment of the present utility model.
Embodiment
See also Fig. 1 to Fig. 3, inventor of the present utility model be in order to understand the technical solution of the utility model better, below by embodiment particularly, and is described in detail by reference to the accompanying drawings:
See also Fig. 1 and Fig. 2, a kind of Ethernet message processor of the present utility model comprises protective circuit 1, data forwarding module 2, processor 3.Described protective circuit 1 comprises two nodes 10, and each node 10 comprises a relay 11, two Ethernet interfaces 13 and two PHY chips 12.Described PHY chip 12 is called again physical chip.Connect by the second data/address bus 15 that is positioned at described relay 11 between described two Ethernet interfaces 13, described two Ethernet interfaces 13 are connected with described two PHY chips 12 correspondingly by the first data/address bus 14 that is positioned at described relay 11.Described two PHY chips 12 all connect described data forwarding module 2, make described protective circuit 1 connect described data forwarding module 2.Described data forwarding module 2 connects described processor 3.
The purpose of design is like this: when the Ethernet message processor works; on any one node 10 of described protective circuit 1; any one from this node 10 of packet be the described Ethernet message processor of network interface 13 inputs too; transmission through described the first data/address bus 14; this packet is stored on the PHY chip 12 corresponding with this Ethernet interface 13; described data forwarding module 2 reads this packet from this PHY chip 12, and carries out data for described processor 3 this package forward and process.This packet is through after the processing of described processor 3, write an other PHY chip 12 on this node 10 by described data forwarding module 2 again, then, treated packet is the transmission by the first data/address bus 14 again, from Ethernet interface 13 outputs corresponding with this PHY chip 12.Like this, two Ethernet interfaces 13 on any one node 10 of described protective circuit 1 are communicated with letter between can realizing by described data forwarding module 2 and described processor 3.The transmission path of packet this moment in described the first data/address bus 14 represents with solid arrow in Fig. 2.
When described Ethernet message processor fault or power down, the relay 11 on described protective circuit 1 whole nodes 10 all can autoshutdown, and the first data/address bus 14 of described relay 11 inside cuts off.Simultaneously, the second data/address bus 15 in the described relay 11 is communicated with.Two Ethernet interfaces 13 on described protective circuit 1 arbitrary node 10 directly communicate.Transmission path among Fig. 2 the with dashed lines arrow of packet this moment in described the second data/address bus 15 represents.
Like this, described Ethernet message processor just can in fault, power down or situation about re-powering, guarantee that the physical layer connection of ethernet link flash can not occur, thereby not affect upper-layer service.
In the present embodiment, the bandwidth of described Ethernet interface 13 is 1000Mbit.
In the present embodiment, the effect of described data forwarding module 2 is: the additional IP address of read data packet and this packet the PHY chip 12 from described protective circuit 1 any one node 10, and IP address additional on this packet and this packet is transmitted to processor 3 carries out data and process; Then receive the IP address that adds on the packet processed through described processor 3 and the packet, and according to the IP address that will add on this packet, described packet is write another piece PHY chip 12 on this node 10, finish the forwarding of packet.
Described processor 3 comprises data operator and controller, after described processor 3 receives described packet from described data forwarding module 2, by described arithmetic unit described packet is carried out data and processes.Then, the packet after described processor 3 will be processed is passed described data forwarding module 2 back.The data that described arithmetic unit carries out are processed and are comprised data interception, data insertion and data modification etc.
Described controller is mainly used to inquire about, arrange the state of described protective circuit 1.Guarantee described Ethernet Message Processing function in fault, power down or situation about re-powering, the physical layer that guarantees ethernet link connects the flash phenomenon can not occur, thereby does not affect upper-layer service.
Described Ethernet message processor also comprises protective circuit control module 4, and described protective circuit control module 4 connects respectively described protective circuit 1 and described processor 3.Described protective circuit control module 4 is connected with each relay 11 and each PHY chip 12 on the described protective circuit 1 by the MDIO bus.
The order that described protective circuit control module 4 receives from the controller of described processor 3, and these orders are converted into electronic signal, control relay 11 opening and closing on the described protective circuit 1.
Described protective circuit control module 4 also has by described MDIO bus; each PHY chip 12 on the described protective circuit 1 is carried out the function that parameter arranges; guarantee described Ethernet message processor in power down, fault or situation about re-powering, the physical layer of ethernet link connects flash does not occur.In the situation of described Ethernet message processor power down; described protective circuit control module 4 is closed the relay 11 on described protective circuit 1 all nodes 10; the first data/address bus 14 in these relays 11 cuts off; the second data/address bus 15 in these relays 11 is communicated with; carry out direct-connected communication between two Ethernet interfaces 13 on described like this protective circuit 1 arbitrary node 10, the link connection of described Ethernet message processor flash can not occur.
The Ethernet message processor powers on; the order that described protective circuit control module 4 receives from the controller of described processor 3; read the information in each PHY chip 12; and these information are stored in the buffer memory that is built in described protective circuit control module 4, simultaneously each PHY chip 12 is carried out the parameter setting.Then, open the relay 11 on described protective circuit 1 each node 10, the second data/address bus 15 in these relays 11 cuts off, and the first data/address bus 14 in these relays 11 is communicated with.Like this, two Ethernet interfaces 13 of arbitrary node 10 on the described protective circuit 1 undertaken by described data forwarding module 2 and described processor 3 between be communicated with letter and recover, the ethernet link of described Ethernet message processor connects and flash do not occur.
Therefore, the process of the relay 11 opening and closing process between the physical signalling of the physical signalling of Ethernet and PHY chip 12, switched of described relay 11 namely on a kind of Ethernet message processor of the present utility model.
Above content all is the explanation to described message processor serial connection communication function.
See also Fig. 3, a kind of Ethernet message processor of the present utility model also has the function of the communication of converging.When described Ethernet message processor normal operation, wherein three Ethernet interfaces 13 receive the packet that Ethernet is inputted, the data that Ethernet interface 13 is processed through described processor 3 to Ethernet output.Packet from 13 inputs of three Ethernet interfaces, the data that the forwarding of the described data processing module 2 of process and the arithmetic unit of described processor 3 carry out are processed, finally in described data forwarding module 2, finish and converge, and from a remaining Ethernet interface 13 outputs of this Ethernet message processor.The transmission path of packet this moment in described Ethernet message processor represents with solid arrow in Fig. 3.In the present embodiment, the bandwidth of four Ethernet interfaces is 1000Mbit.Three real data flows that receive the Ethernet interface 13 of Ethernet input packet are at most 1/3rd of its bandwidth.
When described Ethernet message processor fault or power down, relay 11 on two nodes 10 all can autoshutdown, on any one node 10, the first data/address bus 14 between described two Ethernet interfaces 13 and the described two PHY chips 12 all disconnects, the second data/address bus 15 between described two Ethernet interfaces 13 is communicated with, the transmission path of packet this moment in described the second data/address bus 15 also among available Fig. 2 the with dashed lines arrow represent.
Those of ordinary skill in the art will be appreciated that, above embodiment illustrates the utility model, and be not to be used as restriction of the present utility model, as long as in connotation scope of the present utility model, all will drop in claims scope of the present utility model variation, the modification of the above embodiment.
Claims (5)
1. an Ethernet message processor comprises data forwarding module (2) and processor (3), and described processor (3) connects described data forwarding module (2); It is characterized in that: described Ethernet message processor also comprises protective circuit (1); described protective circuit (1) comprises at least one node (10); any one described node (10) all comprises two Ethernet interfaces (13); a relay (11) and two PHY chips (12); described two Ethernet interfaces (13) are connected with described two PHY chips (12) correspondingly by described relay (11); also connect between described two Ethernet interfaces (13), described two PHY chips (12) all are connected with described data forwarding module (2).
2. a kind of Ethernet message processor according to claim 1; it is characterized in that: on any one node (10) of described protective circuit (1); described two Ethernet interfaces (13) be connected two PHY chips (12) and connect correspondingly by the first data/address bus (14) that is positioned at described relay (11), connect by the second data/address bus (15) that is positioned at described relay (11) between described two Ethernet interfaces (13).
3. a kind of Ethernet message processor according to claim 1 and 2; it is characterized in that: described Ethernet message processor also comprises protective circuit control module (4), and described protective circuit control module (4) connects respectively described protective circuit (1) and described processor (3).
4. a kind of Ethernet message processor according to claim 3 is characterized in that: the built-in buffer memory of described protective circuit control module (4).
5. a kind of Ethernet message processor according to claim 3 is characterized in that: described protective circuit control module (4) is connected with each PHY chip (12) with each relay (11) on the described protective circuit (1) by the MIDO bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220438052 CN202750101U (en) | 2012-08-30 | 2012-08-30 | Ethernet message processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220438052 CN202750101U (en) | 2012-08-30 | 2012-08-30 | Ethernet message processor |
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| Publication Number | Publication Date |
|---|---|
| CN202750101U true CN202750101U (en) | 2013-02-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220438052 Expired - Fee Related CN202750101U (en) | 2012-08-30 | 2012-08-30 | Ethernet message processor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027282A (en) * | 2016-04-28 | 2016-10-12 | 深圳市恒扬数据股份有限公司 | Network probe for preventing link interruption and network probe method |
| CN103747068B (en) * | 2013-12-27 | 2017-07-18 | 珠海市佳讯实业有限公司 | A kind of system that TAP functions of the equipments are realized based on FPGA |
-
2012
- 2012-08-30 CN CN 201220438052 patent/CN202750101U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103747068B (en) * | 2013-12-27 | 2017-07-18 | 珠海市佳讯实业有限公司 | A kind of system that TAP functions of the equipments are realized based on FPGA |
| CN106027282A (en) * | 2016-04-28 | 2016-10-12 | 深圳市恒扬数据股份有限公司 | Network probe for preventing link interruption and network probe method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130220 Termination date: 20170830 |