CN108616370A - A kind of RapidIO exchange networks Dynamic Configuration - Google Patents
A kind of RapidIO exchange networks Dynamic Configuration Download PDFInfo
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- CN108616370A CN108616370A CN201611140250.0A CN201611140250A CN108616370A CN 108616370 A CN108616370 A CN 108616370A CN 201611140250 A CN201611140250 A CN 201611140250A CN 108616370 A CN108616370 A CN 108616370A
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- rapidio
- exchange
- configuration
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- dynamic configuration
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention belongs to onboard networks bussing technique fields, and a kind of RapidIO exchange networks Dynamic Configuration is proposed based on RapidIO exchange networks.The design scheme core of the present invention is the signal processing system based on RapidIO exchange networks, using PowerPC8548E as I2The main equipment of C completes the power-up initializing of RapidIO exchange chips, and using packet is safeguarded in system operation, dynamic configuration is carried out to RapidIO exchange chips, realizes online dynamic configuration RapidIO routings.By establishing the window mapping relations of each equipment DMA addressing spaces in exchange network, the communication efficiency between equipment is improved.
Description
Technical field
The invention belongs to onboard networks bussing technique fields, and a kind of RapidIO friendships are proposed based on RapidIO exchange networks
Switching network Dynamic Configuration.
Background technology
Signal processing system involved in the present invention be certain emphasis model aircraft avionics system at comprehensive core
The critical system of reason machine (ICP).Signal processing module (SPM) completes the processing work of the photoelectricity tasks such as the IRST and DAS of system.
Each module has independent 5 channel FC transmission and signal processing channel, what preceding 4 tunnel completion was connect with front end sensors point-
The processing task of signal, the 5th tunnel processing access are completed signal rear end integrated treatment and are connect with the NSM interchangers of ICP.
Signal processing system is based on RapidIO exchange networks, and inside uses unified RapidIO exchanging interconnection networks, hands over
Change the 80HCPS18xx series RapidIO exchange chips CPS1848 that chip uses Integrated Device Technology, Inc..CPS1848 supports serial
RapidIO2.1 standards have 48 two-way data differences pair, can be configured to tri- kinds of port modes of 1x, 2x and 4x, at most may be used
To be configured to 18 1x or 12 ports 4x, per line rate could be provided as 1.25Gbit/s, 2.5Gbit/s,
3.125Gbit/s, 5Gbit/s or 6.25Gbit/s.CPS1848 tools can be used for completing there are one standard I2C interface
The initial configuration of CPS1848, can also by the interface obtain CPS1848 internal registers come working condition.
The dsp chip TMS320C6455 with serial RapidIO interfaces released using 5 Texas Instruments
Unit as data processing.Each dsp processor realizes that the RapidIO interfaces of 1 road 4x are connected to inner exchanging network, works
Rate 2.5Gbps realizes high-speed interconnection of data communication.
1 set of PowerPC processing circuit is finally separately configured, is responsible for the control management function of entire module, processor is selected
PowerPC8548E, the Power PC Processor are realized the RapidIO interfaces of 1 road 4x, are connected on inner exchanging network, realize
It is communicated with the data of other nodes in exchange network.
In addition the post-processing that three pieces of FPGA are used for data is configured, realizes the RapidIO interfaces of 6 road 2x.
The processing work that 2 pieces of SPM modules complete the photoelectricity tasks such as the IRST and DAS of system is configured in signal processing system
Make, realizes that high speed interconnects by the RapidIO interfaces of 2 road 2x between SPM modules, independent 2 modules of physics are realized, according to place
Manage the adaptable processing framework of the demand structure of task system, topological structure such as Fig. 1 of signal processing module.Signal processing system
Based on RapidIO exchange networks, the end node in network is using between unified RapidIO exchanging interconnection real-time performance equipment
Communication realizes the high-speed traffic of the dynamic configuration and each end node of network according to the demand of application, to entire in system operation
The performance of signal processing system has extremely important influence.
Invention content
The present invention proposes a kind of RapidIO exchange networks Dynamic Configuration, realizes the dynamic configuration of network and each end segment
The high-speed traffic of point.
A kind of RapidIO exchange networks Dynamic Configuration, RapidIO exchange chips CPS1848 tools in the method
There are three types of configuration modes：
It is configured first, being realized by standard JTAG, is suitable for debugging link；
Second is that using I2C interface completes the power-up initializing configuration of exchange chip CPS1848, with exchange chip CPS1848
For reference, there are two kinds of configuration modes of principal and subordinate；
Third, being configured to exchange chip CPS1848 by RapidIO attended operations, power-up initializing can be completed and matched
Set the function of being reconfigured with real-time online.
Using PowerPC8548E as I in this method2The main equipment mode of C completes powering on for CPS1848 exchange chips
Initialization, completes initialization and the routing configuration of entire RapidIO exchange networks on PowerPC8548E.Again using maintenance behaviour
Work configures into RapidIO exchange chips the real-time dynamic configuration of exchange chip.
Accessing by the way of direct memory access between each equipment of exchange network, passes through in this method
The mapping of outband/inband windows realizes the direct memory access operation between equipment so that the communication between equipment
Efficiency is greatly improved.
It is characteristic of the invention that implementation method is simple, using flexible is this to change chip routing by Configuration Online dynamic
The method of configuration makes whole system be obtained in performance indicators such as reconfigurability, scalability, maintainabilitys and significantly changes
Kind, dma operation improves the communication efficiency between equipment.
Description of the drawings
The topological structure of signal processing system is as shown in Figure 1.
It is as shown in Figure 2 that exchange network initializes flow.
Specific implementation mode
This programme implementation steps are as follows：
1.PowerPC8548E completing initialization and the routing configuration of entire RapidIO exchange networks, use
PowerPC8548E is as I2The main equipment mode of C realizes CPS1848 in the power-up initializing for completing RapidIO exchange chips
The basic setups such as the port working pattern of exchange chip, routing table improve system effect to simplify the initialization flow of system
Rate.
Initialization flow is as follows, and detailed process is referring to Fig. 2
1) after system electrification, os starting；
2) using PowerPC8548E as I2C main equipments complete I2The initialization of C interface；
3) pass through I2C interface completes the basic setups such as the port working pattern of CPS1848 exchange chips, routing table；
4) resource that attended operation uses is created；
5) DOORBELL interrupt resources are initialized；
6) each end node configures outband/inband windows, searches available ATMU on PowerPC8548E, according to system
System defines the outband/inband address of cache of each end node and PowerPC8548E in Configuration network, completes in exchange network
Each end node DMA addressing spaces window mapping relations foundation；
7) network configuration when starting according to system, the netinit that system is completed by attended operation work.2.
In whole system operational process, according to the requirement of application, CPS1848 exchange chips are configured using attended operation, are realized
The real-time dynamic configuration of CPS1848 exchange chips.
In RapidIO exchange networks, completed by RapidIO attended operations by the either host of access system entire
The initialization and monitoring management of system work.RapidIO attended operations can be to arbitrary end segment in entire RapidIO network systems
The real time access control of the RapidIO capabilities registers of point and exchange device, status register and data structure.
RapidIO attended operations, which use, safeguards that packet protocol implements arbitrary end node in RapidIO networks and exchanges device
Configuration, RapidIO safeguard that " hop count " field in packet defines the quantity for exchanging device in RapidIO systems, exchange device and connect
It receives and safeguards that Bao Shihui checks that hop count field shows that the target of the operation is exactly to exchange device if it is " 0 "；If not being
" 0 " exchanges device and subtracts 1 by hop count field value, and will safeguard that packet is forwarded according to the routing table of interface port.Pass through this side
Formula, any one end equipment in RapidIO systems can realize configuration and management to whole network.
Symbol description：
SPM:Signal processing module；
ICP:Comprehensive core processor；
DMA：Direct memory access.
Claims (2)
1. a kind of RapidIO exchange networks Dynamic Configuration, RapidIO exchange chips CPS1848 in the method has
Three kinds of configuration modes：
It is configured first, being realized by standard JTAG, is suitable for debugging link；
Second is that using I2C interface completes the power-up initializing configuration of exchange chip CPS1848, is ginseng with exchange chip CPS1848
It examines, there is two kinds of configuration modes of principal and subordinate；
Third, configured to exchange chip CPS1848 by RapidIO attended operations, can complete power-up initializing configuration and
The function that real-time online reconfigures；It is characterized in that
Using PowerPC8548E as I in this method2It is initial that the main equipment mode of C completes powering on for CPS1848 exchange chips
Change, initialization and the routing configuration of entire RapidIO exchange networks are completed on PowerPC8548E；Attended operation pair is used again
RapidIO exchange chips are configured into the real-time dynamic configuration of exchange chip.
2. a kind of RapidIO exchange networks Dynamic Configuration as described in claim 1, characterized in that exchanged in this method
Accessing by the way of direct memory access between each equipment of network, by the mapping of outband/inband windows,
Realize the direct memory access operation between equipment.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611140250.0A CN108616370B (en) | 2016-12-12 | 2016-12-12 | RapidIO switching network dynamic configuration method |
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| CN201611140250.0A CN108616370B (en) | 2016-12-12 | 2016-12-12 | RapidIO switching network dynamic configuration method |
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| CN108616370A true CN108616370A (en) | 2018-10-02 |
| CN108616370B CN108616370B (en) | 2021-08-03 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109474532A (en) * | 2018-10-09 | 2019-03-15 | 天津市滨海新区信息技术创新中心 | A kind of RapidIO switch equipment managing method and system |
| CN111400228A (en) * | 2020-02-24 | 2020-07-10 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Method and system for integrating RapidIO transmission in DDS communication middleware |
| CN112214446A (en) * | 2020-09-28 | 2021-01-12 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Board-level RapidIO network management circuit and network management method |
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| CN103970704A (en) * | 2014-04-16 | 2014-08-06 | 上海电控研究所 | Optical fiber bus hardware system based on Rapid IO protocol |
| CN105824366A (en) * | 2016-03-21 | 2016-08-03 | 浪潮集团有限公司 | Large-capacity high-speed recording board card on basis of Rapid IO (Input-Output) |
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| CN103970704A (en) * | 2014-04-16 | 2014-08-06 | 上海电控研究所 | Optical fiber bus hardware system based on Rapid IO protocol |
| CN105824366A (en) * | 2016-03-21 | 2016-08-03 | 浪潮集团有限公司 | Large-capacity high-speed recording board card on basis of Rapid IO (Input-Output) |
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| ZHANG-XIUZHI: "Rapid IO 接口", 《CSDN》 * |
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| 马友科: "基于CPS1848的SRIO总线交换模块设计", 《专题技术与工程应用》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109474532A (en) * | 2018-10-09 | 2019-03-15 | 天津市滨海新区信息技术创新中心 | A kind of RapidIO switch equipment managing method and system |
| CN111400228A (en) * | 2020-02-24 | 2020-07-10 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Method and system for integrating RapidIO transmission in DDS communication middleware |
| CN112214446A (en) * | 2020-09-28 | 2021-01-12 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Board-level RapidIO network management circuit and network management method |
| CN112214446B (en) * | 2020-09-28 | 2023-05-12 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Board-level rapidIO network management circuit and network management method |
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| CN108616370B (en) | 2021-08-03 |
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