CN202736613U - Wafer resistor - Google Patents
Wafer resistor Download PDFInfo
- Publication number
- CN202736613U CN202736613U CN 201220187892 CN201220187892U CN202736613U CN 202736613 U CN202736613 U CN 202736613U CN 201220187892 CN201220187892 CN 201220187892 CN 201220187892 U CN201220187892 U CN 201220187892U CN 202736613 U CN202736613 U CN 202736613U
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- Prior art keywords
- wafer resistor
- substrate
- electrode
- insulated substrate
- layer
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- Expired - Fee Related
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Abstract
The utility model provides a wafer resistor which comprises an insulation base plate, a pair of terminal electrodes, a resistor body and a protective layer. The insulation base plate is provided with a lower surface, and the pair of terminal electrodes is formed on the lower surface of the insulation base plate. The resistor body is formed on the lower surface of the insulation base plate, and is arranged between the terminal electrodes, and two ends of the resistor body are in electric connection with the terminal electrodes. The protective layer is formed on the resistor body. The wafer resistor is suitable for being welded on a land grid array (LGA) welding pad, and is beneficial to improving the density of electronic components on a circuit board.
Description
Technical field
The utility model is about a kind of wafer resistor (chip resistor), relates in particular to the wafer resistor on a kind of Land Grid Array (land grid array, LGA) weld pad that is applicable to be welded on circuit board.
Background technology
Seeing also Fig. 1, is the sectional view of a traditional wafer resistor 1.Wafer resistor 1 is welded on circuit board 2.
As shown in Figure 1, traditional wafer resistor 1 comprises insulated substrate 10, pair of end electrode (12,14), resistive element 16 and protective layer 18.This is respectively formed on the two relative surfaces (102,104) of insulated substrate 10 termination electrode (12,14), and extends to upper surface 106 and the lower surface 108 of insulated substrate 102.Resistive element 16 is formed on the upper surface 108 of insulated substrate 10, and the two ends of resistive element 16 are covered respectively the realization electric connection to termination electrode (12,14) by this.Protective layer 18 is formed on the resistive element 16, and can be as marking layer.
This of wafer resistor 1 is placed on respectively on the weld pad (22,24) of circuit board 2 termination electrode (12,14), and utilizes respectively scolding tin 30 to be welded on the weld pad (22,24).Yet, this kind exists certain defect with the mode that wafer resistor 1 is welded on circuit board 2, wafer resistor 1 adds that scolding tin 30 namely occupies many spaces, the scolding tin 30 that exposes allows other electronic components of adjacent wafer resistor 1 must leave larger spacing on the circuit board 2, to avoid forming short circuit in welding process and wafer resistor 1.Therefore, traditional wafer resistor 1 is unfavorable for that the electronic component density of circuit board 2 promotes.
The available circuit plate is in order to promote electronic component density on it, and the weld pad on it has adopted the LGA weld pad.And traditional wafer resistor 1 and inapplicable being welded on the LGA weld pad.
The utility model content
In order to promote the density of electronic component on the circuit board, further improve the utilization rate of circuit board, therefore need structure and the corresponding welding manner of electronic component are improved, the utility model just provides the wafer resistor on a kind of Land Grid Array weld pad that is applicable to be welded on circuit board.
The utility model discloses a kind of wafer resistor, it comprises: insulated substrate has a lower surface; The pair of end electrode is formed on this lower surface of this insulated substrate; Resistive element is formed on this lower surface of this insulated substrate, and its position is in this between the termination electrode, and the two ends of this resistive element are electrically connected respectively this to termination electrode; And protective layer, be formed on this resistive element.
The gross thickness of this resistive element and this protective layer stack is no more than the thickness of each termination electrode in described wafer resistor.
All there is a gap at the edge of this lower surface of each termination electrode and this insulated substrate in described wafer resistor.
This insulated substrate has a upper surface relative with this lower surface in described wafer resistor, and this wafer resistor also comprises a marking layer, is formed on this upper surface of this insulated substrate.
In described wafer resistor each termination electrode consist of in the better metal of gold, silver, copper, nickel, tin or other conductivity any one, or be any alloy behind the multiple combination in the above-mentioned metal.
This insulated substrate is by SiN, Si3N4 in described wafer resistor,, any one or various material among SiO2, SiC, Al2O3 and the AlN be made.
The utility model discloses again another kind of wafer resistor, and it comprises: insulated substrate has a lower surface and a upper surface relative with this lower surface; Resistive element is on this upper surface that is formed on this insulated substrate; Protective layer is for being formed on this resistive element; The pair of end electrode is formed on this lower surface of this insulated substrate, and each termination electrode is respectively to end one of in should the two ends of resistive element; And a pair of perforation conductor, being formed in this insulated substrate and running through this insulated substrate, each perforation conductor is electrically connected respectively a wherein end of a termination electrode and this resistive element.
All there is a gap at the edge of this lower surface of each termination electrode and this insulated substrate in described wafer resistor.
Each termination electrode is made by any one material in the better metal of gold, silver, copper, nickel, tin or other conductivity in described wafer resistor, or is any alloy behind the multiple combination in the above-mentioned metal.
This insulated substrate is by SiN, Si3N4 in described wafer resistor,, any one or various material among SiO2, SiC, Al2O3 and the AlN be made.
This insulated substrate is consisted of by being stacked by the multi-layer ceramics layer in described wafer resistor.
In described wafer resistor each perforation conductor serve as reasons be formed at sub-perforation conductor in every one deck ceramic layer stack consist of.
Every one deck ceramic layer is by SiN, Si3N4 in described wafer resistor,, any one or various material among SiO2, SiC, Al2O3 and the AlN be made.
Compared with prior art, wafer resistor provided by the utility model is applicable to be welded on the LGA weld pad, is beneficial to the density that promotes electronic component on the circuit board.
Description of drawings
Fig. 1 is the structural representation of traditional wafer resistor.
Fig. 2 is the structural representation of wafer resistor in the utility model one preferred embodiment.
Fig. 3 is the lower view of wafer resistor among Fig. 2.
Fig. 4 is the structural representation of wafer resistor in another preferred embodiment of the utility model.
Fig. 5 is the lower view of wafer resistor among Fig. 4.
Embodiment
For making the purpose of this utility model, structure, feature and function thereof there are further understanding, hereby cooperate embodiment to be described in detail as follows.
See also Fig. 2, be the sectional view of wafer resistor 4 in the preferred embodiment of the present utility model.Wafer resistor 4 is welded on the circuit board 5, has a pair of weld pad (52,54) on this circuit board 5, is welded and fixed for wafer resistor 4.
As shown in Figure 2, wafer resistor 4 of the present utility model comprises insulated substrate 40, pair of end electrode (42,44), resistive element 46 and protective layer 48.Insulated substrate 40 has lower surface 402.This is formed on the lower surface 402 of insulated substrate 40 termination electrode (42,44).In addition; resistive element 46 also is formed on the lower surface 402 of insulated substrate 40; its position is in this between the termination electrode (42,44); and the two ends of resistive element 46 are electrically connected respectively this to termination electrode (42,44); simultaneously; be not subjected to the impact of environment for better protective resistance body, on resistive element 46 surfaces, also be provided with layer protective layer 48 in the present embodiment.
See also Fig. 3, be the lower view of the utility model wafer resistor 4.Further find out, all there is the gap at the edge on surface 402 under each termination electrode (42,44) and the insulated substrate 40.By this, the insulated substrate 40 of wafer resistor 4 can cover this does not allow it expose termination electrode (42,44) and this to weld pad (52,54), can further dwindle other electronic components of adjacent wafer resistor 4 on the circuit board 5 and the spacing between the wafer resistor 4.
In specific embodiment, resistive element 46 can be first with screen painting processing procedure coating one resistance paste on the lower surface 402 of insulated substrate 40, resistance paste drying, sintering resistive element 46.
In addition, for allowing this can be welded on this on the weld pad (52,54) to termination electrode (42,44), the gross thickness of resistive element 46 and protective layer 48 stacks is no more than the thickness of arbitrary termination electrode (42,44).
Refer again to shown in Figure 2ly, insulated substrate 40 has the upper surface 404 relative with lower surface 402.Chip-R 4 devices also comprise marking layer 49, are formed on the upper surface 404 of insulated substrate 40, in order to indicate the resistance value of wafer resistor 4.
As for the selection aspect, each termination electrode (42,44) is by in the better metal of gold, silver, copper, nickel, tin or other conductivity any one, or is that the alloy material behind the multiple combination is made arbitrarily in the above-mentioned metal, but not as limit; Insulated substrate 40 is made by the good ceramic material of SiN, Si3N4, SiO2, SiC, Al2O3, AlN or other insulating properties; Protective layer 48 can be passivation layer or anti oxidation layer.
See also Fig. 4, be the sectional view of wafer resistor 6 in another preferred embodiment of the utility model.On wafer resistor 6 soldered circuit boards 7, have a pair of weld pad (72,74) on this circuit board 7, be welded and fixed for wafer resistor 6.
As shown in Figure 4, wafer resistor 6 comprises insulated substrate 60, pair of end electrode (62,64), resistive element 66, protective layer 67 and a pair of perforation conductor (68,69).Insulated substrate 60 has lower surface 602 and the upper surface 604 relative with lower surface 602.Resistive element 66 is formed on the upper surface 604 of insulated substrate 60, and is same, is not subjected to the impact of environment for better protective resistance body 66, also is provided with layer protective layer 67 in the present embodiment on resistive element 66 surfaces.This is formed on the lower surface 602 of insulated substrate 60 termination electrode (62,64).Protective layer 67 also can be as marking layer, in order to indicate the resistance value of wafer resistor 6.
Each termination electrode (62,64) is end one of in the two ends of corresponding resistive element 66 respectively.This is formed in the insulated substrate 60 perforation conductor (68,69), and runs through insulated substrate 60.Each perforation conductor (68,69) is electrically connected respectively a wherein end of a termination electrode (62,64) and corresponding resistive element 66 thereof.
See also Fig. 5, be the lower view of the utility model wafer resistor 6.Further find out, all there is the gap at the edge on surface 602 under each termination electrode (62,64) and the insulated substrate 60.By this, the insulated substrate 60 of wafer resistor 6 can cover this does not allow it expose termination electrode (62,64) and this to weld pad (72,74), can further dwindle other electronic components of adjacent wafer resistor 6 on the circuit board 7 and the spacing between the wafer resistor 6.
In specific embodiment, the processing procedure of resistive element 66 is as follows: first cover one deck resistance paste on the upper surface 604 of insulated substrate 60 with the screen painting processing procedure, resistance paste drying, sintering resistive element 66.
As for the selection aspect, each termination electrode (62,64) is by in the good metal of gold, silver, copper, nickel, tin or other conductivity any one, or is that the alloy material behind the multiple combination is made arbitrarily in the above-mentioned metal, but not as limit; Insulated substrate 60 is consisted of by being stacked by multi-layer ceramics layer 61.
In addition, each perforation conductor (68,69) by be formed at sub-perforation conductors (682,692) in every one deck ceramic layer 61 stack consist of.The formation method of sub-perforation conductor (682,692) is as follows: form two perforations (via hole) at every one deck ceramic layer 61 first, again electric conducting material is inserted in these two perforations, with multi-layer ceramics layer 61 sintering, namely finish sub-perforation conductor (682,692), place the every one deck ceramic layer 61 of selection made by the good ceramic material of SiN, Si3N4, SiO2, SiC, Al2O3, AlN or other insulating properties.
The utility model is described by above-mentioned related embodiment, yet above-described embodiment is only for implementing example of the present utility model.Must be pointed out that, the embodiment that has disclosed does not limit scope of the present utility model.On the contrary, the change of doing within not breaking away from spirit and scope of the present utility model and retouching all belong to scope of patent protection of the present utility model.
Claims (13)
1. wafer resistor is characterized in that comprising:
Insulated substrate has a lower surface;
The pair of end electrode is formed on this lower surface of this insulated substrate;
Resistive element is formed on this lower surface of this insulated substrate, and its position is in this between the termination electrode, and the two ends of this resistive element are electrically connected respectively this to termination electrode; And
Protective layer is formed on this resistive element.
2. as claimed in claim 1 wafer resistor is characterized in that the gross thickness of this resistive element and this protective layer stack is no more than the thickness of each termination electrode.
3. as claimed in claim 1 wafer resistor is characterized in that all there is a gap at the edge of this lower surface of each termination electrode and this insulated substrate.
4. as claimed in claim 1 wafer resistor is characterized in that this insulated substrate has a upper surface relative with this lower surface, and this wafer resistor also comprises a marking layer, is formed on this upper surface of this insulated substrate.
5. as claimed in claim 1 wafer resistor is characterized in that each termination electrode is gold electrode, silver electrode, copper electrode, nickel electrode or tin electrode.
6. as claimed in claim 1 wafer resistor is characterized in that this insulated substrate is SiN substrate, Si3N4 substrate, SiO2 substrate, SiC substrate, Al2O3 substrate or AlN substrate.
7. wafer resistor is characterized in that comprising:
Insulated substrate has a lower surface and a upper surface relative with this lower surface;
Resistive element is on this upper surface that is formed on this insulated substrate;
Protective layer is for being formed on this resistive element;
The pair of end electrode is formed on this lower surface of this insulated substrate, and each termination electrode is respectively to end one of in should the two ends of resistive element; And
A pair of perforation conductor is formed in this insulated substrate and runs through this insulated substrate, and each perforation conductor is electrically connected respectively a wherein end of a termination electrode and this resistive element.
8. as claimed in claim 7 wafer resistor is characterized in that all there is a gap at the edge of this lower surface of each termination electrode and this insulated substrate.
9. as claimed in claim 7 wafer resistor is characterized in that each termination electrode is gold electrode, silver electrode, copper electrode, nickel electrode or tin electrode.
10. as claimed in claim 7 wafer resistor is characterized in that this insulated substrate is SiN substrate, Si3N4 substrate, SiO2 substrate, SiC substrate, Al2O3 substrate or AlN substrate.
11. wafer resistor as claimed in claim 7 is characterized in that this insulated substrate is consisted of by being stacked by the multi-layer ceramics layer.
12. wafer resistor as claimed in claim 11, it is characterized in that each perforation conductor serve as reasons be formed at sub-perforation conductor in every one deck ceramic layer stack consist of.
13. wafer resistor as claimed in claim 11 is characterized in that every one deck ceramic layer is SiN layer, Si3N4 layer, SiO2 layer, SiC layer, Al2O3 layer or AlN layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220187892 CN202736613U (en) | 2012-04-28 | 2012-04-28 | Wafer resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220187892 CN202736613U (en) | 2012-04-28 | 2012-04-28 | Wafer resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202736613U true CN202736613U (en) | 2013-02-13 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220187892 Expired - Fee Related CN202736613U (en) | 2012-04-28 | 2012-04-28 | Wafer resistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202736613U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104376938A (en) * | 2013-08-13 | 2015-02-25 | 乾坤科技股份有限公司 | Resistance device |
| US8987864B2 (en) | 2013-06-05 | 2015-03-24 | Samsung Electro-Mechanics Co., Ltd. | Array type chip resistor and method of manufacturing thereof |
-
2012
- 2012-04-28 CN CN 201220187892 patent/CN202736613U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8987864B2 (en) | 2013-06-05 | 2015-03-24 | Samsung Electro-Mechanics Co., Ltd. | Array type chip resistor and method of manufacturing thereof |
| TWI485723B (en) * | 2013-06-05 | 2015-05-21 | Samsung Electro Mech | Array type chip resistor and method of manufacturing thereof |
| CN104376938A (en) * | 2013-08-13 | 2015-02-25 | 乾坤科技股份有限公司 | Resistance device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130213 Termination date: 20170428 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |