CN202712837U - Input DC anti-peak and overvoltage surge circuit - Google Patents
Input DC anti-peak and overvoltage surge circuit Download PDFInfo
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- CN202712837U CN202712837U CN 201220343118 CN201220343118U CN202712837U CN 202712837 U CN202712837 U CN 202712837U CN 201220343118 CN201220343118 CN 201220343118 CN 201220343118 U CN201220343118 U CN 201220343118U CN 202712837 U CN202712837 U CN 202712837U
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Abstract
The utility model discloses an input DC anti-peak and overvoltage surge circuit, comprising an input source, a load Uo, a first voltage stabilizing tube, a second voltage stabilizing tube, a P-channel MOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a 555 integrated timer. By using a transient voltage to restrain a diode to absorb a 600V/10 microsecond peak voltage, the circuit enables the peak voltage of an input end to be clamped within a very low voltage range after absorption; and by using an overvoltage surge absorption circuit to solve a 80 V/50 millisecond overvoltage surge and adding a protection circuit at the front end of a general DC power supply, a general DC power device also can work normally on the condition of a GJB181-86 specified peak voltage and the overvoltage surge voltage, the circuit loss is small, and the efficiency can reach 99%.
Description
Technical field
The utility model relates to a kind of power protecting circuit, particularly the anti-spike of a kind of input direct-current and overvoltage surge circuit.
Background technology
Direct current supply on air equipment has two kinds of sources, the one, aero-engine drives the DC generator power supply, the 2nd, the storage battery stand-by power supply, but because the direct current supply that aero-engine driving DC generator produces is very unstable, the direct voltage of generation is easy to occur the situation of overvoltage; Aircraft is aerial as run into thunderbolt at height, or all can produce very high peak voltage in the moment that inductive load switches; When the high power load interruption of work is arranged, can produce very high overvoltage surge at power line in flight course; The 2.4.4 item has been stipulated the transient voltage of airborne direct-flow electricity utilization apparatus is required in GJB181-86 " aircraft electrical supply parameters is to the requirement of power consumption equipment ": the 1st " anti-peak voltage " for the 2.4.4.1 regulation is the pulse voltage of 600V/10us; : the 2nd is a bar " anti-overvoltage surge " of regulation of the proof voltage surge of 2.4.4.2, is 80V/50ms.
Many common direct-flow electricity utilization apparatus all use on ground on the market at present, environment for use is all secure, above extreme environment can not appear, so the supply district that general direct current of ground power supply unit requires is DC18～36V, the maximum withstand voltage surge that can bear is 50V, the ability that does not have anti-80V overvoltage and anti-spike, these equipment just may can't work under the aviation power supply environment at all or be damaged.
Summary of the invention
Technical problem to be solved in the utility model provides the anti-spike of a kind of input direct-current and overvoltage surge circuit, it is unstable to overcome existing aviation dc power supply, and the various interference that produce of the power input line that occurs in the practical flight process and the problem that causes equipment to work even to damage.
For the purpose that realizes solving the problems of the technologies described above, the utility model has adopted following technical scheme:
The anti-spike of a kind of input direct-current of the present utility model and overvoltage surge circuit comprise input source Ui, load Uo, the first voltage-stabiliser tube, the second voltage-stabiliser tube, P channel MOS tube, the first resistance, the second resistance, the 3rd resistance, the 3rd resistance, the 4th resistance, the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, 555 integrated timers; Wherein
The positive pole of input source Ui is connected to the drain electrode of an end and the P channel MOS tube of the first resistance and the second resistance, the negative pole of input source Ui is connected to the positive pole of the first voltage-stabiliser tube and the second voltage-stabiliser tube, the negative pole of the first electric capacity, one end of the 3rd electric capacity and the 4th electric capacity, 1 pin of 555 integrated timers, load Uo negative pole, described load Uo positive pole is connected to the source electrode of metal-oxide-semiconductor, the grid of described metal-oxide-semiconductor is connected to the other end of the second resistance, the negative pole of the second voltage-stabiliser tube, the other end of the first resistance is connected to the negative pole of the first voltage-stabiliser tube, the positive pole of the first electric capacity, 4 pin of 555 integrated timers and 8 pin, one end of the 4th resistance, 7 pin of 555 integrated timers are connected to an end of the 3rd resistance, and 2 pin of 555 integrated timers are connected to the other end of the 3rd resistance, 6 pin of 555 integrated timers, the other end of the 4th resistance, the other end of the 4th electric capacity; 5 pin of 555 integrated timers are connected to the other end of the 3rd electric capacity, and 3 pin of 555 integrated timers are connected to the negative pole of the second voltage-stabiliser tube successively by the 3rd resistance and the second electric capacity.
The anti-spike of the input direct-current of this patent and overvoltage surge circuit also comprise a transient state twin zener dioder.The positive pole of described Transient Suppression Diode is connected to the negative pole of power supply Ui, and the negative pole of Transient Suppression Diode is connected to the positive pole of power supply Ui.
Concrete, the pin definitions of described 555 integrated timers of this patent is: 1-GND, 2-TRIG, 3-PUT, 4-RESET, 5-CONT, 6-THRIS, 7-DISCH, 8-V
CCFurther concrete preferred, described 555 integrated timers are 555 integrated timers of intersil company production.
By adopting technique scheme, the utlity model has following beneficial effect:
The anti-spike of a kind of input direct-current of the present utility model and overvoltage surge circuit, absorb 600V/10 μ s peak voltage by transient voltage suppressor diode, the peak voltage of input is clamped in the very low voltage range after absorbing, solves the overvoltage surge of 80V/50ms by the overvoltage surge absorbing circuit.This protective circuit is added in conventional DC power supply front end, the conventional DC power consumption equipment also can be worked under the peak voltage of GJB181-86 regulation and overvoltage surge voltage condition.
This circuit is when power supply works, and the energy of circuit loss mainly is the pressure drop of metal-oxide-semiconductor V6, and the V6 pressure drop is the conducting resistance of V6
Multiply by the input current of power supply, the MOSFET conducting resistance of general withstand voltage 200VDC is several milliohms, and circuit loss is very little, and efficient can reach 99%.In view of above description, this circuit uses simple, and it is low to produce hear rate, reliable operation.
Description of drawings
Fig. 1 is the anti-spike of input direct-current of the present utility model and overvoltage surge circuit.
Among the figure, 1 is Transient Suppression Diode, and 2 is the first voltage-stabiliser tube, 3 is the second voltage-stabiliser tube, and 6 is the P channel MOS tube, and 7 is the first resistance, 8 is the second resistance, and 9 is the 3rd resistance, and 10 is the 3rd resistance, 11 is the 4th resistance, 12 is the first electric capacity, and 13 is the second electric capacity, and 14 is the 3rd electric capacity, 15 is the 4th electric capacity, and 16 is 555 integrated timers.
Embodiment
Below in conjunction with drawings and Examples the utility model is described further.
As shown in Figure 1, the anti-spike of the utility model input direct-current and overvoltage surge circuit comprise input source Ui, load Uo, the first voltage-stabiliser tube 2, the second voltage-stabiliser tube 3, P channel MOS tube 6, the first resistance 7, the second resistance 8, the 3rd resistance 9, the 3rd resistance 10, the 4th resistance 11, the first electric capacity 12, the second electric capacity 13, the 3rd electric capacity 14, the 4th electric capacity 15,555 integrated timers 16; Wherein: the positive pole of input source Ui is connected to an end of the first resistance 7 and the second resistance 8 and the drain electrode of P channel MOS tube 6, the negative pole of input source Ui is connected to the positive pole of the first voltage-stabiliser tube 2 and the second voltage-stabiliser tube 3, the negative pole of the first electric capacity 12, one end of the 3rd electric capacity 14 and the 4th electric capacity 15,1 pin of 555 integrated timers 16 that intersil company produces, load Uo negative pole, described load Uo positive pole is connected to the source electrode of metal-oxide-semiconductor 6, the grid of described metal-oxide-semiconductor 6 is connected to the other end of the second resistance 8, the negative pole of the second voltage-stabiliser tube 3, the other end of the first resistance 7 is connected to the negative pole of the first voltage-stabiliser tube 2, the positive pole of the first electric capacity 12,4 pin of 555 integrated timers 16 and 8 pin, one end of the 4th resistance 11,7 pin of integrated timer 16 are connected to an end of the 3rd resistance 10, and 2 pin of 555 integrated timers 16 are connected to the other end of the 3rd resistance 10,6 pin of 555 integrated timers 16, the other end of the 4th resistance 11, the other end of the 4th electric capacity 15; 5 pin of 555 integrated timers 16 are connected to the other end of the 3rd electric capacity 14, and 3 pin of 555 integrated timers 16 are connected to the negative pole of the second voltage-stabiliser tube 3 successively by the 3rd resistance 9 and the second electric capacity 13.
The applicable direct voltage 18V～36V that is input as of this circuit.+ OUT and-the OUT back can connect the DC/DC power module, can realize the anti-peak voltage of input, anti-overvoltage surge function among the GJB181-86.
For 600V/10 μ s pulse voltage, we adopt high-power Transient Suppression Diode 1 to absorb.Wherein Transient Suppression Diode 1 can be the 5KP70A of monarch's credit company production.
For the overvoltage surge of 80V/50ms, we adopt the surge absorbing circuit in Fig. 1 dotted line frame to solve, and when power supply was normal, voltage-stabiliser tube V3 was in cut-off state, MOSFET 6 conductings.During the input overvoltage surge, the second voltage-stabiliser tube 3 is in the voltage stabilizing state, and surge voltage can be clamped to output voltage the normal input voltage range of power module (the GS magnitude of voltage of the voltage stabilizing value-metal-oxide-semiconductor 6 of output voltage=voltage-stabiliser tube 3) by metal-oxide-semiconductor 6.
In the circuit about 3 pin output amplitude 13V of 555 integrated timers 16, the square-wave signal of frequency f (
, unit is international unit).The charge pump circuit of this signal by being formed by the 3rd resistance 9 and the second electric capacity 13, this signal controlling charge pump makes the grid of metal-oxide-semiconductor 6 than more than the high 10V of source potential, and this bias voltage makes metal-oxide-semiconductor 6 conductings.
After this protective circuit, the overvoltage surge of 600V/10us pulse voltage and 80V/50ms all is clamped in the normal input voltage range of power module, guarantees the normal operation of back end DC power consumption equipment.
Claims (3)
1. the anti-spike of input direct-current and overvoltage surge circuit is characterized in that: comprise input source Ui, load Uo, the first voltage-stabiliser tube (2), the second voltage-stabiliser tube (3), P channel MOS tube (6), the first resistance (7), the second resistance (8), the 3rd resistance (9), the 3rd resistance (10), the 4th resistance (11), the first electric capacity (12), the second electric capacity (13), the 3rd electric capacity (14), the 4th electric capacity (15), 555 integrated timers (16); Wherein:
The positive pole of input source Ui is connected to the drain electrode of an end and the P channel MOS tube (6) of the first resistance (7) and the second resistance (8), the negative pole of input source Ui is connected to the positive pole of the first voltage-stabiliser tube (2) and the second voltage-stabiliser tube (3), the negative pole of the first electric capacity (12), one end of the 3rd electric capacity (14) and the 4th electric capacity (15), 1 pin of 555 integrated timers (16), load Uo negative pole, described load Uo positive pole is connected to the source electrode of metal-oxide-semiconductor 6, the grid of described metal-oxide-semiconductor 6 is connected to the other end of the second resistance (8), the negative pole of the second voltage-stabiliser tube (3), the other end of the first resistance (7) is connected to the negative pole of the first voltage-stabiliser tube (2), the positive pole of the first electric capacity (12), 4 pin of 555 integrated timers (16) and 8 pin, one end of the 4th resistance (11), 7 pin of 555 integrated timers (16) are connected to an end of the 3rd resistance (10), and 2 pin of 555 integrated timers (16) are connected to the other end of the 3rd resistance (10), 6 pin of 555 integrated timers (16), the other end of the 4th resistance (11), the other end of the 4th electric capacity (15); 5 pin of 555 integrated timers (16) are connected to the other end of the 3rd electric capacity (14), and 3 pin of 555 integrated timers (16) are connected to the negative pole of the second voltage-stabiliser tube (3) successively by the 3rd resistance (9) and the second electric capacity (13).
2. the according to claim 1 anti-spike of described input direct-current and overvoltage surge circuit, it is characterized in that: the anti-spike of input direct-current and overvoltage surge circuit also comprise a transient state twin zener dioder (1), the positive pole of Transient Suppression Diode (1) is connected to the negative pole of power supply Ui, and the negative pole of Transient Suppression Diode (1) is connected to the positive pole of power supply Ui.
3. the according to claim 1 anti-spike of described input direct-current and overvoltage surge circuit, it is characterized in that: the pin definitions of described 555 integrated timers is: 1-GND, 2-TRIG, 3-PUT, 4-RESET, 5-CONT, 6-THRIS, 7-DISCH, 8-V
CC
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220343118 CN202712837U (en) | 2012-07-16 | 2012-07-16 | Input DC anti-peak and overvoltage surge circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220343118 CN202712837U (en) | 2012-07-16 | 2012-07-16 | Input DC anti-peak and overvoltage surge circuit |
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| Publication Number | Publication Date |
|---|---|
| CN202712837U true CN202712837U (en) | 2013-01-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220343118 Expired - Lifetime CN202712837U (en) | 2012-07-16 | 2012-07-16 | Input DC anti-peak and overvoltage surge circuit |
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| CN (1) | CN202712837U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107317319A (en) * | 2017-07-31 | 2017-11-03 | 北京小米移动软件有限公司 | Surge protection device and method and a kind of mobile terminal |
| CN109643892A (en) * | 2016-04-15 | 2019-04-16 | 力特半导体（无锡）有限公司 | Overvoltage protection and linear regulator EM equipment module |
| CN112039017A (en) * | 2020-09-10 | 2020-12-04 | 贵州天义电器有限责任公司 | On-board equipment 28V power supply short-circuit protection circuit with surge voltage suppression |
-
2012
- 2012-07-16 CN CN 201220343118 patent/CN202712837U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109643892A (en) * | 2016-04-15 | 2019-04-16 | 力特半导体（无锡）有限公司 | Overvoltage protection and linear regulator EM equipment module |
| US10998719B2 (en) | 2016-04-15 | 2021-05-04 | Littelfuse Semiconductor (Wuxi) Co., Ltd. | Overvoltage protection and linear regulator device module |
| TWI743099B (en) * | 2016-04-15 | 2021-10-21 | 大陸商力特半導體（無錫）有限公司 | Overvoltage protection and linear regulator device module |
| CN107317319A (en) * | 2017-07-31 | 2017-11-03 | 北京小米移动软件有限公司 | Surge protection device and method and a kind of mobile terminal |
| CN107317319B (en) * | 2017-07-31 | 2019-11-08 | 北京小米移动软件有限公司 | Surge protection device and method and a kind of mobile terminal |
| CN112039017A (en) * | 2020-09-10 | 2020-12-04 | 贵州天义电器有限责任公司 | On-board equipment 28V power supply short-circuit protection circuit with surge voltage suppression |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130130 |
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| CX01 | Expiry of patent term |