CN202679234U - Hiccup type over-voltage and over-current protection circuit capable of setting time - Google Patents
Hiccup type over-voltage and over-current protection circuit capable of setting time Download PDFInfo
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- CN202679234U CN202679234U CN 201220334161 CN201220334161U CN202679234U CN 202679234 U CN202679234 U CN 202679234U CN 201220334161 CN201220334161 CN 201220334161 CN 201220334161 U CN201220334161 U CN 201220334161U CN 202679234 U CN202679234 U CN 202679234U
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Abstract
The present utility model relates to a hiccup type over-voltage and over-current protection circuit capable of setting time. The circuit comprises a first NAND gate, an input end is connected with a protected circuit detection point for outputting voltage/current signals, an output end is connected with an input end of a second NAND gate, an input end of the second NAND gate is connected with a charging capacitor C1, an output end of the second NAND gate is connected with the input end of the first NAND gate, and the output end of the first NAND gate is connected with a subsequent circuit of a protected circuit through a switch tube Q2. When the protected circuit detection point is in normal output, the switch tube Q2 is cut off, and the protected circuit works normally; otherwise, when the protected circuit detection point is in output over-voltage or over-current, the switch tube Q2 is conducted, and protection is started. When the output of the protected circuit detection point is between normal state and over-voltage, the circuit can be repeatedly realized under the protection and non-protection state, the hiccup phenomenon can be realized, and the protection time of the circuit can be changed through changing the value of a capacitor C1.
Description
Technical field
The utility model relates to a kind of over-voltage over-current protection circuit, the especially a kind of formula of having the hiccups over-voltage over-current protection circuit that duration is set.
Background technology
In general, Switching Power Supply all requires to have the over-voltage over-current protection function, and when guaranteeing that electric power output voltage (electric current) is excessive, power supply can not damage.Common protective circuit has self-locking and two kinds of the formula protections of having the hiccups, in case during self-locking protective circuit output voltage too high (or electric current is excessive), protective circuit will start, power supply quits work, and need power cut-off this moment, and the investigation fault is repaired, and restarts power supply; And the formula protective circuit of having the hiccups is when overvoltage appears in power supply, and work can appear in power supply, and---protection---work---is protected again ... polyisomenism, until fault disappears.For the excessive power supply of some booting moment surge voltages (electric current), the formula of having the hiccups protected mode is more more convenient than self-locking protected mode, yet, also do not occur at present the formula of the having the hiccups protective circuit of protecting duration can be set.
The utility model content
The purpose of this utility model is to provide a kind of formula of having the hiccups over-voltage over-current protection circuit with arranged duration that the guard time function can be set.
For achieving the above object; the utility model has adopted following technical scheme: a kind of formula of having the hiccups over-voltage over-current protection circuit that duration is set; comprise the first NAND gate; its input links to each other with the protected electric circuit inspection point that is used for the output voltage/electric current signal; its output links to each other with the input of the second NAND gate; the input termination charging capacitor C1 of the second NAND gate; the output of the second NAND gate links to each other with the input of the first NAND gate, and the output of the first NAND gate connects the subsequent conditioning circuit of protected circuit by switching tube Q2.
As shown from the above technical solution, when the output of protected electric circuit inspection point is normal, switching tube Q2 cut-off, protected circuit normal operation; Otherwise, when protected circuit monitoring point output overvoltage or overcurrent, switching tube Q2 conducting, protection starts, if protected circuit monitoring is put always output overvoltage or overcurrent, then circuit can be in guard mode always.When the output of protected electric circuit inspection point is between normal and overvoltage; the utility model will be in protection---repeats under the state do not protected; present the phenomenon of having the hiccups; by changing the value of charging capacitor C1; can change the guard time of circuit; the value of charging capacitor C1 is larger, and guard time is longer.
Description of drawings
Fig. 1 is circuit theory diagrams of the present utility model;
Fig. 2 is when C1=1uF, the voltage schematic diagram of the utility model output;
Fig. 3 is when C1=0.1uF, the voltage schematic diagram of the utility model output.
Embodiment
A kind of formula of having the hiccups over-voltage over-current protection circuit that duration is set; comprise the first NAND gate; its input links to each other with the protected electric circuit inspection point that is used for the output voltage/electric current signal; its output links to each other with the input of the second NAND gate; the input termination charging capacitor C1 of the second NAND gate; the output of the second NAND gate links to each other with the input of the first NAND gate, and the output of the first NAND gate connects the subsequent conditioning circuit of protected circuit by switching tube Q2, as shown in Figure 1.
As shown in Figure 1; described the first NAND gate is NAND gate U1A; described the second NAND gate is NAND gate U1B; described switching tube Q2 is triode Q2; the 2nd pin of NAND gate U1A links to each other with the test point that is used for the output voltage/electric current signal; the 1st pin of NAND gate U1A links to each other with the 4th pin of NAND gate U1B; the 3rd pin of NAND gate U1A links to each other with the 5th pin of NAND gate U1B by resistance R 1; the 3rd pin of NAND gate U1A connects the base stage of triode Q2 by resistance R 3; the collector electrode of triode Q2 connects protected circuit, the grounded emitter of triode Q2.
As shown in Figure 1, the 6th pin of described NAND gate U1B connects the parallel circuits that is composed in parallel by capacitor C 2, charging capacitor C1 and resistance R 4 threes, and the positive pole of charging capacitor C1 links to each other the minus earth of charging capacitor C1 with the 6th pin of NAND gate U1B.The 4th pin of described NAND gate U1B connects the base stage of triode Q1 by resistance R 2, the collector electrode of triode Q1 connects+the 12V direct current, and the emitter of triode Q1 is by resistance R 4 ground connection.
When the output of protected electric circuit inspection point was normal, 2 pin of NAND gate U1A were high level, and the 4 pin voltages of NAND gate U1B are high level when normal operation always; then 1 pin of NAND gate U1A also is high level, simultaneously, because triode Q1 conducting; therefore, 6 pin of NAND gate U1B also are high level.Because 1,2 pin of NAND gate U1A are high level, the 3 pin output low levels of NAND gate U1A, triode Q2 cut-off, transistor collector end T2 is high level, the subsequent conditioning circuit normal operation of protected circuit.
When the output overvoltage of protected electric circuit inspection point or overcurrent, 2 pin of NAND gate U1A are low level, and then 3 pin of NAND gate U1A are high level; triode Q2 conducting; the voltage of transistor collector end T2 is dragged down, and the subsequent conditioning circuit of protected circuit is not worked, and protection starts.At this moment, 5 pin of NAND gate U1B are high level; Before overcurrent or overvoltage occur, 6 pin of NAND gate U1B are high level, and give charging capacitor C1 charging, then 4 pin of NAND gate U1B are low level, 1 pin of NAND gate U1A is low level, triode Q1 cut-off, and charging capacitor C1 begins discharge, 6 pin of NAND gate U1B become low level, and then 4 pin of NAND gate U1B become high level.If always overvoltage of the output of protected electric circuit inspection point, then the utility model can be in guard mode always.When the output of protected electric circuit inspection point was between normal and overvoltage, the utility model will be in protection---and repeat under the state do not protected, present the phenomenon of having the hiccups.By changing the value of charging capacitor C1, can change the guard time of circuit.
Fig. 2 and shown in Figure 3 being respectively when charging capacitor C1=1uF and charging capacitor C1=0.1uF, the utility model output is the voltage condition of transistor collector end T2 namely, can be found out by two figure, and when overvoltage or overcurrent, there is the phenomenon of having the hiccups in circuit.Guard time among Fig. 2 is 1s nearly, and the guard time among Fig. 3 is 0.2s.As seen, the value that changes charging capacitor C1 can change guard time, and the value of charging capacitor C1 is larger, and guard time is just longer.
Claims (4)
1. the formula of having the hiccups over-voltage over-current protection circuit that duration can be set; it is characterized in that: comprise the first NAND gate; its input links to each other with the protected electric circuit inspection point that is used for the output voltage/electric current signal; its output links to each other with the input of the second NAND gate; the input termination charging capacitor C1 of the second NAND gate; the output of the second NAND gate links to each other with the input of the first NAND gate, and the output of the first NAND gate connects the subsequent conditioning circuit of protected circuit by switching tube Q2.
2. the formula of the having the hiccups over-voltage over-current protection circuit that duration is set according to claim 1; it is characterized in that: described the first NAND gate is NAND gate U1A; described the second NAND gate is NAND gate U1B; described switching tube Q2 is triode Q2; the 2nd pin of NAND gate U1A links to each other with the test point that is used for the output voltage/electric current signal; the 1st pin of NAND gate U1A links to each other with the 4th pin of NAND gate U1B; the 3rd pin of NAND gate U1A links to each other with the 5th pin of NAND gate U1B by resistance R 1; the 3rd pin of NAND gate U1A connects the base stage of triode Q2 by resistance R 3; the collector electrode of triode Q2 connects protected circuit, the grounded emitter of triode Q2.
3. the formula of the having the hiccups over-voltage over-current protection circuit that duration is set according to claim 1; it is characterized in that: the 6th pin of described NAND gate U1B connects the parallel circuits that is composed in parallel by capacitor C 2, charging capacitor C1 and resistance R 4 threes; the positive pole of charging capacitor C1 links to each other the minus earth of charging capacitor C1 with the 6th pin of NAND gate U1B.
4. the formula of the having the hiccups over-voltage over-current protection circuit that duration is set according to claim 3; it is characterized in that: the 4th pin of described NAND gate U1B connects the base stage of triode Q1 by resistance R 2; the collector electrode of triode Q1 connects+the 12V direct current, and the emitter of triode Q1 is by resistance R 4 ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220334161 CN202679234U (en) | 2012-07-11 | 2012-07-11 | Hiccup type over-voltage and over-current protection circuit capable of setting time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220334161 CN202679234U (en) | 2012-07-11 | 2012-07-11 | Hiccup type over-voltage and over-current protection circuit capable of setting time |
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| Publication Number | Publication Date |
|---|---|
| CN202679234U true CN202679234U (en) | 2013-01-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220334161 Expired - Fee Related CN202679234U (en) | 2012-07-11 | 2012-07-11 | Hiccup type over-voltage and over-current protection circuit capable of setting time |
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| CN (1) | CN202679234U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102780389A (en) * | 2012-07-11 | 2012-11-14 | 合肥华耀电子工业有限公司 | Hiccup type overvoltage and overcurrent protecting circuit capable of setting time length |
-
2012
- 2012-07-11 CN CN 201220334161 patent/CN202679234U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102780389A (en) * | 2012-07-11 | 2012-11-14 | 合肥华耀电子工业有限公司 | Hiccup type overvoltage and overcurrent protecting circuit capable of setting time length |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130116 Termination date: 20210711 |
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| CF01 | Termination of patent right due to non-payment of annual fee |