CN202663370U - Digital controlled analogue modulation circuit - Google Patents
Digital controlled analogue modulation circuit Download PDFInfo
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- CN202663370U CN202663370U CN 201220265298 CN201220265298U CN202663370U CN 202663370 U CN202663370 U CN 202663370U CN 201220265298 CN201220265298 CN 201220265298 CN 201220265298 U CN201220265298 U CN 201220265298U CN 202663370 U CN202663370 U CN 202663370U
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Abstract
The utility model relates to a modulation circuit, and particularly relates to a digital controlled analogue modulation circuit. The modualtion cirucit aims to solve the problem that burr interference exists in the prior art. The main points of the technical scheme are as follows: the analogue modulation circuit comprises a working power source, a bias power source, a modulation signal source and a single-pole double-throw analogue switch ASW1, a single-pole double-throw analogue switch ASW2 and a laser constant-current driving circuit. The digital contorlled analogue modulation circuit further comprises a delay double-output circuit; the input end of the delay double-output circuit is electrically connected with the output end of the modulation signal source; the direct output end of the delay double-output circuit is electrically connected with the control end of the single-pole double-throw analogue switch ASW1; the delay output end of the delay double-output circuit is electrically connected with the control end of the single-pole double-throw analogue switch ASW2; the output electric level of the direct output end of the delay double-output circuit is equal to the negative output level of the modulation signal source; and the delay output end level of the delay double-output circuit is the same as the output level of the modulation signal source. The analogue modulation circuit provided by the utility model has a reasonable design, and the burr interference is removed.
Description
Technical field
The utility model relates to a kind of modulation circuit, particularly a kind of numerically controlled analog modulation circuit.
Background technology
Semiconductor laser is current control device, and luminous power is flow through the control of the forward current size of laser, in order to obtain stable laser power output, usually adopts constant-current source circuit to come drive laser; In order to realize the Digital Modulation to this analog quantity output signals of luminous power, need to adopt numerically controlled analog modulation circuit.Generally, analog modulation circuit can select the single-pole double throw analog switch switching between two analog signals rapidly.But, in the handoff procedure with two signal shorts, when making analog switch device, usually all be provided with one very short interior at time-delay t, in at this moment, whole ports of analog switch all are in off-state, and the off-state of this full port has been arranged, when signal switches, burr will appear in the common port of analog switch to be disturbed, and causes obtaining pure modulated-analog signal output.
China Patent Publication No.: CN1914792A, open day: on 02 14th, 2007, a kind of Circuit tuning of the amplitude for adjusting radiofrequency signal is disclosed, described Circuit tuning comprises: a plurality of terminals that are used for input and output; Matching block has and mates from the input signal of described a plurality of terminals and the effect of arriving the output signal of described a plurality of terminals; And at least one adjustable resistance unit between described matching block and ground, for the resistance of at least one terminal that changes described a plurality of terminals.Usually all be provided with a very short inherence time-delay t when obviously also still there is analog switch device in this technical scheme, in at this moment, whole ports of analog switch all are in off-state, the off-state that this full port has been arranged, when signal switches, burr will appear in the common port of analog switch to be disturbed, and causes obtaining the problem of pure modulated-analog signal output.
The utility model content
The purpose of this utility model is to solve prior art and exists analog switch device usually all to be provided with a very short inherence time-delay t, in at this moment, whole ports of analog switch all are in off-state, the off-state that this full port has been arranged, when signal switches, burr will appear in the common port of analog switch to be disturbed, cause to obtain the problem of pure modulated-analog signal output, provide a kind of common port that can overcome analog switch burr will occur and disturb, obtain the numerically controlled analog modulation circuit of pure modulated-analog signal output.
The technical scheme that its technical problem that solves the utility model adopts is: a kind of numerically controlled analog modulation circuit, comprise working power, bias supply, modulating signal source and single-pole double throw analog switch ASW1, single-pole double throw analog switch ASW2 and laser constant-current drive circuit, the normally opened contact of the normally-closed contact of single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 all is electrically connected with the output of working power, the normally opened contact of the normally-closed contact of single-pole double throw analog switch ASW2 and single-pole double throw analog switch ASW1 all is electrically connected with the output of bias supply, the common port of the common port of single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 all is electrically connected with the input of laser constant-current drive circuit, described numerically controlled analog modulation circuit also comprises time-delay dual output circuit, the input of time-delay dual output circuit is electrically connected with the output of modulating signal source, the direct output of time-delay dual output circuit is electrically connected with the control end of single-pole double throw analog switch ASW1, the time-delay output of time-delay dual output circuit is electrically connected with the control end of single-pole double throw analog switch ASW2, the output level of the direct output of time-delay dual output circuit equals the output level negate of modulating signal source, and the time-delay output level of time-delay dual output circuit is identical with the output level of modulating signal source.The utility model is by arranging time-delay dual output circuit, in prior art, two opposite modulation signal level conversion that modulating signal source is exported simultaneously are a modulation signal level and the modulation signal level with time-delay characteristics, and two modulation signal level are opposite, when modulation signal is logic high, the modulation signal of single-pole double throw analog switch ASW1 is that the modulation signal of low level, single-pole double throw analog switch ASW2 is high level, and this moment, single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 were communicated with working power.When modulation signal during by high step-down, the rising edge of single-pole double throw analog switch ASW1 control end signal will make single-pole double throw analog switch ASW2 switch to being communicated with bias supply by being communicated with working power; Simultaneously, the output of time-delay dual output circuit makes single-pole double throw analog switch ASW2 switch to being communicated with bias supply by being communicated with working power through the anti-phase signal of time-delay (delay time should greater than the switching time of single-pole double throw analog switch ASW1), the level of each modulating signal source output modulation signal changes, always so that single-pole double throw analog switch ASW1 switch first, then single-pole double throw analog switch ASW2 just switches, and at single-pole double throw analog switch ASW1 between transfer period, it is stable that single-pole double throw analog switch ASW2 keeps, single-pole double throw analog switch ASW2 just begins to switch after single-pole double throw analog switch ASW1 enters stable state, obviously, the utility model has been eliminated the burr that full port off-state that the inherent time-delay of analog switch t causes produces and has been disturbed.
As preferably, the common port of described single-pole double throw analog switch ASW2 is electrically connected with the common port of single-pole double throw analog switch ASW1 by resistance R 1.The phenomenon of short circuit can appear in the common port of single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 in the utility model, for this reason, seal in resistance R 1 between the common port of single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2, to isolate the port of two different potentials.
As preferably, time-delay dual output circuit comprises the first logical circuit with inverter functionality and the second logical circuit with inverter functionality, the input of described the first logical circuit is electrically connected with described modulating signal source, the output of described the first logical circuit is electrically connected with the input of described the second logical circuit, the output of described the second logical circuit is electrically connected with the control end of single-pole double throw analog switch ASW2, and the output of described the first logical circuit also is electrically connected with the control end of single-pole double throw analog switch ASW2.Arrange like this, the modulation signal level that has guaranteed the output of the first logical circuit is opposite with the modulating signal source output level, the modulation signal level of the second logical circuit output is identical with the modulating signal source output level, and also there is the inherent delay characteristic in analog element in the second logical circuit, therefore, the second logical circuit can postpone the output modulation signal.
As preferably, described the first logical circuit is inverter U1-1, the inverter group of the second logical circuit for being consisted of by the series connection of odd number inverter, the output of described inverter group is electrically connected with the control end of described single-pole double throw analog switch ASW2, the input of described inverter group is electrically connected with the output of described inverter U1-1, the input of described inverter U1-1 is electrically connected with described modulating signal source, and the output of described inverter U1-1 also is electrically connected with the control end of described single-pole double throw analog switch ASW1.By inverter group is set, utilized the intrinsic of short duration time-delay of analog switch device, these of short duration time-delays are superposeed, reached the purpose that postpones the output modulation signal, in conjunction with inverter U1-1, all logic elements are inverter, just in time can utilize existing integrated chip simultaneously.
As preferably, described inverter group comprises at least three inverters.Arrange like this, the inherent delay time stack of at least three inverters, the level that can guarantee visible each modulating signal source changes, always so that single-pole double throw analog switch ASW1 switch first, then single-pole double throw analog switch ASW2 just switches, and at single-pole double throw analog switch ASW1 between transfer period, it is stable that single-pole double throw analog switch ASW2 keeps, single-pole double throw analog switch ASW2 just begins to switch after single-pole double throw analog switch ASW1 enters stable state, obviously, the utility model has been eliminated the burr that full port off-state that the inherent time-delay of single-pole double throw analog switch t causes produces and has been disturbed.
As preferably, described the second logical circuit is made of three logic circuit components series connection at least.Disturb owing to will guarantee the burr of eliminating the single-pole double throw analog switch, thus need the second logical circuit will carry out the delay of enough time, so, consisting of and can guarantee by three logic circuit component series connection at least, the time of delay of the second logical circuit is enough.
As preferably, described the second logical circuit is made of five logic circuit components series connection at the most.The second logical circuit is made of the series connection of five logic circuit components at the most, has both guaranteed the enough of time in logical delay, also can not cause the common port of single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 the long problem of phenomenon of short circuit can occur.
As preferably, described working power and bias supply are the electric capacity holding circuit that capacitance is 0.1 μ f, and the modulating frequency of described working power and bias supply is 1MHz, and the span of described resistance R 1 is at 47 ~ 200 Ω.Resistance R 1 in the utility model should carefully be selected, because modulating frequency of the present utility model is 1MHz, be to be modulation period 1 μ s, require the rising and falling edges of the modulation signal of the rear input of modulation laser constant-current drive circuit to be no more than 10% of the cycle, then the time of the rising of output signal or decline is less than tedge=100ns, the distributed capacitance C of single-pole double throw analog switch ASW1 common port is 10pf, with this understanding, if resistance R 1 is got 1K Ω, then the time constant of resistance R 1 and the formed circuit of distributed capacitance C is τ=R1*C=10ns, 3 τ=30ns, this value is compared accounting with tedge too large, according to 10% criterion commonly used in the engineering design, get 3 τ=10ns, R1=330 Ω correspondingly, namely R1 should be less than 330 Ω, and this is an aspect of considering when selecting resistance R 1.Investigate from another aspect, when single-pole double throw analog switch ASW1 switched to bias supply and ASW2 when not yet beginning to switch to working power or single-pole double throw analog switch ASW1 switched to working power and single-pole double throw analog switch ASW2 when not yet beginning to switch to bias supply, resistance R 1 two ends are connected respectively to working power and bias supply, 1 one-tenth of resistance R the load of working power and bias supply, this time is relevant with the selection of selected analog switch and negater circuit, for high-speed analog switch and inverter circuit, this time, ts was greatly about about 1ns.Because working power and bias supply in the utility model all only are by simple electric capacity holding circuit, so working power will be charged to bias supply, the result causes working power and bias supply fluctuation, causes that the signal of input laser constant-current drive circuit produces pulsation.In the utility model, the size of capacitor Cv in the electric capacity holding circuit is Cv=0.1 μ f, R1=10 Ω, R1*Cv=1ns then, suitable with ts numerical value, during this period of time, according to RC capacitor charge and discharge curve, to produce the voltage fluctuation of Vs=(working power-bias supply)/3, in order to reduce this voltage fluctuation, should improve the product value of R1*Cv, if the resistance value of resistance R 1 is brought up to 100 Ω, then Vs=(working power-bias supply)/30 ≈ (working power-bias supply) * 3.3%, can ignore.Therefore, the consideration of the factor of comprehensive above-mentioned two aspects, the span of resistance R 1 is at 47 ~ 200 Ω.
As preferably, described resistance R 1 is variable resistor.Variable-resistance setting has guaranteed to adapt to multiple circuit state, can be by manual form, and the on-the-spot size of reconciling resistance R 1.
The beneficial effects of the utility model are: the utility model is reasonable in design, has eliminated the burr that full port off-state that the inherent time-delay of analog switch t causes produces and has disturbed.
Description of drawings
Fig. 1 is a kind of circuit theory diagrams of the present utility model;
Fig. 2 is a kind of circuit theory diagrams of time-delay dual output circuit in the utility model;
Fig. 3 is the another kind of circuit theory diagrams of time-delay dual output circuit in the utility model.
Among the figure: 1, working power, 2, bias supply, 3, modulating signal source, 4, time-delay dual output circuit, 5, the laser constant-current drive circuit.
Embodiment
Below by specific embodiment, and by reference to the accompanying drawings, the technical solution of the utility model is described in further detail.
Embodiment 1:
A kind of numerically controlled analog modulation circuit (referring to accompanying drawing 1), comprise working power 1, bias supply 2, modulating signal source 3 and single-pole double throw analog switch ASW1, single-pole double throw analog switch ASW2 and laser constant-current drive circuit 5, the normally opened contact of the normally-closed contact of single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 all is electrically connected with the output of working power, the normally opened contact of the normally-closed contact of single-pole double throw analog switch ASW2 and single-pole double throw analog switch ASW1 all is electrically connected with the output of bias supply, the common port of the common port of single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 all is electrically connected with the input of laser constant-current drive circuit 5, the input of time-delay dual output circuit 4 is electrically connected with the output of modulating signal source 3, the direct output of time-delay dual output circuit 4 is electrically connected with the control end of single-pole double throw analog switch ASW1, the time-delay output of time-delay dual output circuit 4 is electrically connected with the control end of single-pole double throw analog switch ASW2, the output level of the direct output of time-delay dual output circuit equals the output level negate of modulating signal source 3, and the time-delay output level of time-delay dual output circuit 4 is identical with the output level of modulating signal source 3.The common port of single-pole double throw analog switch ASW2 is electrically connected with the common port of single-pole double throw analog switch ASW1 by resistance R 1.Time-delay dual output circuit comprises the first logical circuit with inverter functionality and the second logical circuit with inverter functionality, the input of the first logical circuit is electrically connected with modulating signal source 3, the output of the first logical circuit is electrically connected with the input of the second logical circuit, the output of the second logical circuit is electrically connected with the control end of single-pole double throw analog switch ASW2, and the output of the first logical circuit also is electrically connected with the control end of single-pole double throw analog switch ASW2.The first logical circuit is inverter U1-1, the inverter group of the second logical circuit for being consisted of by three inverter series connection, the output of described inverter group is electrically connected with the control end of described single-pole double throw analog switch ASW2, the input of inverter group is electrically connected with the output of described inverter U1-1, the input of inverter U1-1 is electrically connected with described modulating signal source, and the output of inverter U1-1 also is electrically connected with the control end of described single-pole double throw analog switch ASW1.The modulating frequency of the present embodiment is 1MHz, be to be modulation period 1 μ s, the rising and falling edges of the output signal after the modulation is no more than 10% of the cycle, the distributed capacitance C of single-pole double throw analog switch ASW1 common port is 10pf, working power in the present embodiment and bias supply are simple electric capacity holding circuit, and the resistance span of the resistance R 1 in the present embodiment is at 47 ~ 200 Ω.The resistance of resistance R 1 100 Ω not in the present embodiment.
During the present embodiment work, by time-delay dual output circuit is set, in prior art, two opposite modulation signal level conversion that modulating signal source is exported simultaneously are a modulation signal level and the modulation signal level with time-delay characteristics, and two modulation signal level are opposite, when modulation signal is logic high, the modulation signal of single-pole double throw analog switch ASW1 is that the modulation signal of low level, single-pole double throw analog switch ASW2 is high level, and this moment, single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 were communicated with working power.When modulation signal during by high step-down, the rising edge of single-pole double throw analog switch ASW1 control end signal will make single-pole double throw analog switch ASW2 switch to being communicated with bias supply by being communicated with working power; Simultaneously, the output of time-delay dual output circuit is through the anti-phase signal of time-delay, because being provided with enough logic elements connects, so delay time is greater than the switching time of single-pole double throw analog switch ASW1, single-pole double throw analog switch ASW2 is switched to being communicated with bias supply by being communicated with working power, the level of each modulating signal source output modulation signal changes, always so that single-pole double throw analog switch ASW1 switch first, then single-pole double throw analog switch ASW2 just switches, and at single-pole double throw analog switch ASW1 between transfer period, it is stable that single-pole double throw analog switch ASW2 keeps, single-pole double throw analog switch ASW2 just begins to switch after single-pole double throw analog switch ASW1 enters stable state, obviously, the present embodiment has been eliminated the burr that full port off-state that the inherent time-delay of analog switch t causes produces and has been disturbed.
Embodiment 2:
The present embodiment is substantially the same manner as Example 1, difference is: the time-delay dual output circuit 4 in the present embodiment is by an inverter, two and door and a NAND gate formation (referring to accompanying drawing 2), connect behind the equal short circuit of the input with door and NAND gate in the present embodiment and form the inverted logic circuit, the input of inverted logic circuit is electrically connected with the output of inverter, the output of inverted logic circuit is electrically connected with the control end of single-pole double throw analog switch ASW2, the input of inverter is electrically connected with the output of modulating signal source 3, and the output of inverter also is electrically connected with the control end of single-pole double throw analog switch ASW1.
Embodiment 3:
The present embodiment is substantially the same manner as Example 1, difference is: the time-delay dual output circuit 4 in the present embodiment consists of (referring to accompanying drawing 3) by three NAND gate and an inverter, series connection forms the inverted logic circuit behind the equal short circuit of the input of the NAND gate in the present embodiment, the input of inverted logic circuit is electrically connected with the output of inverter, the output of inverted logic circuit is electrically connected with the control end of single-pole double throw analog switch ASW2, the input of inverter is electrically connected with the output of modulating signal source 3, and the output of inverter also is electrically connected with the control end of single-pole double throw analog switch ASW1.
Embodiment 4:
The present embodiment is substantially the same manner as Example 1, and difference is: the resistance R 1 in the present embodiment is variable resistor.
Above-described embodiment is a kind of better scheme of the present utility model, is not that the utility model is done any pro forma restriction, also has other variant and remodeling under the prerequisite that does not exceed the technical scheme that claim puts down in writing.
Claims (9)
1. numerically controlled analog modulation circuit, comprise working power, bias supply, modulating signal source and single-pole double throw analog switch ASW1, single-pole double throw analog switch ASW2 and laser constant-current drive circuit, the normally opened contact of the normally-closed contact of single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 all is electrically connected with the output of working power, the normally opened contact of the normally-closed contact of single-pole double throw analog switch ASW2 and single-pole double throw analog switch ASW1 all is electrically connected with the output of bias supply, the common port of the common port of single-pole double throw analog switch ASW1 and single-pole double throw analog switch ASW2 all is electrically connected with the input of laser constant-current drive circuit, it is characterized in that: described numerically controlled analog modulation circuit also comprises time-delay dual output circuit, the input of time-delay dual output circuit is electrically connected with the output of modulating signal source, the direct output of time-delay dual output circuit is electrically connected with the control end of single-pole double throw analog switch ASW1, the time-delay output of time-delay dual output circuit is electrically connected with the control end of single-pole double throw analog switch ASW2, the output level of the direct output of time-delay dual output circuit equals the output level negate of modulating signal source, and the time-delay output level of time-delay dual output circuit is identical with the output level of modulating signal source.
2. numerically controlled analog modulation circuit according to claim 1 is characterized in that: the common port of described single-pole double throw analog switch ASW2 is electrically connected with the common port of single-pole double throw analog switch ASW1 by resistance R 1.
3. numerically controlled analog modulation circuit according to claim 1, it is characterized in that: time-delay dual output circuit comprises the first logical circuit with inverter functionality and the second logical circuit with inverter functionality, the input of described the first logical circuit is electrically connected with described modulating signal source, the output of described the first logical circuit is electrically connected with the input of described the second logical circuit, the output of described the second logical circuit is electrically connected with the control end of single-pole double throw analog switch ASW2, and the output of described the first logical circuit also is electrically connected with the control end of single-pole double throw analog switch ASW2.
4. numerically controlled analog modulation circuit according to claim 3, it is characterized in that: described the first logical circuit is inverter U1-1, the inverter group of the second logical circuit for being consisted of by the series connection of odd number inverter, the output of described inverter group is electrically connected with the control end of described single-pole double throw analog switch ASW2, the input of described inverter group is electrically connected with the output of described inverter U1-1, the input of described inverter U1-1 is electrically connected with described modulating signal source, and the output of described inverter U1-1 also is electrically connected with the control end of described single-pole double throw analog switch ASW1.
5. numerically controlled analog modulation circuit according to claim 4, it is characterized in that: described inverter group comprises at least three inverters.
6. numerically controlled analog modulation circuit according to claim 3 is characterized in that: described the second logical circuit is made of three logic circuit components series connection at least.
7. numerically controlled analog modulation circuit according to claim 3 is characterized in that: described the second logical circuit is made of five logic circuit components series connection at the most.
8. numerically controlled analog modulation circuit according to claim 2, it is characterized in that: described working power and bias supply are the electric capacity holding circuit that capacitance is 0.1 μ f, the modulating frequency of described working power and bias supply is 1MHz, and the span of described resistance R 1 is at 47 ~ 200 Ω.
9. numerically controlled analog modulation circuit according to claim 2 is characterized in that: described resistance R 1 is variable resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220265298 CN202663370U (en) | 2012-06-07 | 2012-06-07 | Digital controlled analogue modulation circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220265298 CN202663370U (en) | 2012-06-07 | 2012-06-07 | Digital controlled analogue modulation circuit |
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| CN202663370U true CN202663370U (en) | 2013-01-09 |
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| CN 201220265298 Expired - Fee Related CN202663370U (en) | 2012-06-07 | 2012-06-07 | Digital controlled analogue modulation circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790606A (en) * | 2012-06-07 | 2012-11-21 | 杭州东城图像技术有限公司 | Digital controlled analog modulation circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102790606A (en) * | 2012-06-07 | 2012-11-21 | 杭州东城图像技术有限公司 | Digital controlled analog modulation circuit |
| CN102790606B (en) * | 2012-06-07 | 2015-11-18 | 杭州东城图像技术有限公司 | Numerically controlled analog modulation circuit |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130109 Termination date: 20200607 |