CN202564351U - Multi-substrate exposed type packaging structure with single-circle pins and multiple normal and flip chips - Google Patents

Multi-substrate exposed type packaging structure with single-circle pins and multiple normal and flip chips Download PDF

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Publication number
CN202564351U
CN202564351U CN201220204480.XU CN201220204480U CN202564351U CN 202564351 U CN202564351 U CN 202564351U CN 201220204480 U CN201220204480 U CN 201220204480U CN 202564351 U CN202564351 U CN 202564351U
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China
Prior art keywords
chip
pin
dao
metal
zone
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Expired - Lifetime
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CN201220204480.XU
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Chinese (zh)
Inventor
王新潮
李维平
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN201220204480.XU priority Critical patent/CN202564351U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The utility model relates to a multi-substrate exposed type packaging structure with single-circle pins and multiple normal and flip chips. The packaging structure comprises multiple substrates (1), the single-circle pins (2), a first chip (3) and a second chip (4). The first chip (3) is arranged on the front faces of the substrates (1) and the pins (2), the second chip (4) is mounted on the first chip (3) in a flip manner, and bottom filling glue (11) is filled between the bottom of the second chip (4) and the front face of the first chip (3). The front face of the first chip (3) is connected with the front faces of the pins (2) through metal wires (6), the surface of plastic packaging materials (7) on the lower portions of the substrates (1) and the pins (2) are provided with small holes (8), and metal balls (10) are arranged in the small holes (8). The packaging structure has the advantages that manufacturing cost is lowered, safety and reliability of a packaging part are improved, environment pollution is reduced, and design and manufacturing of high-density lines can be truly realized.

Description

Many base island exposed type individual pen multicore sheet formal dress flip-chip packaged structures
Technical field
The utility model relates to a kind of how base island exposed type individual pen multicore sheet formal dress flip-chip packaged structure, belongs to the semiconductor packaging field.
Background technology
The manufacturing process flow of traditional high-density base board encapsulating structure is as follows:
Step 1, referring to Fig. 3, get the substrate that a glass fiber material is processed,
Step 2, referring to Fig. 4, perforate on desired position on the glass fiber substrate,
Step 3, referring to Fig. 5, at the back side of glass fiber substrate coating one deck Copper Foil,
Step 4, referring to Fig. 6, insert conductive materials in the position of glass fiber substrate punching,
Step 5, referring to Fig. 7, at positive coating one deck Copper Foil of glass fiber substrate,
Step 6, referring to Fig. 8, the coating photoresistance film on glass fiber substrate surface,
Step 7, referring to Fig. 9, the photoresistance film is carried out exposure imaging in the position of needs windows,
Step 8, referring to Figure 10, the part that completion is windowed is carried out etching,
Step 9, referring to Figure 11, the photoresistance film of substrate surface is divested,
Step 10, referring to Figure 12, carry out the coating of anti-welding lacquer (being commonly called as green lacquer) on the surface of copper foil circuit layer,
Step 11, referring to Figure 13, need carry out load and the zone of routing bonding of back operation at anti-welding lacquer and window,
Step 12, referring to Figure 14, electroplate in the zone that step 11 is windowed, form Ji Dao and pin relatively,
Step 13, accomplish follow-up load, routing, seal, concerned process steps such as cutting.
Above-mentioned traditional high-density base board encapsulating structure exists following deficiency and defective:
1, many glass fiber materials of one deck, same also many costs of layer of glass;
2, because must use glass fiber, so with regard to many thickness space of about 100 ~ 150 μ m of layer of glass thickness;
3, glass fiber itself is exactly a kind of foaming substance, so easily because time of placing and environment suck moisture and moisture, directly have influence on the security capabilities of reliability or the grade of reliability;
4, the fiberglass surfacing Copper Foil metal layer thickness of about 50 ~ 100 μ m of one deck that has been covered; And the etching of metal level circuit and circuit distance also because the etched gap that the characteristic of etching factor can only be accomplished 50 ~ 100 μ m (referring to Figure 15; Best making ability is that etched gap is equal to the thickness that is etched object approximately), so the design of accomplishing high-density line and manufacturing that can't be real;
5, because must use the Copper Foil metal level, and the Copper Foil metal level is the mode that the employing high pressure is pasted, so the thickness of Copper Foil is difficult to be lower than the thickness of 50 μ m, otherwise just is difficult to operation like out-of-flatness or Copper Foil breakage or Copper Foil extension displacement or the like;
6, also because the whole base plate material is to adopt glass fiber material, thus significantly increased thickness 100 ~ 150 μ m of glass layer, can't be real accomplish ultra-thin encapsulation;
7, the traditional glass fiber stick on Copper Foil technology because material property difference very big (coefficient of expansion) causes stress deformation easily in the operation of adverse circumstances, directly have influence on precision and element and substrate adherence and reliability that element loads.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency, and a kind of how base island exposed type individual pen multicore sheet formal dress flip-chip packaged structure is provided, and its technology is simple; Need not use glass layer; Reduce manufacturing cost, improved the fail safe and the reliability of packaging body, reduced the environmental pollution that glass fiber material brings; And the metal substrate line layer adopts is electro-plating method, can really accomplish the design and the manufacturing of high-density line.
The purpose of the utility model is achieved in that a kind of how base island exposed type individual pen multicore sheet formal dress flip-chip packaged structure; It comprises Ji Dao, pin, first chip and second chip; Said Ji Dao has a plurality of; Said first chip is arranged at a plurality of Ji Dao through conduction or non-conductive bonding material and pin is positive, and said second flip-chip is provided with underfill between said second chip bottom and first chip front side on first chip; Be connected with metal wire between said first chip front side and the pin front; Zone and first chip, second chip and the metal wire of zone, Ji Dao and the pin bottom on zone, Ji Dao and pin top between zone, pin and the pin between zone, Ji Dao and the pin of periphery, said basic island all are encapsulated with plastic packaging material outward, offer aperture on the plastic packaging material surface of said Ji Dao and pin bottom, and said aperture is connected with the Ji Dao or the pin back side; Be provided with metal ball in the said aperture, said metal ball contacts with the Ji Dao or the pin back side.
Be provided with coat of metal between said metal ball and Ji Dao or the pin back side.
Said Ji Dao comprises Ji Dao top, Ji Dao bottom and intermediate barrier layers, and said Ji Dao top and Ji Dao bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
Said pin comprises pin top, pin bottom and intermediate barrier layers, and said pin top and pin bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
Compared with prior art, the utlity model has following beneficial effect:
1, the utility model need not use glass layer, so can reduce the cost that glass layer brings;
2, the utility model does not use the foaming substance of glass layer, so the grade of reliability can improve again, the fail safe to packaging body will improve relatively;
3, the utility model need not use the glass layer material, so just can reduce the environmental pollution that glass fiber material brings;
What 4, the two-dimensional metallic substrate circuit layer of the utility model was adopted is electro-plating method; And the gross thickness of electrodeposited coating is about 10 ~ 15 μ m; And the gap between circuit and the circuit can reach the gap below the 25 μ m easily, so can accomplish the technical capability of pin circuit tiling in the high density veritably;
5, the two-dimensional metallic substrate of the utility model is the metal level galvanoplastic because of what adopt; So the technology than glass fiber high pressure Copper Foil metal level is come simply, and do not have metal level because high pressure produces bad or puzzled that metal level out-of-flatness, metal level breakage and metal level extend and be shifted;
6, the two-dimensional metallic substrate circuit layer of the utility model is to carry out metal plating on the surface of metal base; So the material characteristic is basic identical; So the internal stress of coating circuit and metal base is basic identical, can carries out the back engineering (like the surface mount work of high temperature eutectic load, high temperature tin material scolder load and high temperature passive device) of adverse circumstances easily and be not easy to produce stress deformation.
Description of drawings
Fig. 1 is the sketch map of a kind of how base island exposed type individual pen multicore sheet formal dress flip-chip packaged structure of the utility model.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 ~ Figure 14 is each operation sketch map of the manufacturing process flow of traditional high-density base board encapsulating structure.
Figure 15 is the etching situation sketch map of fiberglass surfacing Copper Foil metal level.
Wherein:
Base island 1
Pin 2
First chip 3
Second chip 4
Conduction or non-conductive bonding material 5
Metal wire 6
Plastic packaging material 7
Aperture 8
Coat of metal 9
Metal ball 10
Underfill 11.
Embodiment
Referring to Fig. 1, Fig. 2; A kind of how base island exposed type individual pen multicore sheet formal dress flip-chip packaged structure of the utility model; It comprises basic island 1, pin 2, first chip 3 and second chip 4; Said Ji Dao has a plurality of; Said first chip 3 is arranged at a plurality of basic islands 1 and pin 2 fronts through conduction or non-conductive bonding material 5, and 4 upside-down mountings of said second chip are provided with underfill 11 between said second chip, 4 bottoms and first chip, 3 fronts on first chip 3; Said first chip 3 positive with pin 2 fronts between be connected with metal wire 6; The zone of zone, basic island 1 and pin 2 bottoms on zone, basic island 1 and pin 2 tops between zone, pin 2 and the pin 2 between peripheral zone, basic island 1 and the pin 2 in said basic island 1 and first chip 3, second chip 4 and the metal wire 6 outer plastic packaging materials 7 that all are encapsulated with offer aperture 8 on plastic packaging material 7 surfaces of said basic island 1 and pin 2 bottoms, and said aperture 8 is connected with the basic island 1 or pin 2 back sides; Be provided with metal ball 10 in the said aperture 8, said metal ball 10 contacts with the basic island 1 or pin 2 back sides.
Be provided with coat of metal 9 between said metal ball 10 and basic island 1 or pin 2 back sides, said coat of metal 9 is an oxidation inhibitor.
Said metal ball 10 materials adopt tin or ashbury metal.
Said basic island 1 comprises Ji Dao top, Ji Dao bottom and intermediate barrier layers, and said Ji Dao top and Ji Dao bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
Said pin 2 comprises pin top, pin bottom and intermediate barrier layers, and said pin top and pin bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.

Claims (4)

1. base island exposed type individual pen multicore sheet formal dress flip-chip packaged structure more than a kind; It is characterized in that: it comprises Ji Dao (1), pin (2), first chip (3) and second chip (4); Said Ji Dao (1) has a plurality of; Said first chip (3) is arranged at a plurality of Ji Dao (1) and pin (2) front through conduction or non-conductive bonding material (5); Said second chip (4) upside-down mounting is on first chip (3); Be provided with underfill (11) between said second chip (4) bottom and first chip (3) front; Said first chip (3) positive with pin (2) front between be connected with metal wire (6); The zone of zone, Ji Dao (1) and pin (2) bottom on zone, Ji Dao (1) and pin (2) top between zone, pin (2) and the pin (2) between zone, Ji Dao (1) and the pin (2) of said Ji Dao (1) periphery and first chip (3), second chip (4) and metal wire (6) are outer all to be encapsulated with plastic packaging material (7), offers aperture (8) on plastic packaging material (7) surface of said Ji Dao (1) and pin (2) bottom, and said aperture (8) is connected with the Ji Dao (1) or pin (2) back side; Be provided with metal ball (10) in the said aperture (8), said metal ball (10) contacts with the Ji Dao (1) or pin (2) back side.
2. a kind of how base island exposed type individual pen multicore sheet formal dress flip-chip packaged structure according to claim 1 is characterized in that: be provided with coat of metal (9) between said metal ball (10) and Ji Dao (1) or pin (2) back side.
3. a kind of how base island exposed type individual pen multicore sheet formal dress flip-chip packaged structure according to claim 1; It is characterized in that: said Ji Dao (1) comprises Ji Dao top, Ji Dao bottom and intermediate barrier layers; Said Ji Dao top and Ji Dao bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
4. a kind of how base island exposed type individual pen multicore sheet formal dress flip-chip packaged structure according to claim 1; It is characterized in that: said pin (2) comprises pin top, pin bottom and intermediate barrier layers; Said pin top and pin bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
CN201220204480.XU 2012-05-09 2012-05-09 Multi-substrate exposed type packaging structure with single-circle pins and multiple normal and flip chips Expired - Lifetime CN202564351U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201220204480.XU CN202564351U (en) 2012-05-09 2012-05-09 Multi-substrate exposed type packaging structure with single-circle pins and multiple normal and flip chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201220204480.XU CN202564351U (en) 2012-05-09 2012-05-09 Multi-substrate exposed type packaging structure with single-circle pins and multiple normal and flip chips

Publications (1)

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CN202564351U true CN202564351U (en) 2012-11-28

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Granted publication date: 20121128

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