CN202564251U - Single base island exposed type single-circle multi-chip positive-and-inverse packaging passive device packaging structure - Google Patents
Single base island exposed type single-circle multi-chip positive-and-inverse packaging passive device packaging structure Download PDFInfo
- Publication number
- CN202564251U CN202564251U CN201220204481.4U CN201220204481U CN202564251U CN 202564251 U CN202564251 U CN 202564251U CN 201220204481 U CN201220204481 U CN 201220204481U CN 202564251 U CN202564251 U CN 202564251U
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- Prior art keywords
- pin
- chip
- dao
- passive device
- exposed type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to which comprises a single base island exposed type single-circle multi-chip positive-and-inverse packaging passive device packaging structure which comprises base islands (1), pins (2), a first chip (3) and a second chip (4), wherein the first chip (3) is arranged on the front faces of the base islands (1) and the pins (2), and the second chip (4) is arranged on the first chip (3) in an inverse packaging mode. Bottom filling glue (11) is arranged between the bottom of the second chip (4) and the front face of the first chip (3), metal wires (6) are connected between the front face of the first chip (3) and the front faces of the pins (2), small holes (8) are arranged on the surfaces of plastic package materials (7) on the lower portions of the base islands (1) and the pins (2), metal balls (10) are arranged inside the small holes (8), and passive devices (12) are connected between the pins (2) in a crossover mode. The single base island exposed type single-circle multi-chip positive-and-inverse packaging passive device packaging structure has the advantages of reducing the manufacturing cost, improving the safety and reliability of a packaging body, and therefore high density circuit design and manufacturing can be really achieved.
Description
Technical field
The utility model relates to the base island exposed type individual pen of a kind of list multicore sheet formal dress upside-down mounting passive device encapsulating structure, belongs to the semiconductor packaging field.
Background technology
The manufacturing process flow of traditional high-density base board encapsulating structure is as follows:
Step 13, accomplish follow-up load, routing, seal, concerned process steps such as cutting.
Above-mentioned traditional high-density base board encapsulating structure exists following deficiency and defective:
1, many glass fiber materials of one deck, same also many costs of layer of glass;
2, because must use glass fiber, so with regard to many thickness space of about 100 ~ 150 μ m of layer of glass thickness;
3, glass fiber itself is exactly a kind of foaming substance, so easily because time of placing and environment suck moisture and moisture, directly have influence on the security capabilities of reliability or the grade of reliability;
4, the fiberglass surfacing Copper Foil metal layer thickness of about 50 ~ 100 μ m of one deck that has been covered; And the etching of metal level circuit and circuit distance also because the etched gap that the characteristic of etching factor can only be accomplished 50 ~ 100 μ m (referring to Figure 15; Best making ability is that etched gap is equal to the thickness that is etched object approximately), so the design of accomplishing high-density line and manufacturing that can't be real;
5, because must use the Copper Foil metal level, and the Copper Foil metal level is the mode that the employing high pressure is pasted, so the thickness of Copper Foil is difficult to be lower than the thickness of 50 μ m, otherwise just is difficult to operation like out-of-flatness or Copper Foil breakage or Copper Foil extension displacement or the like;
6, also because the whole base plate material is to adopt glass fiber material, thus significantly increased thickness 100 ~ 150 μ m of glass layer, can't be real accomplish ultra-thin encapsulation;
7, the traditional glass fiber stick on Copper Foil technology because material property difference very big (coefficient of expansion) causes stress deformation easily in the operation of adverse circumstances, directly have influence on precision and element and substrate adherence and reliability that element loads.
Summary of the invention
The purpose of the utility model is to overcome above-mentioned deficiency, and the base island exposed type individual pen of a kind of list multicore sheet formal dress upside-down mounting passive device encapsulating structure is provided, and its technology is simple; Need not use glass layer; Reduce manufacturing cost, improved the fail safe and the reliability of packaging body, reduced the environmental pollution that glass fiber material brings; And the metal substrate line layer adopts is electro-plating method, can really accomplish the design and the manufacturing of high-density line.
The purpose of the utility model is achieved in that the base island exposed type individual pen of a kind of list multicore sheet formal dress upside-down mounting passive device encapsulating structure; It comprises Ji Dao, pin, first chip and second chip; Said first chip is arranged at Ji Dao through conduction or non-conductive bonding material and pin is positive; Said second flip-chip is on first chip; Be provided with underfill between said second chip bottom and first chip front side, be connected with metal wire between said first chip front side and the pin front, zone and first chip, second chip and the metal wire of zone, Ji Dao and the pin bottom on zone, Ji Dao and pin top between zone, pin and the pin between peripheral zone, Ji Dao and the pin in said basic island all are encapsulated with plastic packaging material outward; Offer aperture on the plastic packaging material surface of said Ji Dao and pin bottom; Said aperture is connected with the Ji Dao or the pin back side, is provided with metal ball in the said aperture, and said metal ball contacts with the Ji Dao or the pin back side; Cross-over connection passive device between said pin and the pin, said passive device cross-over connection in pin between the positive and pin front or cross-over connection between the pin back side and the pin back side.
Be provided with coat of metal between said metal ball and Ji Dao or the pin back side.
Said Ji Dao comprises Ji Dao top, Ji Dao bottom and intermediate barrier layers, and said Ji Dao top and Ji Dao bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
Said pin comprises pin top, pin bottom and intermediate barrier layers, and said pin top and pin bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
Compared with prior art, the utlity model has following beneficial effect:
1, the utility model need not use glass layer, so can reduce the cost that glass layer brings;
2, the utility model does not use the foaming substance of glass layer, so the grade of reliability can improve again, the fail safe to packaging body will improve relatively;
3, the utility model need not use the glass layer material, so just can reduce the environmental pollution that glass fiber material brings;
What 4, the two-dimensional metallic substrate circuit layer of the utility model was adopted is electro-plating method; And the gross thickness of electrodeposited coating is about 10 ~ 15 μ m; And the gap between circuit and the circuit can reach the gap below the 25 μ m easily, so can accomplish the technical capability of pin circuit tiling in the high density veritably;
5, the two-dimensional metallic substrate of the utility model is the metal level galvanoplastic because of what adopt; So the technology than glass fiber high pressure Copper Foil metal level is come simply, and do not have metal level because high pressure produces bad or puzzled that metal level out-of-flatness, metal level breakage and metal level extend and be shifted;
6, the two-dimensional metallic substrate circuit layer of the utility model is to carry out metal plating on the surface of metal base; So the material characteristic is basic identical; So the internal stress of coating circuit and metal base is basic identical, can carries out the back engineering (like the surface mount work of high temperature eutectic load, high temperature tin material scolder load and high temperature passive device) of adverse circumstances easily and be not easy to produce stress deformation.
Description of drawings
Fig. 1 is the sketch map of the base island exposed type individual pen of a kind of list of the utility model multicore sheet formal dress upside-down mounting passive device encapsulating structure.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 ~ Figure 14 is each operation sketch map of the manufacturing process flow of traditional high-density base board encapsulating structure.
Figure 15 is the etching situation sketch map of fiberglass surfacing Copper Foil metal level.
Wherein:
Base island 1
Conduction or non-conductive bonding material 5
Coat of metal 9
Embodiment
Referring to Fig. 1, Fig. 2; The base island exposed type individual pen of a kind of list of the utility model multicore sheet formal dress upside-down mounting passive device encapsulating structure; It comprises basic island 1, pin 2, first chip 3 and second chip 4; Said first chip 3 is arranged at basic island 1 and pin 2 fronts through conduction or non-conductive bonding material 5; 4 upside-down mountings of said second chip are on first chip 3; Be provided with underfill 11 between said second chip, 4 bottoms and first chip, 3 fronts, said first chip 3 positive with pin 2 fronts between be connected with metal wire 6, zone, basic island 1 and pin 2 bottoms on zone, basic island 1 and pin 2 tops between zone, pin 2 and the pin 2 between peripheral zone, basic island 1 and the pin 2 in said basic island 1 regional and first chip 3, second chip 4 and metal wire 6 all are encapsulated with plastic packaging materials 7 outward; Offer aperture 8 on plastic packaging material 7 surfaces of said basic island 1 and pin 2 bottoms; Said aperture 8 is connected with the basic island 1 or pin 2 back sides, is provided with metal ball 10 in the said aperture 8, and said metal ball 10 contacts with the basic island 1 or pin 2 back sides; Cross-over connection passive device 12 between said pin 2 and the pin 2, said passive device 12 cross-over connections in pin 2 between positive and pin 2 fronts or cross-over connection between pin 2 back sides and pin 2 back sides.
Be provided with coat of metal 9 between said metal ball 10 and basic island 1 or pin 2 back sides, said coat of metal 9 is an oxidation inhibitor.
Said metal ball 10 materials adopt tin or ashbury metal.
Said basic island 1 comprises Ji Dao top, Ji Dao bottom and intermediate barrier layers, and said Ji Dao top and Ji Dao bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
Said pin 2 comprises pin top, pin bottom and intermediate barrier layers, and said pin top and pin bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
Claims (4)
1. the base island exposed type individual pen of list multicore sheet formal dress upside-down mounting passive device encapsulating structure; It is characterized in that: it comprises Ji Dao (1), pin (2), first chip (3) and second chip (4); Said first chip (3) is arranged at Ji Dao (1) and pin (2) front through conduction or non-conductive bonding material (5); Said second chip (4) upside-down mounting is on first chip (3); Be provided with underfill (11) between said second chip (4) bottom and first chip (3) front; Said first chip (3) positive with pin (2) front between be connected with metal wire (6); The outer plastic packaging material (7) that all is encapsulated with of the zone of zone, Ji Dao (1) and pin (2) bottom on zone, Ji Dao (1) and pin (2) top between zone, pin (2) and the pin (2) between zone, Ji Dao (1) and the pin (2) of said Ji Dao (1) periphery and first chip (3), second chip (4) and metal wire (6); Offer aperture (8) on plastic packaging material (7) surface of said Ji Dao (1) and pin (2) bottom; Said aperture (8) is connected with the Ji Dao (1) or pin (2) back side; Be provided with metal ball (10) in the said aperture (8); Said metal ball (10) contacts with the Ji Dao (1) or pin (2) back side, cross-over connection passive device (12) between said pin (2) and the pin (2), said passive device (12) cross-over connection in pin (2) between positive and pin (2) front or cross-over connection between pin (2) back side and pin (2) back side.
2. the base island exposed type individual pen of a kind of list according to claim 1 multicore sheet formal dress upside-down mounting passive device encapsulating structure is characterized in that: be provided with coat of metal (9) between said metal ball (10) and Ji Dao (1) or pin (2) back side.
3. the base island exposed type individual pen of a kind of list according to claim 1 multicore sheet formal dress upside-down mounting passive device encapsulating structure; It is characterized in that: said Ji Dao (1) comprises Ji Dao top, Ji Dao bottom and intermediate barrier layers; Said Ji Dao top and Ji Dao bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
4. the base island exposed type individual pen of a kind of list according to claim 1 multicore sheet formal dress upside-down mounting passive device encapsulating structure; It is characterized in that: said pin (2) comprises pin top, pin bottom and intermediate barrier layers; Said pin top and pin bottom form by the single or multiple lift metal plating, and said intermediate barrier layers is nickel dam, titanium layer or copper layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201220204481.4U CN202564251U (en) | 2012-05-09 | 2012-05-09 | Single base island exposed type single-circle multi-chip positive-and-inverse packaging passive device packaging structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201220204481.4U CN202564251U (en) | 2012-05-09 | 2012-05-09 | Single base island exposed type single-circle multi-chip positive-and-inverse packaging passive device packaging structure |
Publications (1)
Publication Number | Publication Date |
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CN202564251U true CN202564251U (en) | 2012-11-28 |
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CN201220204481.4U Expired - Lifetime CN202564251U (en) | 2012-05-09 | 2012-05-09 | Single base island exposed type single-circle multi-chip positive-and-inverse packaging passive device packaging structure |
Country Status (1)
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CN (1) | CN202564251U (en) |
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2012
- 2012-05-09 CN CN201220204481.4U patent/CN202564251U/en not_active Expired - Lifetime
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GR01 | Patent grant | ||
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CX01 | Expiry of patent term |
Granted publication date: 20121128 |