CN202548823U - Non-blocking coprocessor interface system - Google Patents
Non-blocking coprocessor interface system Download PDFInfo
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- CN202548823U CN202548823U CN2012200441744U CN201220044174U CN202548823U CN 202548823 U CN202548823 U CN 202548823U CN 2012200441744 U CN2012200441744 U CN 2012200441744U CN 201220044174 U CN201220044174 U CN 201220044174U CN 202548823 U CN202548823 U CN 202548823U
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Abstract
The utility model relates to a non-blocking coprocessor interface system. The non-blocking coprocessor interface system comprises a primary processor, at least one parameter register, at least one coprocessor and an external register, wherein the primary processor is used for transmitting a call instruction to the coprocessor, continuously executing subsequent instructions after finishing transmitting, and transmitting a return instruction to the coprocessor when the primary processor needs an operating result of the coprocessor; the parameter register is used for reading operating parameters from a data bus according to the call instruction transmitted by the primary processor, supplying the operating parameters to the coprocessor, reading return parameters from the data bus according to the return instruction transmitted by the primary processor, and supplying the return parameters to the coprocessor; the coprocessor executes an operation according to the operating parameters, comprises an internal register, and stores an operating result in the internal register after finishing the operation; the operating result stored in the internal register of the coprocessor is written in the external register by the coprocessor according to the return parameters; and the operating result in the external register is read by the primary processor.
Description
Technical field
The utility model provides a kind of coprocessor interface system, particularly a kind of coprocessor interface system of unblock formula.
Background technology
In the system based on microprocessor, coprocessor is generally used for assisting primary processor to accomplish specific operation, and the serviceability that improves system is played an important role.And the interface mode between coprocessor and the primary processor has determined the communication delay between primary processor and the coprocessor, and performances such as data throughput also are one of bottlenecks of entire system performance simultaneously.
Existing coprocessor interface mainly comprises block type coprocessor sync cap and register trigger-type coprocessor asynchronous interface.
The principle of block type coprocessor sync cap is; When needs were used coprocessor, primary processor sent enabled instruction to coprocessor, and coprocessor is operated according to this instruction; During co processor operation; The instruction pipelining of primary processor quits work and waits for the operating result of coprocessor, and to primary processor return result, after this primary processor is proceeded subsequent operation after the coprocessor complete operation.The floating-point coprocessor interface of ARM is exactly typical block type coprocessor sync cap.The advantage of this interface is to make primary processor and coprocessor hardware-switch information efficiency higher.But because this interface has adopted " obstruction mode ", promptly primary processor and coprocessor are in same thread, and primary processor need not quit work and wait for before coprocessor instruction finishes as yet fully, has therefore influenced the operational efficiency of primary processor.
The principle of register trigger-type coprocessor asynchronous interface is; Primary processor maps to external register with the enabled instruction of coprocessor; Coprocessor reads instruction in the external register line operate of going forward side by side, and primary processor works on during co processor operation, after the coprocessor complete operation; With returning to external register as a result, primary processor obtains this result through reading external register.This asynchronous interface mode of the many employings of the special purpose interface that the chip designer designs voluntarily.The advantage of this interface is to make coprocessor work in different processes with primary processor, and primary processor is no longer waited for coprocessor, and this interface can support a plurality of coprocessor parallel runnings, thereby has improved system performance.Yet the shortcoming of this interface is to depend on the read-write of external register, and that the external register read and write access usually postpones is big, and flux is low, and the visit of register is needed the dozens or even hundreds of clock period usually, can only visit 16 or 32 usually at every turn.And the visit itself to register is " block type "; That is to say; During access register; Primary processor and coprocessor all quit work, and this makes the access speed of register and flux become the bottleneck of communicating by letter between primary processor and the coprocessor, and therefore this interface is not suitable for having between primary processor and the coprocessor application scenario of more interchange.
The utility model content
The purpose of the utility model is to propose a kind of unblock coprocessor interface system, overcomes the problems referred to above of existing coprocessor interface.The coprocessor interface system of the utility model had both had high-level efficiency message exchange ability, also had the advantage of multithreading ability and highly-parallel simultaneously.
According to the one side of the utility model, a kind of unblock coprocessor interface system has been proposed, it is characterized in that this system comprises:
Primary processor; Its output terminal connects at least one parameter register and at least one coprocessor; This primary processor sends call instruction to coprocessor; And, when primary processor needs the operating result of coprocessor, send link order to coprocessor by primary processor sending completion continued execution subsequent instructions;
At least one parameter register; The input end of each parameter register is connected to primary processor and data bus respectively; The output terminal of each parameter register is connected to coprocessor; The call instruction that said parameter register sends according to primary processor offering coprocessor, and reads return parameters to offer coprocessor according to the link order that primary processor sends from said data bus from said data bus read operation parameter;
At least one coprocessor, according to said operating parameter executable operations, said coprocessor comprises internal register, coprocessor is stored in operating result in the said internal register after operation is accomplished;
External register, coprocessor writes this external register according to said return parameters with the operating result of storing in the coprocessor internal register; Primary processor reads the operating result in this external register.
Preferably, this system also comprises the utmost point width bus of the register read-write of supporting a plurality of unit widths; And at least one parameter register, comprise the special register that is associated with this utmost point width bus, and this special register is according to call instruction or link order, and the register to a plurality of unit widths reads simultaneously.
Preferably, this system also can comprise configuration register, is used to store the static configuration information of coprocessor.
Preferably, there are a plurality of coprocessors, and distinguish each coprocessor through the coprocessor ID that is included in the call instruction.
The unblock coprocessor interface system of the utility model supports the out of order visit between a plurality of coprocessors and a plurality of hardware accelerator, has high dirigibility.
The unblock coprocessor interface system of the utility model can support utmost point width bus, and data throughput increases greatly.
The unblock coprocessor interface system of the utility model can be compatible with traditional block type coprocessor sync cap.
Description of drawings
Fig. 1 is the process flow diagram according to a kind of unblock coprocessor interface method of an embodiment of the utility model;
Fig. 2 is the block diagram according to the unblock coprocessor interface system of an embodiment of the utility model;
Fig. 3 is the block diagram according to the unblock coprocessor interface system of another embodiment of the utility model;
Fig. 4 has described a specific embodiment according to the unblock formula coprocessor interface system of the utility model.
Embodiment
The ultimate principle of the unblock coprocessor interface method of the utility model is:
-send call instruction by primary processor to coprocessor;
Promptly finish after-call instruction sends, primary processor continues to carry out subsequent instructions;
-coprocessor is according to the call instruction complete operation and bear results;
-when primary processor need use this as a result, send link order to collect the result to coprocessor by primary processor.
Use the described method of the utility model; Communication between primary processor and the coprocessor need not passed through external register; Therefore has the message exchange ability as association handles sync cap; Primary processor is in different processes with coprocessor simultaneously, therefore has the such multi-threaded parallel ability to work of coprocessor asynchronous interface.
Fig. 1 is that this method mainly may further comprise the steps according to the process flow diagram of a kind of unblock coprocessor interface method of an embodiment of the utility model:
S101 sends call instruction by primary processor to coprocessor, and primary processor continues to carry out subsequent instructions after sending completion, obtains the operating parameter of coprocessor according to this call instruction;
S102, coprocessor is according to said operating parameter executable operations;
S103, coprocessor is stored in operating result in the internal register of coprocessor after operation is accomplished;
S104 when primary processor needs the operating result of coprocessor, sends link order by primary processor to coprocessor, and obtains return parameters according to this link order;
S105, coprocessor writes external register according to said return parameters with the operating result of storing in the coprocessor internal register;
S106, primary processor read the operating result in this external register.
Wherein, the operating parameter of coprocessor can comprise the operational order that coprocessor is to be accomplished, information such as service data, and return parameters can comprise information such as return address.This method can support primary processor to the calling of a plurality of coprocessors, and can distinguish each coprocessor through coprocessor ID, and coprocessor ID is the unique identifying information of each coprocessor, can be included in call instruction and the link order.Because each coprocessor and primary processor all have independently thread, therefore can realize the out of order visit between each coprocessor, make system flexibility increase.
In a modification of the utility model, primary processor all need send link order successively to each call instruction that each coprocessor sends.In this modification, coprocessor keeps the operating result that each call instruction produces, and obtains these operating results for primary processor through link order.
In another distortion of the utility model; Each coprocessor is only handled the call instruction that the last time receives; And only effective corresponding to the return results of this call instruction of receiving for the last time, the operating result of call instruction is before abandoned as not read then by primary processor in advance.For instance; If primary processor sends the call instruction that requires coprocessor A executable operations 1; Read operation 1 not as a result the time primary processor send the call instruction that requires association to handle A executable operations 2 again; Then operate 1 operating result and abandoned, the operating result of only preserving operation 2 supplies primary processor to read.This pattern is specially adapted to the sight that primary processor is carried out the order of anticipation severed finger; Promptly operating 1 is the operation that primary processor is prejudged according to probability; Be only the actual operation that will carry out and operate 2; When the actual operation that will carry out 2 and the operation of prejudging 1 not simultaneously, the result of coprocessor abort operation 1 result of reservation operations 2 only then.
In another distortion of the utility model; Primary processor can omit the step of sending call instruction, and directly sends link order, and the operating parameter of coprocessor is included in the link order; Coprocessor receives after the link order; Direct executable operations and return results, during the coprocessor executable operations, primary processor quits work; Wait for coprocessor complete operation and return results, this mode of operation has realized coprocessor interface of the utility model and the compatibility between the traditional block type coprocessor sync cap.
In an embodiment of the utility model, coprocessor can be read and write a plurality of registers simultaneously.That is to say; Be different from the traditional register data that at every turn can only read and write a unit width (for example 16 or 32); In the method according to the utility model, coprocessor can read while write the register data of a plurality of unit widths, for example reads while write 4 16 bit registers to visit 64 bit data or to read and write 8 16 bit registers to visit 128 bit data; Make coprocessor can support bus extremely wide and that delay is extremely low, thereby improved the message exchange ability greatly.
In one embodiment, can be the data that coprocessor provides a unit width through the data bus of routine, and be the data that coprocessor provides a plurality of unit widths, thereby improve the processing power of coprocessor through extremely wide data bus.In one example, can through call or link order in a field indicate coprocessor need read while write the register of what unit widths.
Fig. 2 is the block diagram according to the unblock coprocessor interface system of an embodiment of the utility model.Wherein, this interface system mainly comprises:
At least one parameter register 202; The input end of each parameter register 202 is connected to primary processor 201 and data bus 205 respectively; The output terminal of each parameter register 202 is connected to coprocessor 203; The call instruction that said parameter register 202 sends according to primary processor 201 offering coprocessor 203, and reads return parameters to offer coprocessor 203 according to the link order that primary processor 201 sends from said data bus 205 from said data bus 205 read operation parameters;
At least one coprocessor 203, according to said operating parameter executable operations, said coprocessor 203 comprises internal register 2031, coprocessor 203 is stored in operating result in the said internal register 2031 after operation is accomplished;
In another embodiment as shown in Figure 3; This system also comprises the utmost point width bus 2051 of the register read-write of supporting a plurality of unit widths; In at least one parameter register 202, comprise the parameter register 2021 that is associated with this utmost point width bus 2051, or be called special register, this special register can be according to call instruction or link order; Register to a plurality of unit widths reads simultaneously; For example read 64 or 128 simultaneously,, thereby greatly improved the work efficiency of coprocessor 203 as the input of coprocessor 203.
In another embodiment, this system also can comprise configuration register, is used to store the static configuration information of coprocessor, and this static configuration information can be by user definition.
Fig. 4 has described a specific embodiment according to the unblock formula coprocessor interface system of the utility model.Wherein, this system comprises main processor MP, coprocessor COP, parameter register UTP, VTP and XTP, coprocessor output register XWB, external register RF and configuration register COPRF.Wherein, Send call instruction by main processor MP; This call instruction has indicated the coprocessor ID that will call, and is activated with the corresponding coprocessor of this ID, i.e. coprocessor COP in this example; According to this call instruction; Parameter register VTP and XTP have read the operational order (being 16 in this example) of coprocessor COP and the operand (being 128 in this example) of coprocessor COP respectively, and coprocessor COP operates according to the data of parameter register VTP and XTP, and operating result is kept among the internal register IRF of coprocessor COP.When main processor MP sends link order; This link order has indicated the coprocessor ID that will call, i.e. coprocessor COP in this example is according to this link order; Parameter register UTP reads return parameters; Coprocessor COP is according to this return parameters, utilizes output register XWB to read the operating result among the internal register IRF and outputs to external register RF, and main processor MP externally reads this operating result among the register RF.
It should be noted; Above example only is an exemplary embodiment of the utility model; And and unrestricted the utility model; Wherein the quantity of parameter register is not limited to three, and the parameter classification that the figure place of parameter register and each parameter register read can be adjusted according to actual needs, also can be defined voluntarily by coprocessor.The quantity of coprocessor can be a plurality of, and discerns each coprocessor through coprocessor ID.
The foregoing description is principle and the effect thereof that is used for illustrative the utility model, but not is used to limit the utility model.Any those skilled in the art all can make amendment to the foregoing description under the spirit and category of the utility model.So the protection domain of the utility model, should be listed like claims of the utility model.
Claims (4)
1. unblock coprocessor interface system is characterized in that this system comprises:
Primary processor; Its output terminal connects at least one parameter register and at least one coprocessor; This primary processor sends call instruction to coprocessor; And, when primary processor needs the operating result of coprocessor, send link order to coprocessor by primary processor sending completion continued execution subsequent instructions;
At least one parameter register; The input end of each parameter register is connected to primary processor and data bus respectively; The output terminal of each parameter register is connected to coprocessor; The call instruction that said parameter register sends according to primary processor offering coprocessor, and reads return parameters to offer coprocessor according to the link order that primary processor sends from said data bus from said data bus read operation parameter;
At least one coprocessor, according to said operating parameter executable operations, said coprocessor comprises internal register, coprocessor is stored in operating result in the said internal register after operation is accomplished;
External register, coprocessor writes this external register according to said return parameters with the operating result of storing in the coprocessor internal register; Primary processor reads the operating result in this external register.
2. unblock coprocessor interface according to claim 1 system is characterized in that, this system also comprises the utmost point width bus of the register read-write of supporting a plurality of unit widths; And
In at least one parameter register, comprise the special register that is associated with this utmost point width bus, this special register is according to call instruction or link order, and the register to a plurality of unit widths reads simultaneously.
3. unblock coprocessor interface according to claim 1 system is characterized in that this system also can comprise configuration register, is used to store the static configuration information of coprocessor.
4. unblock coprocessor interface according to claim 1 system is characterized in that, has a plurality of coprocessors, and distinguishes each coprocessor through the coprocessor ID that is included in the call instruction.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200441744U CN202548823U (en) | 2012-02-10 | 2012-02-10 | Non-blocking coprocessor interface system |
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| CN2012200441744U CN202548823U (en) | 2012-02-10 | 2012-02-10 | Non-blocking coprocessor interface system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103246496A (en) * | 2012-02-10 | 2013-08-14 | 上海算芯微电子有限公司 | Non-blocking coprocessor interface method and non-blocking coprocessor interface system |
| WO2018000765A1 (en) * | 2016-06-27 | 2018-01-04 | 深圳市中兴微电子技术有限公司 | Co-processor, data reading method, processor system and storage medium |
-
2012
- 2012-02-10 CN CN2012200441744U patent/CN202548823U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103246496A (en) * | 2012-02-10 | 2013-08-14 | 上海算芯微电子有限公司 | Non-blocking coprocessor interface method and non-blocking coprocessor interface system |
| CN103246496B (en) * | 2012-02-10 | 2015-12-16 | 上海算芯微电子有限公司 | Unblock coprocessor interface method and system |
| WO2018000765A1 (en) * | 2016-06-27 | 2018-01-04 | 深圳市中兴微电子技术有限公司 | Co-processor, data reading method, processor system and storage medium |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Galaxycore Microelectronics (Shanghai) Co., Ltd. Assignor: Shanghai Suanxin Microelectronics Co., Ltd. Contract record no.: 2015990000743 Denomination of utility model: Non-blocking coprocessor interface system Granted publication date: 20121121 License type: Common License Record date: 20150821 |
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| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121121 |