CN202524319U - High efficiency grid-connected inverter circuit - Google Patents
High efficiency grid-connected inverter circuit Download PDFInfo
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- CN202524319U CN202524319U CN 201220015706 CN201220015706U CN202524319U CN 202524319 U CN202524319 U CN 202524319U CN 201220015706 CN201220015706 CN 201220015706 CN 201220015706 U CN201220015706 U CN 201220015706U CN 202524319 U CN202524319 U CN 202524319U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/30—Reactive power compensation
Abstract
The utility model relates to a high efficiency grid-connected inverter circuit. The high efficiency grid-connected inverter circuit comprises an enhanced voltage reduction chopper circuit and a controlled silicon power frequency phase inverter circuit, wherein the enhanced voltage reduction chopper circuit comprises an SPWM (Sinusoidal Pulse Width Modulation) modulated power switch tube, a double freewheel diode, a power factor adjusting power switch tube, a bypass low frequency switch, an inductor and a capacitor. Direct current is converted into a half sine wave by adjusting the duty ratio of the high frequency switch tube in the enhanced voltage reduction chopper circuit; and power factor adjustment can be realized by adjusting the conduction mode of the power factor adjusting power switch tube or the switch. The direct current half sine wave is subjected to phase inversion by the phase inverter circuit composed of four low frequency controlled silicons to obtain a full sine wave so as to finish inversion from direct current to sine alternating current. The high efficiency grid-connected inverter circuit provided by the utility model is simple in structure, strong in overcurrent resistance, high in stability, high in inversion efficiency and low in cost, and the number of high frequency tubes is reduced. In the switching and phase inverting process, a constant common mode voltage is produced from the alternating current output of the inverter, so that the common mode current is inhibited and the EMI (Electro-Magnetic Interference) interference is reduced.
Description
Technical field
The utility model relates to a kind of efficient grid-connected inverter circuit and control method, especially a kind of high conversion efficiency, low harmonics distortion degree, can carry out DC/AC grid-connected inverter circuit and control method that power factor is regulated simultaneously.
Background technology
The effect of grid-connected inverter circuit is that dc voltage conversion is become sinusoidal ac, and the supply power consumption equipment of realizing being incorporated into the power networks uses.High efficiency, low harmonics distortion degree are the key indexs of this technology; When generating electricity by way of merging two or more grid systems, also need be according to power scheduling instruction adjustment power factor.
The combining inverter technology that exists the at present four pipe full-bridge circuit structures that adopt more, as shown in Figure 2, adopt bipolarity modulation system or unipolarity modulation system.In the bipolarity modulation circuit, all with higher switching frequency work, the loss of switching tube is bigger, influences efficient for four switching tubes (shown in the frame of broken lines), and has bigger switching noise and current ripples amplitude.In the unipolarity modulation circuit, the common-mode voltage magnitude that inversion produces is bigger, and consequent common mode current increases along with the increase of switching frequency is linear, and harmonic distortion is more serious.
Summary of the invention
The purpose of the utility model is to overcome the deficiency that exists in the prior art; A kind of efficient grid-connected inverter circuit is provided; When power factor is 1 condition of work, only use a HF switch pipe to realize modulation, effectively reduce the HF switch loss, improved conversion efficiency; When power factor is not 1 condition of work; Only there are two HF switch plumbers to do; Can realize inversion simultaneously, be incorporated into the power networks and power factor controlling; Be grid-connected inverter circuit, can be widely used in wind-force, solar grid-connected inverter, microgrid inverter etc. and network source and inverter power supply technical applications, can satisfy the requirement that power factor is regulated simultaneously with very strong overload capacity.
The technical scheme that the utility model adopts is: a kind of efficient grid-connected inverter circuit (as shown in Figure 1) comprises enhancement mode buck circuit, controllable silicon commutation circuit, inverter current sample circuit, voltage and current detection circuit, controllable silicon commutation control circuit and SPWM control circuit.When the required power factor was regulated: if the inverter active power of output, the enhancement mode buck circuit had only a power switch to be in the SPWM modulation condition, and the another one power switch is in normally open; Regulate if inverter carries out reactive power, two power switchs all are on off state.
Described enhancement mode buck circuit comprises power switch Q1 (MOSFET or IGBT), power switch Q2 (MOSFET or IGBT); Diode D1, diode D2; Inductance L 1, inductance L 2, capacitor C 1 and low frequency switch Q3; Power switch Q1 drain electrode (or collector electrode) is joined with dc power anode and diode D2 negative electrode, and its source electrode (or emitter) joins with inductance L 1 one ends and diode D1 negative electrode; Power switch pipe Q2 drain electrode (or collector electrode) is connected with an end of diode D2 anode, inductance L 2, and its source electrode (or emitter) joins with an end of anode, dc power cathode and the low frequency switch of diode D1; Source electrode (or emitter), the diode D1 negative electrode of one end of inductance L 1 and Q1 join, and the end of one-way SCR anode and C1 joins in the other end and the commutating circuit; One end of inductance L 2 is connected with the anode of Q2 drain electrode (or collector electrode) and D2, and the other end is connected with controllable silicon negative electrode, capacitor C 1 and the end of low frequency switch Q3; The end of low frequency switch Q3 is connected with the source electrode (or emitter) of Q2, the anode of diode D1 and the negative pole of DC power supply, and the other end is connected with an end of controllable silicon negative electrode, capacitor C 1 and inductance L 2.
Described controllable silicon commutation circuit comprises 4 unidirectional controllable silicon S 1 ~ S4; Controllable silicon S1 and controllable silicon S2 form series, and controllable silicon S3 and controllable silicon S4 form series, and two series are in parallel; The anode of controllable silicon S1 and controllable silicon S3 joins; As the high voltage input, the negative electrode of controllable silicon S2 and controllable silicon S4 joins, as the low-voltage output.The tie point of the tie point of controllable silicon S1 and controllable silicon S2 and controllable silicon S3 and controllable silicon S4 connects to single-phase electrical network or AC load respectively as the single phase alternating current (A.C.) output.The drive signal of controllable silicon S1 and controllable silicon S4 is one group, and the drive signal of controllable silicon S2 and controllable silicon S3 is one group, and ON time respectively accounts for power frequency period half.
Said power switch Q1, power switch Q2 are the HF switch pipe, and selecting device for use is MOSEFT or IGBT, adopt SPWM control.
Said low frequency switch Q3 is operated in low frequency mode, and selecting device for use is relay, bidirectional triode thyristor, low frequency IGBT or MOSFFT etc.
Said controllable silicon S1 ~ S4 is the low frequency switching tube, and selecting device for use is unidirectional controllable silicon S CR or IGBT.
Described power factor is regulated; When inverter works in the unity power factor pattern; The enhancement mode buck circuit has only power switch Q1 to be in the SPWM modulation condition, low frequency switch closure, bypass another one power switch Q2 and inductance Q2; When Q1 turn-offs, constitute continuous current circuit with diode D1, inductance L 1.
Described power factor is regulated, and when inverter carried out the reactive power adjusting, Q1, Q2 need carry out switch simultaneously, and when Q1, Q2 turn-offed simultaneously, D2, C2, D1, L1 and L2 and commutating circuit constituted continuous current circuit, realized the control of reactive power.
The enhancement mode buck circuit of the utility model is accomplished the half-sinusoid modulation and power factor is regulated.Inverter can work in two kinds of patterns: unity power factor pattern and reactive power are regulated pattern, and under the unity power factor pattern, switching tube Q1 adopts SPWM control to see Fig. 4 in the circuit, convert the direct current energy of dc bus C2 into half-sinusoid; Under the reactive power adjusting pattern in the circuit switching tube Q1 and Q2 adopt SPWM control to see Fig. 5, convert the direct current energy of dc bus C2 into half-sinusoid, through adjusting the ON time of two groups of controllable silicon phase changers, change into sinusoidal all-wave to half-sinusoid.
The utility model has the advantages that:
Have only two HF switch pipes in the enhancement mode buck circuit in the entire circuit, so the switching loss of switching tube is very little, inversion efficiency is greatly improved;
Under the unity power factor pattern (power factor is 1), low frequency switch bypass HF switch Q2 and inductance L 2, thus switching loss and minimize line losses, maximizing efficiency;
Four power frequency controllable silicon overload capacity that adopt in the controllable silicon commutation circuit are strong, enhance system stability greatly, and devices switch loss and conduction loss are little; Improved system effectiveness; Device cost is low, can significantly reduce the cost of system, helps popularizing of new forms of energy combining inverter;
In the controllable silicon commutation circuit, the common-mode voltage that inversion produces is constant, produces common mode current thus near zero, can effectively suppress common mode current, has reduced system's conduction loss, guarantees the quality of inverter current.
On the basis of traditional Buck circuit, increase a switching tube and a diode in the enhancement mode buck circuit, can realize the power factor adjusting, can satisfy the adjustable demand of growing power factor.
The ingenious cooperation of enhancement mode buck circuit and commutation circuit has realized direct current input and the common mode inhibition that exchanges output, has effectively reduced EMI.
Description of drawings
Fig. 1 is that the utility model circuit is formed sketch map.
Fig. 2 is conventional four pipe full bridge inverter schematic diagrams.
Fig. 3 is the circuit theory diagrams of the utility model.
Fig. 4 is that sketch map takes place the SPWM signal (unity power factor pattern) of the utility model.
Fig. 5 is that sketch map takes place the SPWM signal (reactive power adjusting pattern) of the utility model.
Fig. 6 is that the utility model circuit (unity power factor pattern) drives sequential chart.
Fig. 7 is that the utility model circuit (reactive power adjusting pattern) drives sequential chart.
Fig. 8 is the utility model first quartile (unity power factor pattern) Q1 conducting isoboles.
Fig. 9 is that the utility model first quartile (unity power factor pattern) Q1 turn-offs isoboles.
Figure 10 is the utility model third quadrant (unity power factor pattern) Q1 conducting isoboles.
Figure 11 is that the utility model third quadrant (unity power factor pattern) Q1 turn-offs isoboles.
Figure 12 is that the utility model first quartile (reactive power adjusting pattern) Q1, Q2 turn-off isoboles.
Figure 13 is the utility model first quartile (reactive power adjusting pattern) Q1, Q2 conducting isoboles.
Figure 14 is the utility model second quadrant (reactive power adjusting pattern) Q1, Q2 conducting isoboles.
Figure 15 is that the utility model second quadrant (reactive power adjusting pattern) Q1, Q2 turn-off isoboles.
Figure 16 is the utility model third quadrant (reactive power adjusting pattern) Q1, Q2 conducting isoboles.
Figure 17 is that the utility model third quadrant (reactive power adjusting pattern) Q1, Q2 turn-off isoboles.
Figure 18 is the utility model four-quadrant (reactive power adjusting pattern) Q1, Q2 conducting isoboles.
Figure 19 is that the utility model four-quadrant (reactive power adjusting pattern) Q1, Q2 turn-off isoboles.
Embodiment
Like Fig. 1, Fig. 3, Fig. 4, Fig. 5, Fig. 6, shown in Figure 7; Efficient grid-connected inverter circuit comprises enhancement mode buck circuit, controllable silicon commutation circuit, inverter current sample circuit, voltage and current detection circuit, controllable silicon commutation control circuit and SPWM control circuit.
Described enhancement mode buck circuit comprises power switch Q1 (MOSFET or IGBT), power switch Q2 (MOSFET or IGBT); Diode D1, diode D2; Inductance L 1, inductance L 2, capacitor C 1 and low frequency switch Q3; Power switch Q1 drain electrode (or collector electrode) is joined with dc power anode and diode D2 negative electrode, and its source electrode (or emitter) joins with inductance L 1 one ends and diode D1 negative electrode; Power switch pipe Q2 drain electrode (or collector electrode) is connected with an end of diode D2 anode, inductance L 2, and its source electrode (or emitter) joins with an end of anode, dc power cathode and the low frequency switch of diode D1; Source electrode (or emitter), the diode D1 negative electrode of one end of inductance L 1 and Q1 join, and the end of one-way SCR anode and C1 joins in the other end and the commutating circuit; One end of inductance L 2 is connected with the anode of Q2 drain electrode (or collector electrode) and D2, and the other end is connected with controllable silicon negative electrode, capacitor C 1 and the end of low frequency switch Q3; The end of low frequency switch Q3 is connected with the source electrode (or emitter) of Q2, the anode of diode D1 and the negative pole of DC power supply, and the other end is connected with an end of controllable silicon negative electrode, capacitor C 1 and inductance L 2.
Described controllable silicon commutation circuit comprises 4 unidirectional controllable silicon S 1 ~ S4; Controllable silicon S1 and controllable silicon S2 form series, and controllable silicon S3 and controllable silicon S4 form series, and two series are in parallel; The anode of controllable silicon S1 and controllable silicon S3 joins; As the high voltage input, the negative electrode of controllable silicon S2 and controllable silicon S4 joins, as the low-voltage output.The tie point of the tie point of controllable silicon S1 and controllable silicon S2 and controllable silicon S3 and controllable silicon S4 connects to single-phase electrical network or AC load respectively as the single phase alternating current (A.C.) output.The drive signal of controllable silicon S1 and controllable silicon S4 is one group, and the drive signal of controllable silicon S2 and controllable silicon S3 is one group, and ON time respectively accounts for power frequency period half.
Said inverter can work in two kinds of patterns: unity power factor pattern and reactive power are regulated pattern.
As shown in Figure 6, during unity power factor, voltage and sense of current are pressed in low frequency switch Q3 conducting, can each power frequency period be divided into 2 stages: first quartile, output voltage are greater than zero, and output current is greater than zero; Third quadrant, output voltage are less than zero, and output current is less than zero.Provided power switch pipe Q1 in each quadrant among Fig. 6, the drive signal of power frequency period phase changer S1 ~ S4.Below in conjunction with legend each stage is further specified.
1. first quartile, output voltage are greater than zero, and output current is greater than zero.
Output current is greater than zero, S1, S4 conducting, and switching tube Q1 exports signal controlling by SPWM, and drive signal generation pattern is seen Fig. 4.
When the Q1 conducting, isoboles is seen Fig. 8, and DC source outwards transmits energy through inductance L 1; The conduction voltage drop of ignoring device, inductance voltage UL=Ubus – Uout is greater than zero, so inductive current increases gradually; Inductive energy storage increases gradually, and current circuit is shown in arrow among the figure.
When Q1 turn-offed, isoboles was seen Fig. 9, and inductance continues outwards to transmit energy.The conduction voltage drop of ignoring device, inductance voltage UL=-Uout is less than zero, so inductive current progressively reduces, the energy of storage progressively reduces, and current circuit is shown in arrow among the figure.
2. third quadrant, output voltage are less than zero, and output current is less than zero.
Output current is less than zero, S2, S3 conducting, and switching tube Q1 exports signal controlling by SPWM, and drive signal generation pattern is seen Fig. 4.
When the Q1 conducting, isoboles is seen Figure 10, and DC source outwards transmits energy through inductance L 1.The conduction voltage drop of ignoring device, inductance voltage UL=Ubus+Uout is greater than zero, so inductive current increases gradually, inductive energy storage increases gradually, current circuit is shown in arrow among the figure.
When Q1 turn-offed, isoboles was seen Figure 11, and inductance continues outwards to transmit energy.The conduction voltage drop of ignoring device, inductance voltage UL=Uout is less than zero, so inductive current progressively reduces, the energy of storage progressively reduces, current circuit is shown in arrow among the figure.
As shown in Figure 7, under the reactive power adjusting pattern, low frequency switch Q3 turn-offs, and presses voltage and sense of current, can each power frequency period be divided into 4 stages: first quartile, output voltage are greater than zero, and output current is greater than zero; Second quadrant, output voltage are less than zero, and output current is greater than zero; Third quadrant, output voltage are less than zero, and output current is less than zero; Four-quadrant, output voltage are greater than zero, and output current is less than zero.Power switch pipe Q1, Q2 in each quadrant have been provided among Fig. 5, the drive signal of controllable silicon S1 ~ S4.Below in conjunction with legend each stage is further specified.
1. first quartile, output voltage are greater than zero, and output current is greater than zero.
Output current is greater than zero, S1, S4 conducting, and switching tube Q1, Q2 export signal controlling by SPWM, and drive signal generation pattern is seen Fig. 5.
When Q1, Q2 conducting, isoboles is seen Figure 13, and DC source outwards transmits energy through inductance L 1; The conduction voltage drop of ignoring device, inductance voltage UL=Ubus – Uout is greater than zero, so inductive current increases gradually; Inductive energy storage increases gradually, and current circuit is shown in arrow among the figure.
As Q1, when Q2 turn-offs, isoboles is seen Figure 12, and inductance continues outwards to transmit energy.The conduction voltage drop of ignoring device, inductance voltage UL=-Ubus – Uout is less than zero, so inductive current progressively reduces, the energy of storage progressively reduces, and current circuit is shown in arrow among the figure.
2. second quadrant, output voltage are less than zero, and output current is greater than zero.
Output current is greater than zero, S1, S4 conducting, and switching tube Q1 and Q2 export signal controlling by SPWM, and drive signal generation pattern is seen Fig. 5.
When Q1, Q2 conducting simultaneously, isoboles is seen Figure 14, and DC source outwards transmits energy through inductance L 1.The conduction voltage drop of ignoring device, inductance voltage UL=Ubus – Uout is greater than zero, so inductive current increases gradually, inductive energy storage increases gradually, current circuit is shown in arrow among the figure.
When Q1, Q2 turn-offed simultaneously, isoboles was seen Figure 15, and inductance continues outwards to transmit energy.The conduction voltage drop of ignoring device, inductance voltage UL=-Ubus-Uout is less than zero, so inductive current progressively reduces, the energy of storage progressively reduces, and current circuit is shown in arrow among the figure.
3. third quadrant, output voltage are less than zero, and output current is less than zero.
Output current is less than zero, S2, S3 conducting, and Q2 is in conducting state all the time, and switching tube Q1 exports signal controlling by SPWM, and drive signal generation pattern is seen Fig. 5.
When Q1, Q2 conducting simultaneously, isoboles is seen Figure 16, and DC source outwards transmits energy through inductance L 1.The conduction voltage drop of ignoring device, inductance voltage UL=Ubus+Uout is greater than zero, so inductive current increases gradually, inductive energy storage increases gradually, current circuit is shown in arrow among the figure.
When Q1, Q2 turn-offed simultaneously, isoboles was seen Figure 17, and inductance continues outwards to transmit energy.The conduction voltage drop of ignoring device, inductance voltage UL=-Ubus+Uout is less than zero, so inductive current progressively reduces, the energy of storage progressively reduces, and current circuit is shown in arrow among the figure.
4. four-quadrant, output voltage be greater than zero, and output current is less than zero, S2, S3 conducting, and switching tube Q1 and Q2 export signal controlling by SPWM, and drive signal generation pattern is seen Fig. 5.
When Q1, Q2 conducting simultaneously, isoboles is seen Figure 18, and DC source outwards transmits energy through inductance L 1.The conduction voltage drop of ignoring device, inductance voltage UL=Ubus+Uout is greater than zero, so inductive current increases gradually, inductive energy storage increases gradually, current circuit is shown in arrow among the figure.
When Q1, Q2 turn-offed simultaneously, isoboles was seen Figure 19, and inductance continues outwards to transmit energy.The conduction voltage drop of ignoring device, inductance voltage UL=-Ubus+Uout is less than zero, so inductive current progressively reduces, the energy of storage progressively reduces, and current circuit is shown in arrow among the figure.
Claims (5)
1. an efficient grid-connected inverter circuit is characterized in that comprising enhancement mode buck circuit, controllable silicon commutation circuit, inverter current sample circuit, voltage and current detection circuit, controlled rectifier commutation control circuit and SPWM control circuit.
2. efficient grid-connected inverter circuit according to claim 1; It is characterized in that: described enhancement mode buck circuit comprises power switch Q1, power switch Q2, diode D1, diode D2, inductance L 1; Inductance L 2; Capacitor C 1 and low frequency switch Q3, power switch Q1 drain electrode and dc power anode and diode D2 negative electrode join, and its source electrode joins with inductance L 1 one ends and diode D1 negative electrode; Power switch pipe Q2 drain electrode is connected with an end of diode D2 anode, inductance L 2, and an end of the anode of its source electrode and diode D1, dc power cathode and low frequency switch joins; One end of inductance L 1 joins with the source electrode of Q1, diode D1 negative electrode, and the end of one-way SCR anode and C1 joins in the other end and the commutating circuit; One end of inductance L 2 is connected with the anode of D2 with the Q2 drain electrode, and the other end is connected with controllable silicon negative electrode, capacitor C 1 and the end of low frequency switch Q3; The end of low frequency switch Q3 is connected with the anode of the source electrode of Q2, diode D1 and the negative pole of DC power supply, and the other end is connected with an end of controllable silicon negative electrode, capacitor C 1 and inductance L 2.
3. efficient grid-connected inverter circuit according to claim 1 is characterized in that: described controllable silicon commutation circuit comprises 4 unidirectional controllable silicon S 1 ~ S4, and controllable silicon S1 and controllable silicon S2 form series; Controllable silicon S3 and controllable silicon S4 form series; Two series are in parallel, and the anode of controllable silicon S1 and controllable silicon S3 joins, as the high voltage input; The negative electrode of controllable silicon S2 and controllable silicon S4 joins, as the low-voltage output; The tie point of the tie point of controllable silicon S1 and controllable silicon S2 and controllable silicon S3 and controllable silicon S4 connects to single-phase electrical network or AC load respectively as the single phase alternating current (A.C.) output.
4. efficient grid-connected inverter circuit according to claim 2 is characterized in that: said power switch Q1, power switch Q2 are the HF switch pipe, and selecting device for use is MOSEFT or IGBT; Q3 is the low frequency switch, and selecting device for use is relay, bidirectional triode thyristor, low frequency IGBT or MOSFFT.
5. efficient grid-connected inverter circuit according to claim 3 is characterized in that: said controllable silicon S1 ~ S4 is the low frequency switching tube, and selecting device for use is unidirectional controllable silicon S CR or IGBT.
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| CN 201220015706 CN202524319U (en) | 2012-01-14 | 2012-01-14 | High efficiency grid-connected inverter circuit |
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| CN 201220015706 CN202524319U (en) | 2012-01-14 | 2012-01-14 | High efficiency grid-connected inverter circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403922A (en) * | 2011-12-21 | 2012-04-04 | 牟英峰 | DC/AC grid connected inverter circuit and power factor adjusting method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403922A (en) * | 2011-12-21 | 2012-04-04 | 牟英峰 | DC/AC grid connected inverter circuit and power factor adjusting method |
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Granted publication date: 20121107 Termination date: 20140114 |