CN202523750U - LED wafer-level chip-size packaging structure - Google Patents
LED wafer-level chip-size packaging structure Download PDFInfo
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- CN202523750U CN202523750U CN2011205713327U CN201120571332U CN202523750U CN 202523750 U CN202523750 U CN 202523750U CN 2011205713327 U CN2011205713327 U CN 2011205713327U CN 201120571332 U CN201120571332 U CN 201120571332U CN 202523750 U CN202523750 U CN 202523750U
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Abstract
The utility model relates to an LED wafer-level chip-size packaging structure, which comprises a silicon chip, an LED wafer, a bonding layer, an LED epitaxial layer, an insulation layer, a reflection layer, pads, a phosphor layer and lenses. The structure is characterized in that the silicon chip is equipped with through holes, metals are filled in the through holes to realize vertical electric interconnection, the insulation layer is deposited on the back side of the silicon chip, the front side of the silicon chip is equipped with the pads and the reflection layer, ant the back side of the silicon chip is equipped with electrodes; that the LED epitaxial layer is equipped with an n electrode and a p electrode, wherein the n and the p electrodes are equipped with the bonding layer; and that the LED wafer bonds with the silicon chip with the through holes, the phosphor layer is coated on the LED wafer, and the LED wafer is equipped with a lens array or a silicon rubber protection layer. The structure of the utility model has the advantages that the LED size is reduced; that heat and electricity separation is realized by the structure and the technology of conductive vertical interconnection, thereby improving the heat radiating capability of LED devices; and that the spin coating technology realizes environment-friendly coating and improves consistency of LED packaging.
Description
Technical field
The utility model relates to a kind of semiconductor device, particularly a kind of LED disc grade chip size encapsulating structure.
Background technology
Compare with conventional light source, as the 4th generation light source LED have advantages such as energy-efficient, Gao Liang, longevity, environmental protection, playing the part of more and more important role in fields such as illumination, demonstrations.At present, the LED encapsulation technology demonstrates the development trend of diversification.Traditional encapsulation technology uses lead frame that independent one by one chip is encapsulated, and packaging efficiency is low, consistency of product is poor, and exists hot interface many and cause dispelling the heat bad.And by means of (the Through Silicon Via of the silicon through hole in the IC technology; TSV) technology is carried out system in package to led chip; Be convenient to the integrated of LED device and circuit, can improve the integrated level and the consistency of product of LED encapsulation, improve the performance of device; Reduce device cost simultaneously, in the LED encapsulation field, have great importance and huge market potential.
Summary of the invention
The purpose of the utility model is to the defective that exists in the prior art, and a kind of LED disc grade chip size encapsulating structure is provided.
The utility model comprises: silicon chip, LED disk, bonded layer and LED epitaxial loayer, and insulating barrier, reflector, pad, phosphor powder layer and lens is characterized in that said silicon chip is provided with through hole; The backside deposition of silicon chip has a layer insulating, is filled with metal in the through hole and realizes the vertical electrical interconnection, is provided with pad and reflector in the silicon chip front; The silicon chip back side is provided with electrode; The LED epitaxial loayer is provided with n and p electrode, on n and p electrode, is provided with bonded layer, LED disk and the silicon chip bonding of being with through hole; Apply phosphor powder layer on the LED disk, on the LED disk, be provided with lens arra or silica gel protected layer.
Said silicon chip is 2inch or large scale more, and thickness is at 100-500um.The through hole of silicon chip is a vertical through hole, and it is shaped as circular or square, fills metal in the through hole; Its diameter is that 5um is to 100um; Spacing is perhaps filled metal circular tube or metal side tube at 5-500um, and it is of a size of 5um to 100um; Spacing is at 5-500um, perhaps filled high polymer material in metal tube.
Said insulating barrier is SiO
2Or SiN
x, deposition of adhesion on insulating barrier, the barrier layer, Seed Layer, adhesion layer is Ni, Ti, Ta, and the barrier layer is Ta, and Seed Layer is Cu.The reflector is metal A g, Au, and pad is Au.
Said LED epitaxial loayer exposes n type GaN through the ICP etching technics; Form insulating barrier through depositing operation n type GaN and p type GaN are separated, n electrode and p electrode are two formulas or distributed, deposit electrode structure, pads such as ohmic contact layer through depositing operation, and ohmic contact layer is Cr, Ti, Pt, Ti, Pd etc., pad be Au.
Said bonded layer be arranged on the LED epitaxial loayer or silicon chip on.
Said LED disk surfaces is provided with the phosphor powder layer of forming with fluorescent powder silica gel mixture or fluorescent material glass, and phosphor powder layer is provided with lens arra, lens be shaped as hemisphere or free form surface.
The utility model is divided into single led encapsulating structure through slice process with disk, and its physical dimension can be 0.5mm * 0.5mm, 1mm * 1mm, 2mm * 2mm, 5mm * 5mm, 10mm * 10mm, 20mm * 20mm.
The utility model has the advantages that the size of having dwindled LED after the encapsulation; Can satisfy the harsh occasion of high-power LED encapsulation structure dimensional requirement, realize the LED encapsulation, improve the production efficiency of LED encapsulation through wafer level technology; Realize that through conduction vertical interconnecting structure and technology electric heating separates; Adopt the high silicon chip of thermal conductivity to encapsulate, overcome the bad problem of dispelling the heat, improve the heat-sinking capability of LED device; Through spin coating proceeding, typography has realized that guarantor's type of LED applies, and has improved the consistency of LED encapsulation.The utility model provides that a kind of technology is simple, low cost and high reliability LED disc grade chip size encapsulating structure and process thereof.
Description of drawings
The profile of Fig. 1 the utility model LED disc grade chip size encapsulating structure;
The vertical view of Fig. 2 the utility model LED disc grade chip size encapsulating structure array;
Fig. 3 the utility model LED disc grade chip size encapsulation backplate structure chart;
Fig. 3 a the utility model LED disc grade chip size encapsulation backplate structure chart;
Fig. 4 the utility model LED adopts the profile of planar lens disc grade chip size encapsulating structure;
Fig. 5 the utility model LED adopts the vertical view of planar lens (triangle micro-structural) disc grade chip size encapsulating structure;
Fig. 6 the utility model LED adopts the profile of planar lens (square micro-structural) disc grade chip size encapsulating structure;
The profile of Fig. 7 the utility model LED disc grade chip size encapsulating structure (free-form surface lens);
Fig. 8 the utility model LED wafer bonding layer manufacturing process steps sketch map;
Fig. 9 the utility model LED wafer bonding layer distribution schematic diagram;
Figure 10 the utility model LED wafer bonding layer distribution schematic diagram;
Figure 11 the utility model has the silicon substrate manufacturing process steps sketch map of perpendicular interconnection through hole;
Figure 12 the utility model LED disk size encapsulation wafer bonding technology;
Figure 13 the utility model LED wafer bonding layer (both positive and negative polarity alternative form) manufacturing process steps sketch map;
Figure 14 the utility model LED wafer bonding layer (both positive and negative polarity alternative form) distribution schematic diagram;
Figure 15 the utility model silicon chip (vertical through hole tamps technology) manufacturing process steps sketch map;
Figure 16 the utility model silicon chip (the tiltedly packless technology of through hole) manufacturing process steps sketch map;
Figure 17 the utility model silicon chip (tiltedly through hole tamps technology) manufacturing process steps sketch map;
Figure 18 the utility model silicon chip (vertical through hole is filled out the molecule padded coaming technology of leaping high) manufacturing process steps sketch map;
Figure 19 the utility model silicon chip (tiltedly through hole is filled out the molecule padded coaming technology of leaping high) manufacturing process steps sketch map.
Among the figure: 1 silicon chip, 2 through holes, 3 electro-copperings, 4 pads, 5 bonded layers; 6n type GaN, 7p type GaN, 8 MQWs, 9 insulating barriers; 10 Sapphire Substrate, 11 phosphor powder layers, 12 spherical lenses, 13 planar lenss; 14 triangle micro-structurals, 15 square micro-structurals, 16 free-form surface lens, 17 macromolecule packing materials.
Embodiment
Embodiment one
Further specify the embodiment of the utility model below in conjunction with accompanying drawing:
Make LED wafer bonding layer structure: photoetching development on the LED epitaxial loayer; The electrode pattern that designs is transferred on the LED epitaxial loayer, utilized dry etch process etching GaN, etching depth is the summation of the thickness of n type GaN 7 and MQW 8; Expose figure n type GaN 6; Make insulating barrier at n type GaN 6 and 7 of p type GaN, metallization n type GaN 6 and p type GaN 7, pad 4 comprises metals such as Ni, Ag, Au, ITO.Photoetching, development, making bonded layer 5, manufacture method can comprise deposition, printing, technologies such as plating.Bonded layer 5 materials can comprise: metals such as Sn-Ag, Sn, Ag, Au, Sn-Ag-Cu, Pb-Sn, Au-Sn.As shown in Figure 8.The shape of bonded layer 5 can be for whole two of both positive and negative polarity, and is as shown in Figure 9, also can be for distributed, and shown in figure 10.
Make the silicon chip of band vertical electrode structure: silicon chip 1 be 2inch or large scale more, and thickness is at 100-500um, and photoetching is developed, and etches vertical through hole 2 through DRIE technology at silicon chip 1, and the shape in hole can be a circle or square; Its diameter be 5um to 100um, spacing is at 10-500um.Form insulating barrier through thermal oxidation or pecvd process, insulating barrier is SiO
2Or SiN
x, form adhesion layer, barrier layer, Seed Layer through sputter or depositing operation.The metal of filling interconnecting metal copper or adopting depositing operation to fill tungsten or other high conductivity through electroplating technology forms the vertical conduction interconnection structure.Fill metal and not exclusively fill full through hole 3, form through depositing operation through depositing operation and form adhesion layer, pad 4 and reflector.Adhesion layer can be metal Ni, Ti, and pad 4 can be metal A u, the metal in reflector can be Ag, and is shown in figure 11.And make the silicon substrate back and be used for surface-pasted electrode structure 4, shown in Fig. 3 and Fig. 3 a.
LED disk and silicon chip bonding technology: the silicon chip of making band vertical electrode structure utilizes disk thermocompression bonding technology to accomplish bonding with the LED disk of making bonded layer, and is shown in figure 12.
Utilize spin coating proceeding on sapphire 10, to make phosphor powder layer 11.As shown in Figure 1.
Utilize mould-forming process or free forming technology on 11 layers in fluorescent material, to make lenticule 12.As shown in Figure 1.
Utilize slice process that disk is separately formed LED disc grade chip size package module, like Fig. 1, shown in 2.
Embodiment two
Embodiment two is identical with embodiment one, and different is must be layered as the formation of employing typography by fluorescence on the sapphire, and its processing step is before all technologies.
Embodiment three
Embodiment three is identical with embodiment one, and different is to be that LED disk and silicon chip bonding technology adopt reflux technique to realize.
Embodiment four
Embodiment four is identical with embodiment one, and different is to be that formed lenticule is a planar lens 13, and has made above that and can improve triangle micro-structural 14, the square micro-structural 15 of getting optical efficiency.Its version can be triangle permutation, circular permutation, quadrangle permutation 15, pentagon permutation, hexagon permutation.Its length of side and spacing satisfy certain requirement.Like Fig. 4, Fig. 5, shown in Figure 6.
Embodiment five
Embodiment five is identical with embodiment one, and different is to be that formed lenticule is a free-form surface lens 16, can satisfy concrete illumination occasion to the hot spot distribution requirements.
Embodiment six
Embodiment six is identical with embodiment one; Different is to be that the bonded layer of made connection LED epitaxial loayer n type GaN and p type GaN is a cross-distribution; Like Figure 13, shown in Figure 14,, improve the uniformity of CURRENT DISTRIBUTION to improve the electric current injection efficiency of LED epitaxial loayer MQW.
Embodiment seven
Embodiment seven is identical with embodiment one, and different is that perpendicular interconnection through hole 2 interior fillings that are made have been expired electro-coppering 3, shown in figure 15.
Embodiment eight
Embodiment eight is identical with embodiment one, and different is that the through-hole interconnection 2 that is made is inverted trapezoidal structure, and metal level wherein is electro-coppering 3, and is shown in figure 16.Also can complete filling expire through hole, shown in figure 17.
Embodiment nine
Embodiment nine is identical with embodiment one; Different is is only to fill skim electro-coppering 3 in the through-hole interconnection 2 of vertical or inverted trapezoidal structure of made; The stress that filled high polymer material 17 causes with thermal mismatching between buffering metal level and the silicon in electro-coppering 3 is like Figure 18, shown in Figure 19.
Implement row ten
Embodiment ten is identical with embodiment one; Different is after being that LED epitaxial loayer and band conductive through hole silicon chip 1 are accomplished bonding technology, Sapphire Substrate 10 to be carried out attenuate, and the technology that can adopt comprises the ICP etching; Laser lift-off, mechanical grinding add chemico-mechanical polishing (CMP) technology.
Claims (6)
1. a LED disc grade chip size encapsulating structure comprises: silicon chip, LED disk, bonded layer and LED epitaxial loayer, insulating barrier, reflector, pad, phosphor powder layer and lens; It is characterized in that said silicon chip is provided with through hole, the backside deposition of silicon chip has a layer insulating, is filled with metal in the through hole and realizes the vertical electrical interconnection; Be provided with pad and reflector in the silicon chip front, the silicon chip back side is provided with electrode, and the LED epitaxial loayer is provided with n and p electrode; On n and p electrode, be provided with bonded layer; LED disk and the silicon chip bonding that is provided with through hole are coated with phosphor powder layer on the LED disk, on the LED disk, are provided with lens arra or silica gel protected layer.
2. LED disc grade chip size encapsulating structure according to claim 1 is characterized in that said silicon chip is 2inch or large scale more, and thickness is at 100-500um.
3. LED disc grade chip size encapsulating structure according to claim 1, the through hole that it is characterized in that said silicon chip is a vertical through hole, it is shaped as circular or square; Fill metal in the through hole, its diameter be 5um to 100um, spacing is at 5-500um; Perhaps fill metal circular tube or metal side tube; It is of a size of 5um to 100um, and spacing is at 5-500um, perhaps filled high polymer material in metal tube.
4. LED disc grade chip size encapsulating structure according to claim 1 is characterized in that depositing adhesion layer on the said insulating barrier barrier layer, Seed Layer.
5. LED disc grade chip size encapsulating structure according to claim 1 is characterized in that said LED epitaxial loayer through the ICP etching technics, exposes n type GaN; Form insulating barrier through depositing operation n type GaN and p type GaN are separated, n electrode and p electrode are two formulas or distributed, the ohmic contact layer in the depositing operation depositing electrode, pad.
6. LED disc grade chip size encapsulating structure according to claim 1 is characterized in that said bonded layer selection is arranged on LED epitaxial loayer or the silicon chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205713327U CN202523750U (en) | 2011-12-31 | 2011-12-31 | LED wafer-level chip-size packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205713327U CN202523750U (en) | 2011-12-31 | 2011-12-31 | LED wafer-level chip-size packaging structure |
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| CN202523750U true CN202523750U (en) | 2012-11-07 |
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| CN2011205713327U Expired - Lifetime CN202523750U (en) | 2011-12-31 | 2011-12-31 | LED wafer-level chip-size packaging structure |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187508A (en) * | 2011-12-31 | 2013-07-03 | 刘胜 | Size encapsulation structure and encapsulation technology of light-emitting diode (LED) wafer level chip |
| CN103700738A (en) * | 2013-12-29 | 2014-04-02 | 哈尔滨固泰电子有限责任公司 | LED (Light-Emitting Diode) packaging method and LED device on basis of special substrate |
| CN103762283A (en) * | 2013-12-24 | 2014-04-30 | 大连德豪光电科技有限公司 | LED flip chip |
| CN104909331A (en) * | 2014-03-12 | 2015-09-16 | 中芯国际集成电路制造(北京)有限公司 | Wafer selective-bonding method |
| JP2016178307A (en) * | 2015-03-20 | 2016-10-06 | コミサリア ア エナジー アトミック エ オックス エナジーズ オルタネティヴ | Photoelectric device having light emission diode |
| CN112928194A (en) * | 2021-01-25 | 2021-06-08 | 上海大学 | Bonding method of flip Micro LED chip and substrate |
| CN113345812A (en) * | 2021-06-03 | 2021-09-03 | 广东新锐流铭光电有限公司 | Packaging process of LED wafer-level chip-free substrate |
-
2011
- 2011-12-31 CN CN2011205713327U patent/CN202523750U/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187508A (en) * | 2011-12-31 | 2013-07-03 | 刘胜 | Size encapsulation structure and encapsulation technology of light-emitting diode (LED) wafer level chip |
| CN103187508B (en) * | 2011-12-31 | 2015-11-18 | 刘胜 | LED Wafer-level Chip Scale Package structure and packaging technology |
| CN103762283A (en) * | 2013-12-24 | 2014-04-30 | 大连德豪光电科技有限公司 | LED flip chip |
| CN103700738A (en) * | 2013-12-29 | 2014-04-02 | 哈尔滨固泰电子有限责任公司 | LED (Light-Emitting Diode) packaging method and LED device on basis of special substrate |
| CN104909331A (en) * | 2014-03-12 | 2015-09-16 | 中芯国际集成电路制造(北京)有限公司 | Wafer selective-bonding method |
| CN104909331B (en) * | 2014-03-12 | 2016-08-17 | 中芯国际集成电路制造(北京)有限公司 | A kind of wafer selectivity bonding method |
| JP2016178307A (en) * | 2015-03-20 | 2016-10-06 | コミサリア ア エナジー アトミック エ オックス エナジーズ オルタネティヴ | Photoelectric device having light emission diode |
| CN112928194A (en) * | 2021-01-25 | 2021-06-08 | 上海大学 | Bonding method of flip Micro LED chip and substrate |
| CN112928194B (en) * | 2021-01-25 | 2022-07-15 | 上海大学 | Bonding method of flip Micro LED chip and substrate |
| CN113345812A (en) * | 2021-06-03 | 2021-09-03 | 广东新锐流铭光电有限公司 | Packaging process of LED wafer-level chip-free substrate |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121107 |