CN202488870U - Circuit substrate structure - Google Patents
Circuit substrate structure Download PDFInfo
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- CN202488870U CN202488870U CN2012200243461U CN201220024346U CN202488870U CN 202488870 U CN202488870 U CN 202488870U CN 2012200243461 U CN2012200243461 U CN 2012200243461U CN 201220024346 U CN201220024346 U CN 201220024346U CN 202488870 U CN202488870 U CN 202488870U
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Abstract
The utility model discloses a circuit substrate structure. The circuit substrate structure comprises a carrier, one or more adhering promoting units and a metal layer, wherein the adhering promoting units form a rough surface on the surface of the carrier, and the rough surface formed by the adhering promoting units is in an open-ended state, the metal layer is arranged on the adhering promoting units and is formed by the reaction between a catalyst preinstalled on the adhering promoting units and an electroless plating solution. The circuit substrate structure can effectively reduce uses of catalysts or contact agents and significantly reduce use cost of the catalysts and the contact agents.
Description
Technical field
The utility model relates to a kind of board structure, particularly a kind of circuit substrate structure at non-conductive carrier.
Background technology
Variation based on present 3C Product makes popular more exquisite for the convenience and the portability of 3C Product; Order about electronic product and develop, impelled IC design and circuit design thereof to develop simultaneously towards the direction of three-dimensional 3D design towards the direction of microminiaturization, lightweight and multifunction.Three-dimensional through the circuit unit design can form complicated circuitry on the circuit unit of limited bulk, let electronic product not influencing under its function, can dwindle the outward appearance volume, makes its microminiaturization and lightweight more.In other words, the design of the circuit unit of three-dimensional impels electronic product under small volume; Also can possess complicated circuitry; Therefore the three-dimensional of circuit unit design has really and lets the multiple potentiality of electronic product microminiaturization, lightweight and multifunction, has the high product competitiveness; And can be applied in widely on the various aspects, like electronic products such as mobile phone, automobile circuit, ATM and hearing aidss.
At present; Be used for making the multiple mode of stereo circuit assembly; One of them is molded interconnecting assembly-laser straight forming method (MID-LDS, Molded Interconnect device-Laser Direct Structuring), and this mode is that the non-conductive plastics that contain catalyst are formed assembly carrier via ejection formation; Again with the catalyst on the laser laser activation carrier; Make catalyst change catalyst nuclear into, carry out electroless plating reaction through catalyst nuclear and preplating metal ion, and form the metallic conduction circuit.
Conducting wire structure Design in the above-mentioned stereo circuit manufacturing process often is made up of mutual disjunct a plurality of circuit; Form the metal solvent that part surface adhered to of conducting wire pattern through desire on the circuit unit; The preplating metal ion that exists in the chemical plating fluid is carried out a catalytic reaction form the part surface of circuit patterns, so chemical plating has the advantage that does not have the uneven influence of electric force lines distribution and also can obtain the uniform coating of thickness to the plating piece of complex geometry compared to plating the preplating metal ion is reduced on circuit unit desire.The method of prior art use at present adopts the chemical plating mode to make the conducting wire of stereo circuit assembly more.
Chemical plating is under the situation that does not apply electric power; Form the metal solvent that part surface adhered to of circuit patterns through desire on the circuit unit; Preplating metal ion to existing in the chemical plating fluid carries out a catalytic reaction, forms the part surface of circuit patterns the preplating metal ion is reduced on circuit unit desire.Therefore, electroless plating method can form thickness even metal coating by the part surface of desire formation circuit patterns on circuit unit.
By above-mentioned visible; At present the conducting wire structure in the stereo circuit manufacturing process its objective is and makes made electronic product microminiaturization, lightweight and multifunction and reach the high product competitiveness more; Has vast application potential on 3C electronic product field; Yet it still has following restriction and shortcoming:
1. the manufacture method of existing stereo circuit assembly; Though can efficiently produce the conducting wire structure in the stereo circuit manufacturing process, need be added in a large amount of catalyst to the non-conductive plastics, again the ejection formation carrier; In molded interconnecting assembly-laser straight forming method (MID-LDS) manufacturing process; The catalyst of participating in reaction but because need to add a certain proportion of catalyst in non-conductive plastics, therefore need expend higher catalyst cost also only at superficial layer.
2. as stated; Because of needing to add in a large amount of catalyst to the non-conductive plastics in the MID-LDS manufacturing process; Ejection formation forms carrier again; Because catalyst is evenly distributed in the carrier, the metal core on surface needs the reductant concentration of higher dosage in subsequent chemistry plating process after laser divests, and just can make metal core open plating smoothly.Relatively, the chemical copper plating bath need expend more chemical plating fluid chemical reduction reaction is carried out on the integral carrier surface than unstability, on circuit unit, forms the conducting wire of needed stereo circuit, yet but expends higher chemical plating fluid cost.
Therefore, the manufacturing technology of existing stereo circuit still is subject to the great number production cost, still lacks a kind of conducting wire structure and preparation method thereof at present and is applied in the field, 3C electronic product field.
The utility model content
For solving the problem that exists in the above-mentioned prior art, the purpose of the utility model is to provide a kind of circuit substrate structure, need expend higher problems such as production cost to solve in the existing stereo circuit manufacturing process.
The purpose of the utility model; A kind of circuit substrate structure is provided; It comprises a carrier, at least one promotion portion of adhering to, and wherein respectively adhere to promotion portion and utilize the roughened mode to form rough surface at carrier surface, and the rough surface that respectively adheres to promotion portion presents open state; And one metal level being set respectively adhering to promotion portion, this metal level is formed by defaulting in the catalyst and the chemical plating fluid reaction of respectively adhering to promotion portion.
Preferably; Above-mentioned circuit substrate structure further comprises at least one conductive junction point; Each conductive junction point also is arranged on the carrier with the roughened method, and is arranged at and respectively adheres to outside the promotion portion, through the edge of each conductive junction point connection carrier with respectively adhere to promotion portion and form the circuit that communicates.
Above-mentioned circuit substrate structure further comprises electrodeposited coating; One anti-plating insulating barrier is set on each conductive junction point again; Utilize the energising plating mode electrodeposited coating to be set respectively adhering in the promotion portion; To increase the metal layer thickness on each circuit pattern, remove anti-plating insulating barrier and metal level on each conductive junction point at last, obtain independently circuit pattern.
Another purpose of the utility model provides a kind of circuit substrate structure, and it comprises a carrier, a catalyst insulating barrier, an at least one promotion portion and metal level of adhering to; Wherein respectively adhering to promotion portion utilizes the roughened mode to run through the catalyst insulating barrier and is arranged at carrier surface and forms rough surface; And the rough surface that respectively adheres to promotion portion is open state; And one metal level being set respectively adhering to promotion portion, this metal level is formed by defaulting in the catalyst and the chemical plating fluid reaction of respectively adhering to promotion portion.
Above-mentioned circuit substrate structure further comprises at least one conductive junction point and electrodeposited coating; Each conductive junction point also runs through the catalyst insulating barrier with the roughened method and is arranged at carrier surface and is arranged at and adheres to outside the promotion portion; Edge through each conductive junction point connection carrier with adhere to promotion portion and form the circuit that communicates, through each conductive junction point in order to the edge of connection carrier with adhere to promotion portion and carry out chemical plating and form metal level, an anti-plating insulating barrier is set on the metal level of each conductive junction point; It is in order to insulate each conductive junction point; Prevent to electroplate precipitating metal, utilize the energising plating mode to form electrodeposited coating, in order to increase metal layer thickness; At last anti-plating insulating barrier on each conductive junction point and metal level are removed, obtained independently circuit pattern.
In sum, circuit substrate structure that the utility model provided and preparation method thereof has advantage:
(1) in the existing stereo circuit manufacturing process, because of in high molecule plastic, being added into a large amount of catalyst or catalyst and chemical plating fluid, having the higher production cost problem that expends.Because of the non-conductive carrier of the utility model not containing metal oxide or catalyst; After forming the compartmentalization rough surface with laser irradiation etching; Catalyst can only be attached to the zone of carrier surface, effectively is reduced to the employed catalyst of high molecule plastic in the circuit production process.
(2) existing LDS laser laser activation metal oxide or catalyst produce the method for metal core; Reductant concentration for the reaction needed higher dosage of electroless copper just can make metal core open plating smoothly; The plating bath of chemical copper is shorter than instability and life-span relatively; The administrative expenses of plating bath increase, and need higher production cost.The utility model forms coarse facies posterior hepatis with laser irradiation etching mode; It can effectively adsorb catalyst, in order to the formation of subsequent metal layer, and the use of minimizing catalyst or catalyst; Have advantage, significantly reduce the use cost of catalyst and catalyst and chemical plating fluid than low production cost.
Description of drawings
Fig. 1 is the circuit substrate structure step of manufacturing flow chart of the utility model first embodiment;
Fig. 2 is the structural representation of the circuit substrate structure of the utility model first embodiment;
Fig. 3 is the circuit substrate structure step of manufacturing flow chart of the utility model second embodiment;
Fig. 4-5 is the structural representation of the circuit substrate structure of the utility model second embodiment;
Fig. 6 is the circuit substrate structure step of manufacturing flow chart of the utility model the 3rd embodiment;
Fig. 7 is the structural representation of the circuit substrate structure of the utility model the 3rd embodiment;
Fig. 8-9 is the structural representation of the circuit substrate structure of the utility model the 4th embodiment;
Figure 10 is the structural representation of the circuit substrate structure of the utility model the 5th embodiment;
Figure 11 is the structural representation of the circuit substrate structure of the utility model the 6th embodiment;
Figure 12 is the structural representation of the circuit substrate structure of the utility model the 7th embodiment;
Figure 13-14 is the structural representation of the circuit substrate structure of the utility model the 8th embodiment;
Figure 15-16 is the structural representation of the circuit substrate structure of the utility model the 9th embodiment.
In conjunction with the accompanying drawing following Reference numeral of mark above that:
The 1-circuit substrate structure; The 11-carrier; The 111-conductive junction point; The 1111-Heat Conduction Material; 12-adheres to promotion portion; The 121-rough surface; The 13-metal level; The anti-plating of 141-insulating barrier; 14-catalyst insulating barrier; The 15-electrodeposited coating; The 16-heat carrier;
S1-S4: process step; S1a-S7a: process step; Sa1-Sa5: process step.
Embodiment
For ease of technical characterictic, content and the advantage of understanding the utility model and the effect that can reach thereof; Existing with the utility model conjunction with figs.; And specify as follows with the expression-form of embodiment, and wherein employed accompanying drawing, its purport is merely to be illustrated and the aid illustration book; May not be true ratio after the utility model enforcement and precisely configuration, so should not understand, limit to the interest field of the utility model on reality is implemented with regard to the ratio and the configuration relation of appended accompanying drawing.Be can detail knowledge the utility model technical characterictic and practical effect, and can implement according to the content of specification, existing further through following examples, specify as after.
The utility model proposes a kind of circuit substrate structure and preparation method thereof.See also Fig. 1, it is the first embodiment sketch map of the flow chart of steps of the utility model circuit substrate structure manufacture method.
As shown in Figure 1, the manufacture method key step of the utility model circuit substrate structure comprises:
Step S1 at first provides a carrier.Carrier can be non-conductive carrier.
Step S2 forms the promotion portion of adhering to rough surface at carrier surface with the roughened method.
Step S3 is provided with a catalyst in adhering to promotion portion.Above-mentioned catalyst generation type is that carrier is immersed in the catalyst solution tank, makes catalyst attached to adhering to promotion portion.
Step S4 carries out chemical plating metalization at last to form metal level on the catalyst of carrier surface.
In the promotion portion of adhering to of step S2, the result appears by the electron microscope photography, and it presents irregular rough form.(Scanning Electron Microscopy, be called for short: SEM) detecting obtains the promotion portion of adhering to of the carrier surface after roughened, the about 10-20 μ of its pore size m with sweep electron microscope.
With the carrier surface clean, remove the materials such as grease and dirty dirt on the carrier surface at step S3; Present embodiment adopts carrier is dipped in the good cleaning agent (cleaning agent can contain interfacial agent) of dilution, makes its carrier surface clean in order to oil removing, and the character that will adhere to the rough surface of promotion portion converts hydrophily into by hydrophobicity, cleans carrier with pure water again.
Further, catch the globule by electron microscope and drip the image that is attached on the carrier surface.Without the carrier surface after the roughened globule is dripped and to be attached to carrier surface, the globule does not appear and adheres to and adsorption phenomena, so be drops.The promotion portion of adhering to of the carrier surface after roughened; The globule appears and adheres to and diffusion phenomena; So adhering to promotion portion transfers hydrophily to by hydrophobicity, represent that more catalyst is adsorbable and can plate reaction in order to subsequent chemistry more securely attached to adhering to promotion portion.
The catalyst that is adopted at step S3 can be used titanium, antimony, silver, palladium, iron, nickel, copper, vanadium, cobalt, zinc, platinum, iridium, osmium, rhodium, rhenium, ruthenium, tin one of them or its mixture, also can comprise the compound of above-mentioned element.For example: palladium bichloride (PdCl
2), stannic chloride (SnCl
2), palladium sulfate (II) hydrate (Palladium Sulfate Hydrate) etc., but not as limit.
Step S4 can adopt copper or nickel carrying out on the chemical plating one deck metal level at least on the catalyst of carrier surface with chemical reduction reaction; Also can carry out the initial conducting film before the electroplating processes, for the general electric galvanizing process of back copper, nickel, chromium as non-conductive carrier.In the utility model, metal level can be any metal or alloy with good electrical conductive properties, and present embodiment adopts copper and catalyst reaction to form metal level, but does not exceed with this example.The manufacture method of the circuit substrate structure of above-mentioned steps S1-S4 can be adaptable across the solid or the planar circuit manufacturing process of non-conductive carrier.
Please with reference to shown in Figure 2, it is the circuit substrate structure of the first made embodiment of the above-mentioned step S1-S4 that utilizes Fig. 1.As shown in the figure; The circuit substrate structure 1 of the utility model is applicable in the line construction; Circuit substrate structure 1 comprises carrier 11 and at least one promotion portion 12 of adhering to; Wherein respectively adhere to promotion portion 12 and form rough surface 121 with roughened method (present embodiment adopts laser irradiation etching mode) in carrier 11 surfaces, the rough surface 121 that respectively adheres to promotion portion 12 is open state.Afterwards, carrier 11 is immersed in the catalyst solution tank, make catalyst attached to adhering to promotion portion 12.At last, on the catalyst on carrier 11 surfaces, carry out chemical plating metalization to form metal level 13, metal level 13 comprises at least one circuit pattern.
In the utility model, metal level also can carry out the initial conducting film before the electroplating processes as non-conductive carrier, for more understanding the technological means that this case further is applied in electroplating processes, therefore specially is illustrated in the handling process of the enterprising electroplating of metal level in this.See also shown in Figure 3ly, the utility model is applied to the second embodiment sketch map of the flow chart of steps of electroplating processes, and is as follows:
Step S1a at first provides a carrier, and carrier can be non-conductive carrier.
Step S2a, what form circuit pattern with rough surface with the roughened method in carrier surface adheres to promotion portion and conductive junction point.
Step S3a is provided with a catalyst in adhering to promotion portion.The mode that above-mentioned catalyst forms is that carrier is immersed in the catalyst solution tank, makes catalyst attached to adhering to promotion portion.
Step S4a carries out chemical plating metalization to form metal level on the catalyst of carrier surface.
Step S5a imposes anti-plating insulating barrier again on conductive junction point.
Step S6a, electroplating processes capable of using is provided with electrodeposited coating on metal level.
Step S7a removes anti-plating insulating barrier on the conductive junction point and metal level at last, forms each independently circuit pattern.
Please with reference to Fig. 4 and shown in Figure 5, it is the above-mentioned made circuit substrate structure of step S1a-S7a that utilizes Fig. 3.As shown in Figure 4; The circuit substrate structure 1 of the utility model is applicable in the line construction; Circuit substrate structure 1 comprises carrier 11 and at least one promotion portion 12 of adhering to; Wherein respectively adhering to promotion portion 12 is arranged at carrier 11 surfaces with roughened method (present embodiment adopt laser irradiation etching mode) and respectively adheres to the rough surface 121 of promotion portion 12 to form; The rough surface 121 that respectively adheres to promotion portion 12 is open state; Conductive junction point 111 is also further set up in carrier 11 in carrier 11 surfaces, and each conductive junction point 111 is connected in the edge of carrier 11 and respectively adheres to promotion portion 12, through each conductive junction point 111 in order to the edge of connection carrier 11 with respectively adhere to promotion portion 12 and carry out chemical plating and form metal level 13.As shown in Figure 5; On each conductive junction point 111, impose an anti-plating insulating barrier 141 again; Metal level 13 thickness that utilize the increase of energising plating mode to adhere to promotion portion 12 form an electrodeposited coating 15; Remove anti-plating insulating barrier 141 and metal level 13 on each conductive junction point 111 at last, form the circuit pattern of each independence.
In the middle of the electroplating process; Can through electroplate energising produce have conducting property metal level 13 in electroplating process as negative pole; And let the positive pole of power supply and preplating metal solid join; When carrier 11 assemblies were soaked in the electroplate liquid that contains the preplating metal ion, the preplating metal ion just received electronics on as the metal level 13 of negative pole and reduces and separate out the preplating metal in metal level 13, forms desired metallic circuit.Wherein, electroplated metal can be copper, nickel, chromium, tin, silver or gold or its alloying metal in advance.
Because carrier surface does not have the part of active catalytic layer, when carrying out chemical plating, possibly be prone to produce reaction because of its material property with catalyst, chemical plating fluid.See also the steps flow chart of the 3rd embodiment circuit substrate structure manufacture method of the utility model, see also Fig. 6, as follows:
Step Sa1 at first provides a carrier, and carrier can be non-conductive carrier.
Step Sa2 is provided with the catalyst insulating barrier at carrier surface.
Step Sa3 runs through the catalyst insulating barrier with the roughened method and is arranged at carrier surface and forms at carrier and respectively adheres to promotion portion.
Step Sa4 is provided with catalyst in adhering to promotion portion.The mode that above-mentioned catalyst forms is that carrier is immersed in the catalyst solution tank, makes catalyst attached to adhering to promotion portion.
Step Sa5 carries out chemical plating metalization at last to form metal level on the catalyst of carrier surface.
In brief, the circuit substrate structure of the utility model the 3rd embodiment and first embodiment are identical, both differences be in, on carrier 11 surfaces catalyst insulating barrier 14 (as shown in Figure 7) is set before the step S2.
In addition; Please with reference to Fig. 8 and shown in Figure 9, the steps flow chart of the circuit substrate structure manufacture method of the 4th embodiment of the utility model and second embodiment are identical, both difference be in; On carrier 11 surfaces catalyst insulating barrier 14 is set before the step S2a; And run through catalyst insulating barrier 14 in carrier with the roughened method, and be arranged at carrier surface and form and respectively adhere to promotion portion, subsequent step is identical with S2a-S7a.
Wherein, catalyst insulating barrier 14 can use photoresist, printing ink or coating to process with modes such as printing, ink-jets, maybe can stick insulating tape or dry film photoresist as catalyst insulating barrier 14, and catalyst insulating barrier 14 can be selected to remove or do not remove.
Among above-mentioned all embodiment, adopt carrier is immersed in the catalyst solution tank, catalyst solution main component can be palladium bichloride, stannic chloride and hydrogen chloride (PdCl
2+ SnCl
2+ HCl), can form the very thin and catalyst of tool catalytic action of one deck adhering to promotion portion like this.Because the tin ion of the material surface of carrier becomes stannic hydroxide Sn (OH)
4, because of its no catalytic effect, and stannic hydroxide can form the catalytic effect that colloid weakens palladium (Pd) metallic.Divest this " tin shell " and handle, make palladium (Pd) that the surface reduction of carrier goes out metallic state with catalyst as the subsequent chemistry plating.Said process is referred to as speedization (Accelerator).
Further, for increasing the hot transfer efficiency of whole circuit substrate structure, can bury a heating column underground in carrier.Please with reference to shown in Figure 10; It is the steps flow chart of the circuit substrate structure manufacture method of the utility model the 5th embodiment; Its steps flow chart and first embodiment are identical, both differences be in, bury a heating column 16 underground in carrier 11 before the step S2; In step S2, around carrier 11 surperficial corresponding heating column 16 positions and heating column 16, form the promotion portion 12 of adhering to the roughened method with rough surface 121.The said heating column of burying underground can be accordinged to the producer designs product demand in carrier, and the high thermal source place that is chosen in the carrier buries at least one heating column 16 underground to increase the hot transfer efficiency of whole circuit substrate structure.
Further; The heating column material can be lead, aluminium, gold, copper, tungsten, magnesium, molybdenum, zinc, silver, graphite, Graphene, diamond, CNT, nano carbon microsphere, nanometer foam, carbon 60, carbon nanocone, carbon nanohorn, carbon nanometer dropper, tree-shaped carbon micrometer structure, beryllium oxide, aluminium oxide, zirconia, boron nitride, aluminium nitride, magnesia, silicon nitride or carborundum one of them or its combination, but not as limit.
Please with reference to shown in Figure 11, it is the sketch map of the circuit substrate structure of the utility model the 6th embodiment.Identical with the purpose of above-mentioned the 5th embodiment, be all the hot transfer efficiency that increases whole circuit substrate structure, can add Heat Conduction Material in carrier.The structure of the 6th embodiment and first embodiment (Fig. 2) are identical; Both differences be in; Step S1 carrier 11 steps are provided the time; In the middle of added Heat Conduction Material 1111, and evenly be mixed in the carrier 11, form the promotion portion 12 of adhering to the roughened method equally afterwards with rough surface 121.Subsequent step is all identical with first embodiment.
Please with reference to shown in Figure 12, it is the circuit substrate structure sketch map of the utility model the 7th embodiment, and its structure and the 3rd embodiment are identical; Both differences be in; Step 1 the step of carrier 11 is provided the time, centrally added Heat Conduction Material 1111 and evenly be mixed in the carrier 11, before step S2, catalyst insulating barrier 14 is set earlier afterwards in carrier 11 surfaces; With isolated carrier 11 surfaces, avoid carrier 11 surfaces to be prone to produce reaction with catalyst, chemical plating fluid because of its material property.
Please with reference to shown in Figure 13-14, it is the circuit substrate structure sketch map of the utility model the 8th embodiment, and it is the distortion appearance attitude (Fig. 4-5) of second embodiment; Both differences be in; Step S 1 the step of carrier 11 is provided the time, add Heat Conduction Material 1111, and evenly be mixed in the carrier 11.Subsequent step is all identical with second embodiment.
Please with reference to shown in Figure 15-16; It is the circuit substrate structure sketch map of the utility model the 9th embodiment; It is the distortion appearance attitude (Fig. 8-9) of the 4th embodiment, both differences be in, when the step of carrier 11 is provided; The central Heat Conduction Material 1111 that adds also evenly is mixed in the carrier 11, and subsequent step is all identical with the 4th embodiment.
In sum; The 6th, seven, eight, nine embodiment of the utility model; All in carrier 11, add Heat Conduction Material 1111, its required addition and kind can be done the appropriateness adjustment according to the producer designs product demand, and purpose is for increasing the hot transfer efficiency of whole circuit substrate structure.
The material of the non-conductive carrier that adopts in the utility model can be high molecule plastic or ceramic material.High molecule plastic can be thermoplastics or thermoset plastics.The material of the non-conductive carrier that adopts has heat conduction property; And can add inorganic filler in the high molecule plastic of non-conductive carrier, wherein the composition of inorganic filler can be silicic acid, silica derivative, carbonic acid, carbonic acid derivative, phosphoric acid, phosphoric acid derivatives, activated carbon, porous carbon, carbon black, glass fiber, carbon fiber or ore deposit fiber one of them or its combination.In addition, ceramic material can be oxide, nitride, carbide, boride one of them.Further, ceramic material by oxide, nitride, carbide, boride one of them combine adhesive to form can to penetrate, the mixture of extrusion etc., and after mixture is shaped, remove adhesive thermal sintering again.
The roughened method that is adopted in the utility model can adopt modes such as sandblast processing mode or laser irradiation etching that its carrier surface is provided with and form the promotion portion of adhering to roughening; The laser illumination wavelength scope that adopts can be between being between 248 nanometer to 10600 nanometers, and wherein laser irradiation etching mode can be carbon dioxide (CO
2) laser, the refined chromium of rubidium (Nd:YAG) laser, Nd-doped yttrium vanadate crystal (Nd:YVO
4) laser, quasi-molecule (EXCIMER) laser or optical fiber laser (Fiber Laser), but not as limit.
In the utility model, non-conductive carrier disperses interpolation to have heat conductivity material or derivatives thereof material; The material with heat conduction property that is adopted can be metal heat-conducting material or nonmetal heat conduction material; The metal heat-conducting material that adopts can be lead, aluminium, gold, copper, tungsten, magnesium, molybdenum, zinc or silver one of them or its combination; The nonmetal heat conduction material that adopts can be graphite, Graphene, diamond, CNT, nano carbon microsphere, nanometer foam, carbon 60, carbon nanocone, carbon nanohorn, carbon nanometer dropper, tree-shaped carbon micrometer structure, beryllium oxide, aluminium oxide, zirconia, boron nitride, aluminium nitride, magnesia, silicon nitride or carborundum one of them or its combination, but not as limit.
The catalyst that present embodiment adopted can adopt titanium, antimony, silver, palladium, iron, nickel, copper, vanadium, cobalt, zinc, platinum, iridium, osmium, rhodium, rhenium, ruthenium, tin one of them or its mixture, also can comprise the compound of above-mentioned element.For example: palladium bichloride (PdCl2), stannic chloride (SnCl2), palladium sulfate (II) hydrate (Palladium Sulfate Hydrate) etc., but not as limit.
According to the manufacturing approach of above-mentioned first to the 9th described circuit substrate structure of embodiment, can be adaptable across various non-conductive carriers, and it can have the material of heat conduction property or have the stereo circuit manufacturing process of the plastic film interconnecting assembly of heat conduction property.
The data that the carrier of the utility model carries out elementary analysis (EDS) back gained show do not mix in the carrier of the utility model any metal oxide or catalyst; Gold (Au) element that the analysis data appear is the gold layer that non-conductive conductor all need plate earlier in the pre-treatment process; It is in order to increase conductivity; Avoid the accumulation of surface electronic, can avoid the electric charge accumulation that resolution is impacted.
Through analyze existing LPKF-LDS technology to carrier (LPKF) surface with laser carved SEM figure, all be doped with the metal oxide composition in the used LPKF carrier on the industry at present; Show in the LPKF carrier in the middle of the data to be doped with metal oxide, show to have chromium (Cr) and copper (Cu) element is present in the LPKF carrier among elementary analysis (EDS) figure.By above-mentioned said; The technical characterictic of the utility model is with the different of prior art; The carrier of the utility model is not because of containing any metal oxide; After formation compartmentalization rough surface was set with roughened mode (laser irradiation etching), catalyst can adhere to and the firm roughened area that invests carrier surface, can effectively be reduced in the employed catalyst amount of high molecule plastic in solid or the planar circuit manufacturing process.Prior art with LDS laser laser activation metal oxide to produce metal core; Because of existing LPKF carrier contains metal oxide; Therefore in the reaction of electroless copper, need the reductant concentration of higher dosage just can make metal core open plating smoothly, the plating bath with relative chemical copper is unstable, the life-span is short, expense plating bath increases and need higher shortcomings such as production cost.
In sum; The circuit substrate structure of the utility model makes its non-conductive carrier form the promotion portion of adhering to through laser irradiation etching, and it can effectively adsorb catalyst and firm being arranged at adhered in the promotion portion; Formation in order to subsequent metal layer; Can effectively reduce the use of catalyst or catalyst, have advantage, can significantly reduce the use cost of catalyst and catalyst amount and chemical plating fluid than low production cost.The method of improving existing laser laser activation metal oxide or catalyst generation metal core expends the problem of higher production cost.
In addition, be, in each embodiment of the utility model, respectively adhere to promotion portion, catalyst, metal level, anti-plating insulating barrier, catalyst insulating barrier, and electrodeposited coating etc., be provided with on one of them single plane on the non-conductive carrier and appear what this need explain.But when the utility model is implemented in reality, be not limited to this, also can be arranged on the promotion portion of respectively adhering to that is provided with on the non-conductive carrier different plane, catalyst, metal level, anti-plating insulating barrier, catalyst insulating barrier, reach electrodeposited coating etc.In other words, circuit substrate structure of the utility model and manufacturing approach thereof can be made the circuit on solid or plane.
Moreover, in each embodiment of the utility model, before each step will be carried out next step; All have cleaning; To avoid last step to pollute the fabrication schedule of next step, therefore the technological means that this technical field is familiar with does not give unnecessary details in the utility model.For example: form the promotion portion of adhering to the roughened method on the non-conductive carrier, at this moment, will have waste material and remain in non-conductive carrier, utilize cleaning that waste material is removed from non-conductive carrier surface with rough surface.But be stressed that wherein non-conductive carrier immerses in the catalyst solution tank, makes catalyst attached to adhering to promotion portion; Through behind the cleaning,, make that catalyst can be attached to adhering to promotion portion owing to adhere to the rough surface of promotion portion; All the other do not have the part of the promotion of adhering to portion non-conductive carrier, then can be because of cleaning, and remove catalyst; Or the residual quantity of catalyst is difficult for and chemical plating produces reaction, or the unlikely line quality to circuit substrate structure of its reaction has too big influence.
The above embodiment is merely the technological thought and the characteristics of explanation the utility model; Its purpose makes those of ordinary skill in the art can understand the content of the utility model and is implementing according to this; When the claim that can not limit the utility model with this; The equalization of promptly doing according to the spirit that the utility model disclosed generally changes or modifies, and must be encompassed in the claim of the utility model.
Claims (8)
1. a circuit substrate structure is characterized in that, comprises:
One carrier;
At least one promotion portion of adhering to, each said promotion portion of adhering to forms rough surface at said carrier surface, and each said rough surface that adheres to promotion portion presents open state; And
One metal level is provided with said metal level in each said promotion portion of adhering to, and said metal level is formed by defaulting in each said catalyst and chemical plating fluid reaction of adhering to promotion portion.
2. circuit substrate structure according to claim 1 is characterized in that, further comprises at least one conductive junction point, and each said conductive junction point connects the edge of this carrier and respectively this adheres to promotion portion and forms the circuit that communicates.
3. circuit substrate structure according to claim 2 is characterized in that, an anti-plating insulating barrier further is set on the metal level of each said conductive junction point.
4. circuit substrate structure according to claim 3 is characterized in that, an electrodeposited coating is set on the said metal level.
5. a circuit substrate structure is characterized in that, comprises:
One carrier;
One catalyst insulating barrier, it is arranged on the said carrier surface;
At least one promotion portion of adhering to, each said promotion portion of adhering to runs through said catalyst insulating barrier and is arranged at said carrier surface, and each said rough surface that adheres to promotion portion is open state; And
One metal level, it is arranged on each said adhering in the promotion portion, and said metal level is formed by defaulting in the catalyst and the chemical plating fluid reaction of respectively adhering to promotion portion.
6. circuit substrate structure according to claim 5 is characterized in that, further comprises at least one conductive junction point, and each said conductive junction point connects the edge of this carrier and respectively this adheres to promotion portion and forms the circuit that communicates.
7. circuit substrate structure according to claim 6 is characterized in that, an anti-plating insulating barrier is set on the metal level of each said conductive junction point.
8. circuit substrate structure according to claim 7 is characterized in that, on each said metal level an electrodeposited coating is set.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200243461U CN202488870U (en) | 2012-01-18 | 2012-01-18 | Circuit substrate structure |
| PCT/CN2012/071130 WO2013107065A1 (en) | 2012-01-18 | 2012-02-14 | Circuit substrate structure and manufacturing method thereof |
| US13/533,702 US20130180773A1 (en) | 2012-01-18 | 2012-06-26 | Circuit substrate structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200243461U CN202488870U (en) | 2012-01-18 | 2012-01-18 | Circuit substrate structure |
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| Publication Number | Publication Date |
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| CN202488870U true CN202488870U (en) | 2012-10-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012200243461U Expired - Lifetime CN202488870U (en) | 2012-01-18 | 2012-01-18 | Circuit substrate structure |
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| CN (1) | CN202488870U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103220884A (en) * | 2012-01-18 | 2013-07-24 | 光宏精密股份有限公司 | Line substrate structure and manufacturing method thereof |
| CN103313523A (en) * | 2013-05-28 | 2013-09-18 | 上海安费诺永亿通讯电子有限公司 | Manufacturing method for electronic circuit |
| CN108712830A (en) * | 2018-05-30 | 2018-10-26 | 广东天承科技有限公司 | A kind of circuit board without palladium chemical-copper-plating process |
| CN110785018A (en) * | 2018-07-31 | 2020-02-11 | 精工爱普生株式会社 | Wiring board and method for manufacturing wiring board |
-
2012
- 2012-01-18 CN CN2012200243461U patent/CN202488870U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103220884A (en) * | 2012-01-18 | 2013-07-24 | 光宏精密股份有限公司 | Line substrate structure and manufacturing method thereof |
| CN103313523A (en) * | 2013-05-28 | 2013-09-18 | 上海安费诺永亿通讯电子有限公司 | Manufacturing method for electronic circuit |
| CN108712830A (en) * | 2018-05-30 | 2018-10-26 | 广东天承科技有限公司 | A kind of circuit board without palladium chemical-copper-plating process |
| CN108712830B (en) * | 2018-05-30 | 2021-02-26 | 广东天承科技股份有限公司 | Palladium-free chemical copper plating process for circuit board |
| CN110785018A (en) * | 2018-07-31 | 2020-02-11 | 精工爱普生株式会社 | Wiring board and method for manufacturing wiring board |
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