CN202475404U - Fully integrated CMOS super-regeneration time division multiplexing wireless receiver structure - Google Patents
Fully integrated CMOS super-regeneration time division multiplexing wireless receiver structure Download PDFInfo
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- CN202475404U CN202475404U CN2011204511597U CN201120451159U CN202475404U CN 202475404 U CN202475404 U CN 202475404U CN 2011204511597 U CN2011204511597 U CN 2011204511597U CN 201120451159 U CN201120451159 U CN 201120451159U CN 202475404 U CN202475404 U CN 202475404U
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Abstract
The utility model discloses a fully integrated CMOS (Complementary Metal-Oxide-Semiconductor Transistor) super-regeneration time division multiplexing wireless receiver structure in an analogue integrated circuit. A receiver adopts a time division multiplexing control mode to solve a contradiction between stabilizing oscillation-starting time and raising receiving sensitivity. The fully integrated CMOS super-regeneration time division multiplexing wireless receiver structure comprises a radio-frequency amplifier, an SRO (Super Regeneration Oscillator) having a loop control function, an envelope detection circuit, a comparator, a logic circuit, a charge pump, a low pass filter, a black-out signal generation circuit, and a data demodulation circuit; wherein, the SRO operates in an intermittent oscillation state, an intermittent oscillation period of the SRO is controlled by a black-out signal, oscillation-starting time in the each oscillation period is determined by an input signal amplified by a low noise amplifier; oscillation-starting time variation is converted into pulse width variation via the envelope detection, output data is obtained after a pulse is processed by the demodulation circuit. The fully integrated CMOS super-regeneration time division multiplexing wireless receiver structure of the utility model integrates multi-channel control clock and the black-out signal generation circuit therein, so that the whole receiver operates in a synchronous clock mode, thereby reducing noises generated by the control clock.
Description
Technical field
The utility model relates to the wireless superregeneration receiver system architecture of communications field short-distance and medium-distance.
Background technology
Owing to have simple in structure, low in energy consumption, low cost and other advantages, be fit to very much short distance radio communication systems such as wireless sense network, family are controlled automatically, antitheft based on the theoretical wireless receiver of superregenerative.
Fig. 1 is typical superregeneration receiver, comprises that radio frequency amplifier, superregenerator (SRO), black out signal produce circuit, envelope detection circuit and demodulator circuit etc.Superregenerator is operated in the intermittent oscillation state, controls its cycle of oscillation at intermittence by black out signal, but the starting of oscillation time in each cycle of oscillation is then mainly determined by the input signal after amplifying through low noise amplifier.When the consistent perhaps input signal strength with oscillator frequency of frequency input signal is strong; The oscillator starting of oscillation time shortens; Otherwise the starting of oscillation time increases, and this starting of oscillation time that changes along with frequency input signal or Strength Changes is exactly the foundation of superregeneration receiver difference input signal logic.Through after the envelope detection, this starting of oscillation change of time changes the variation of pulse duration into, and pulse obtains dateout through behind the demodulator circuit.
The ability that superregeneration receiver receives signal relies on its superregenerator starting of oscillation change of time when receiving signal, and this variable quantity is big more, and system's receiving sensitivity is high more.But superregenerator is operated in the intermittent oscillation state, and its starting of oscillation time is very responsive to technology, temperature, noise etc.Above-mentioned factor possibly make the oscillator starting of oscillation too fast or slow excessively, and not even starting of oscillation causes correctly identification signal of system.In theory, the starting of oscillation time that can come control generator through the bias current size that changes oscillator.But this electric current is bigger with factors vary such as flow-route and temperatures, is difficult to control.For the operating state of stabilized oscillator, the control circuit of the complicacy that is made up of microprocessor and digital to analog converter is used to search and correct automatically the bias current of oscillator, and this has increased the complexity of system greatly.
The utility model adopts the loop that is similar to phase-locked loop that is made up of superregenerator, high efficiency envelope detector and high accuracy charge pump etc. to come the bias current of control generator; Thereby the starting of oscillation state of stabilized oscillator, have simple in structure, be easy to integrated and steady performance.But obtaining stable starting of oscillation state and improving between the receiving sensitivity is contradiction.For this reason, the receiver of the utility model has adopted time-multiplexed control model, has effectively avoided this contradiction.In addition, in order to reduce to control the influence of the noise of clock generating to receiving sensitivity as far as possible, receiver is inner integrated, and multichannel control clock and black out signal produce circuit, make whole operation of receiver in the synchronised clock pattern.
The utility model content
The utility model emphasis has solved the theoretical question of negative feedback control loop, oscillator starting of oscillation time and current source, inject signal strength signal intensity concern problem, the stability problem of negative feedback control loop.Because the purpose of loop control is to stablize the starting of oscillation state of superregenerator, and the change starting of oscillation state that the reception of signal requires oscillator not stop according to the intensity that receives signal, the two is a contradiction.The utility model makes the two obtain good balance and compatibility through adopting time-multiplexed architecture, has dissolved this contradiction.Steady operation for this architecture; And the performance of raising system, in the utility model each main circuit module is all carried out deep analysis and research, and proposed multinomial corrective measure; Make each circuit module can stably be system service, and have higher circuit performance.Fully integrated CMOS superregenerative time division multiplexing wireless receiver structure is: radio frequency amplifier connects superregenerative oscillator SRO; Get into comparator through envelope detection circuit again; Feed back to charge pump through logical circuit,, produce circuit with black out signal and be connected control generator formation linkloop jointly through low pass filter; Export to data demodulation circuit through the logical circuit computing at last and accomplish the total function; It is characterized in that this structure has the superregenerative oscillator SRO of band road controlled function, black out signal produces circuit, and passes through the reponse system that logical circuit forms.
Description of drawings
Fig. 1 superregeneration receiver basic principle figure
The superregeneration receiver systematic schematic diagram that Fig. 2 the utility model adopts
He puts out formula superregeneration receiver oscillogram Fig. 3
Fig. 4 radio frequency amplifier
Fig. 5 oscillator SRO
Fig. 6 black out signal produces circuit
Fig. 7 current source circuit
Fig. 8 envelope detector
Fig. 9 charge pump circuit
Embodiment
The superregeneration receiver structure of the utility model is as shown in Figure 2.This operation of receiver puts out mode at him, realizes the function and the performance of system requirements through a plurality of modular circuits.Comprise: the SRO (comprising SRO, envelope detection circuit, comparator, logical circuit, charge pump, low pass filter) of radio frequency amplifier, band road controlled function, black out signal produce circuit and data demodulation circuit.
The physical circuit module that the utility model superregeneration receiver will be discussed below realizes:
1, Radio Frequency Amplifier Design
The radio frequency amplifier of utility model is as shown in Figure 4.Circuit adopts classical cascodes, and this structure has the upper limiting frequency height, reverse isolation degree advantages of higher.
Compare with the traditional active inductance, the active inductance of the utility model design is many resistance R d is shown in Fig. 4 frame of broken lines.This resistance can effectively reduce the influence of the parasitic capacitance Cgd of metal-oxide-semiconductor M3, is obtaining under the equal inductance value prerequisite, and the introducing of Rd makes quality factor and self-resonant frequency to be improved
2, the design of oscillator SRO
Have in the superregenerator of loop controlled function, oscillator is a Key Circuit.This oscillator will have the control port of extinguishing, and realizes the intermittent oscillation function, will have input interface simultaneously, and input signal is coupled in the LC resonant tank, also will have good reverse isolation performance, reduces local oscillator as far as possible and reveals.The oscillator of the utility model design is as shown in Figure 5, and wherein the LC in the frame of broken lines is the outer device of sheet.Among the figure, the cross-coupled differential that PMOS pipe M5 and M6 constitute oscillator is right, does not adopt nmos differential right, and purpose is in order to make full use of the automatic biasing effect in the starting of oscillation process, to improve the system envelope detection efficiency.Among Fig. 5, the differential pair source electrode is a supply voltage, because the automatic biasing effect, the output average voltage can rise in the starting of oscillation process gradually, up to reaching stable state.In conjunction with follow-up envelope detection circuit, can effectively improve the envelope detection efficient of system.M7 and M8 formation is extinguished control switch among the figure, and under the control signal effect, oscillator is operated in the intermittent oscillation state.M3 and M4 constitute grid level altogether, reduce the reverse leakage of oscillator signal.M1 and M2 formation input stage will be coupled in the resonant tank from the signal of pre-amplifier, thereby influence the starting of oscillation time of oscillator.M9 constitutes current source, and the value of electric current is determined according to the starting of oscillation state by loop automatically, has avoided the influence of factors such as technology, temperature, power supply.
3, black out signal produces circuit
In the system schema of Fig. 2; The black out signal generator mainly produces the black out signal of oscillator; System carries out the square-wave signal of clock signal and any duty ratio of time division multiplexing reception, and each road control signal that this circuit produces is being controlled the work schedule of system, is the control centre of whole system.As shown in Figure 6.
According to the requirement of system, the black out signal generator need satisfy following requirement: operate as normal when operating voltage range is 2.5～5.5V, and the frequency of black out signal and independent of power voltage; Each the road control signal that produces is a synchronizing signal; The edge of all control signals all can not influence the starting of oscillation time of oscillator, mainly refers to because the parasitic damped oscillation signal that this edge signal produces in system can not influence the starting of oscillation time of oscillator.
In order to reduce the clock edge; Especially rising edge is to the influence of oscillator starting of oscillation time; Adopt among Fig. 6 and monolaterally black out signal is carried out rise edge delay along delay circuit (among the figure in the frame of broken lines circuit); Make in it produces the time of noise, oscillator is in and extinguishes state, thereby avoids the edge The noise.
4, current source circuit
Current source circuit is responsible for to each module for power supply, and especially radio frequency amplifier is to the having relatively high expectations of current source, thus requirement: with supply independent, but relevant with temperature, technology etc., and the variation of this correlation energy compensation temperature and technology is to the influence of mutual conductance.Its schematic diagram such as Fig. 7.
5, envelope detector
The envelope detector that adopts in the loop has increased differential amplifier on the basis of traditional full-wave rectifying circuit, constitute the envelope detector with positive feedback effect, and is as shown in Figure 8.
Circuit has adopted positive feedback loop; When circuit design, to select suitable parameters; Avoid the generation of vibrating. because envelope detection circuit has a bigger electric capacity at output; If this node as the loop dominant pole, is guaranteed that simultaneously other node is the low-resistance node all in the loop, and selects suitable loop gain just can guarantee the steady operation of loop.
6, charge pump circuit
For the sequential that guarantees system is correct, the ratio that discharges and recharges of charge pump must be accurately with stable in the loop. and as shown in Figure 9.
It is stable that this structure makes each circuit node voltage relevant with the charging and discharging currents ratio all keep, and the node voltage of effectively having avoided causing owing to switch control in the conventional charge pump changes, thereby has avoided node voltage to set up needed settling time.
Claims (1)
1. fully integrated CMOS superregenerative time division multiplexing wireless receiver structure; Its structure is: radio frequency amplifier connects superregenerative oscillator SRO, gets into comparator through envelope detection circuit again, feeds back to charge pump through logical circuit; Through low pass filter; Produce circuit with black out signal and be connected control generator formation linkloop jointly, export to data demodulation circuit through the logical circuit computing at last and accomplish the total function, it is characterized in that this structure has the superregenerative oscillator SRO of band road controlled function; Black out signal produces circuit, and passes through the reponse system that logical circuit forms.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011204511597U CN202475404U (en) | 2011-11-15 | 2011-11-15 | Fully integrated CMOS super-regeneration time division multiplexing wireless receiver structure |
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| CN2011204511597U CN202475404U (en) | 2011-11-15 | 2011-11-15 | Fully integrated CMOS super-regeneration time division multiplexing wireless receiver structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103023522A (en) * | 2012-12-05 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption awakening receiver of wireless node of internet of things and short-distance wireless internet |
| CN103259552A (en) * | 2013-05-07 | 2013-08-21 | 中山大学 | Superregenerative receiver with ultra-low power consumption |
| CN112769440A (en) * | 2020-11-04 | 2021-05-07 | 山东科技大学 | Low-power-consumption digital intelligent USBL receiver |
-
2011
- 2011-11-15 CN CN2011204511597U patent/CN202475404U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103023522A (en) * | 2012-12-05 | 2013-04-03 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption awakening receiver of wireless node of internet of things and short-distance wireless internet |
| CN103259552A (en) * | 2013-05-07 | 2013-08-21 | 中山大学 | Superregenerative receiver with ultra-low power consumption |
| CN103259552B (en) * | 2013-05-07 | 2015-03-18 | 中山大学 | Superregenerative receiver with ultra-low power consumption |
| CN112769440A (en) * | 2020-11-04 | 2021-05-07 | 山东科技大学 | Low-power-consumption digital intelligent USBL receiver |
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| C14 | Grant of patent or utility model | ||
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| DD01 | Delivery of document by public notice |
Addressee: Nanjing Sino Chip Mircoelectronics Co., Ltd. Document name: Notification to Pay the Fees |
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| DD01 | Delivery of document by public notice |
Addressee: Luo Yin Document name: Notification of Termination of Patent Right |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121003 Termination date: 20131115 |