CN202455364U - Single port random access memory (SPRAM) full-duplex communication control circuit - Google Patents
Single port random access memory (SPRAM) full-duplex communication control circuit Download PDFInfo
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- CN202455364U CN202455364U CN2012200327791U CN201220032779U CN202455364U CN 202455364 U CN202455364 U CN 202455364U CN 2012200327791 U CN2012200327791 U CN 2012200327791U CN 201220032779 U CN201220032779 U CN 201220032779U CN 202455364 U CN202455364 U CN 202455364U
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Abstract
The utility model discloses a single port random access memory (SPRAM) full-duplex communication control circuit, which comprises a read-write collision memory circuit, a write command control circuit, a write operation buffer storage and an addressing circuit, wherein the read-write collision memory circuit comprises a first latch which records a write command in the read operation process and a second latch which is connected with the first latch and outputs a control instruction when a read command is finished; the write command control circuit is provided with a third latch, wherein a reset end of the third latch is connected with a read command input end, a clock end of the third latch is connected with a write command input end and an output end of the second latch and receives the control instruction, and an output end of the third latch is connected with a write command output end; the write operation buffer storage comprises a data buffer storage and an address buffer storage; and two input ends of the addressing circuit are respectively connected with a read address input end and an output end of the address buffer storage, an output end of the addressing circuit is connected with an address output end, and a control end of the addressing circuit is connected with the read command input end. The SPRAM full-duplex communication control circuit has the effects of saving the size of chips and reducing the occupied space.
Description
Technical field
The utility model relates to the control circuit field, relates to a kind of SPRAM full-duplex communication control circuit in particular, and it is fitted between SPRAM read-write control circuit and the SPRAM body, thereby reach the full duplex of SPRAM body is used.
Background technology
Adopt the led array scanning drive chip of SRAM as memory device, chip internal needs constantly periodically continuous reading of data from SRAM when operate as normal, and driving LED shows thereby be used for correctly.Simultaneously, the master control device shows that in order to control led array need to use I2C serial communication mode write data in SRAM constantly, read operation and write operation possibly initiated SRAM simultaneously thus.
SPRAM (Single Port SRAM; Abbreviation SPRAM) the kernel unit circuit is made up of 6 metal-oxide-semiconductors; The memory that the SPRAM unit is formed has only a group address bus and one group of data/address bus; Be the shared group address bus of read and write operation address bus, the then shared one group of data/address bus of read and write data; Be that the SPRAM body can only carry out half-duplex operation, so make SPRAM based on the restriction of itself structure and can't be used in the environment of full-duplex communication.
DPRAM (Duel Port RAM; Abbreviation DPRAM) the kernel unit circuit is made up of 8 metal-oxide-semiconductors; The memory that the DPRAM unit is formed comprises reads address bus, write address bus, write data bus and read data bus; But its chip area almost is the twice of SPRAM, thereby the DPRAM circuit of identical storage data volume almost is 2 times of SPRAM circuit layout area.So, realize in the circuit environment to the memory full-duplex communication at needs, use DPRAM to replace SPRAM, increase the chip area that memory occupies greatly, thereby increased this a part of chip cost greatly.
In view of this, the inventor has this case to produce to the above-mentioned defective further investigation that exists in the existing memory then.
The utility model content
The purpose of the utility model is to provide a kind of SPRAM full-duplex communication control circuit; It is connected between SPRAM read-write control circuit and the SPRAM body; Letting the SPRAM body realize full-duplex communication, and solve that there is the big problem of chip area that occupies in the full-duplex communication memory in the prior art.
In order to reach above-mentioned purpose, the solution of the utility model is:
A kind of SPRAM full-duplex communication control circuit wherein, comprising:
The read/write conflict memory circuit is connected with read command input and write order input, has to be used for being recorded in first latch of read operation process write order and to link to each other with first latch and second latch of output control command when read command finishes;
The write order control circuit; Has the 3rd latch; The reset terminal of the 3rd latch links to each other with the read command input, and clock end then links to each other with the output of the write order input and second latch and receives control command, and output then is connected with the write order output;
The write operation buffer storage has Data Buffer Memory and address buffer memory, and the input of this Data Buffer Memory is connected with the write data input, and output then is connected with the write data output; The input of this address buffer memory is connected with the write address input;
Addressing circuit, two inputs are connected with the output of reading address input end and address buffer memory respectively, and output then is connected with address output end, and control end then links to each other with the read command input.
Further; This write order control circuit also has the time-delay reset counter; The clock end of this time-delay reset counter and the usage quantity output of read-write clock end and write order output or Data Buffer Memory do with logic after output link to each other; The output of this time-delay reset counter then through one with behind the door, again through the reset terminal of signal controlling the 3rd latch behind delayer and the reset terminal of time-delay reset counter.
Further, the positive input terminal of this addressing circuit with read address input end and link to each other, negative input end then links to each other with the output of address buffer.
Further, this Data Buffer Memory and address buffer memory all adopt the push-up storage of multibyte storage.
After adopting said structure; A kind of SPRAM full-duplex communication control circuit that the utility model relates to; When the SPRAM read-write control circuit sends read command and write order simultaneously; This read command meeting directly arrives the SPRAM body, and this reads the address also through arriving the SPRAM body through address output end behind the addressing circuit, thereby guarantees preferentially carrying out of read command; This write order then can be recorded in first latch; Write data and write address then are stored through Data Buffer Memory and address buffer memory respectively; After in case second latch detects the read command end; Then can notify the 3rd latch immediately, and send write order to the SPRAM body by the write order output.In addition, the utility model when write order when free time of read command produces, because this write order input directly links to each other with the clock end of the 3rd latch, so also can send write order to the SPRAM body by the write order output.Thus; Compared with prior art; The utility model can let the SPRAM body realize full duplex; And because the SPRAM full-duplex communication control circuit that the utility model relates to is less compared to the volume that the DPRAM body increases, thus the chip layout of saving area had, and then the effect of practicing thrift chip cost.
Description of drawings
The sketch map of Fig. 1 when a kind of SPRAM full-duplex communication control circuit is connected between SPRAM read-write control circuit and the SPRAM body for the utility model relates to;
The physical circuit figure of Fig. 2 a kind of SPRAM full-duplex communication control circuit first embodiment for the utility model relates to;
The physical circuit figure of Fig. 3 a kind of SPRAM full-duplex communication control circuit second embodiment for the utility model relates to;
Fig. 4 is the control timing sketch map of a kind of SPRAM full-duplex communication control circuit when read/write conflict for the utility model relates to.
Among the figure:
SPRAM full-duplex communication control circuit 100
Read/write conflict memory circuit 1 first latch 11
Second latch, 12 rising edge testing circuits 13
Write order control circuit 2 the 3rd latch 21
Time-delay reset counter 22 quad latch 23
The 5th latch 24 write operation buffer storage 3
Addressing circuit 4
SPRAM read-write control circuit 200 SPRAM bodies 300.
Embodiment
In order further to explain the technical scheme of the utility model, come the utility model is set forth in detail through specific embodiment below.
As shown in Figure 1, it is connected the sketch map between SPRAM read-write control circuit 200 and the SPRAM body 300 its a kind of SPRAM full-duplex communication control circuit that relates to for the utility model 100.
This SPRAM full-duplex communication control circuit 100, its input have write order input, write address input, write data input, read address input end, clock end and read command input; Its output has write order output, write data output and address output end.For the read command of SPRAM read-write control circuit 200, its one side links to each other with the read command input of the SPRAM full-duplex communication control circuit 100 that the utility model relates to, and also directly links to each other with SPRAM body 300 on the other hand; In addition, the read data of this SPRAM body 300 also directly links to each other with SPRAM read-write control circuit 200, thereby the data of storage in the SPRAM body 300 are sent to 200 uses of SPRAM read-write control circuit.
As shown in Figure 2, first embodiment of its a kind of SPRAM full-duplex communication control circuit 100 for the utility model relates to, it specifically is meant and is used to realize 1 byte buffer-stored, the situation that it is only applicable to continuous read/write conflict maximum is 1 byte.
This SPRAM full-duplex communication control circuit 100 comprises read/write conflict memory circuit 1, write order control circuit 2, write operation buffer storage 3 and addressing circuit 4, wherein:
This read/write conflict memory circuit 1; Have first latch 11 and second latch 12; In the present embodiment, this read command input and write order input through first with link to each other with the clock end of this first latch 11 behind the door, thereby be used for being recorded in the write order of read operation process; The D of this second latch 12 end then links to each other with the Q end of first latch 11, and this read command input passes through first and non-ly links to each other with the clock end of second latch 12 behind the door; The reset terminal of this first latch 11 and second latch 12 all links to each other with the read command input simultaneously; Thereby first latch 11 is resetted and be convenient to count next time; 12 of this second latchs are to be used for when read command finishes, producing control command; Concrete is to utilize rising edge that read command input trailing edge signal produced after doing NOT logic as clock signal in the present embodiment, drives the output end signal that second latch 12 deposits first latch 11 in, and then produces control command; Promptly also be provided with rising edge testing circuit 13 between this second latch 12 and the read command input; Thereby when read command becomes high level and begins, producing a rising edge controls second latch 12 and resets; Make this second latch 12 when read operation begins, reset, and then write down the write command signal in the read operation process again.
This write order control circuit 2; Has the 3rd latch 21; The reset terminal of the 3rd latch 21 links to each other with the read command input; Thereby make the operating state of the 3rd latch 21 also controlled by the read command input, thereby the priority of guaranteeing read command is higher than write order, promptly reaching only has the purpose that when read command finishes, could open write order; The clock end of the 3rd latch 21 then all links to each other with the output of the write order input and second latch 12; Concrete its can be accepted the instruction of write order input and receive the control command that the read/write conflict memory circuit sends, and output then is connected with the write order output; Preferably; This write order control circuit 2 also has time-delay reset counter 22; The clock end of this time-delay reset counter 22 is done with the output of logic with the write order output with the read-write clock end and is linked to each other; Thereby sensing obtains the output of write order in real time; The output of this time-delay reset counter 22 is then done the count value ' 01 ' decoding of counter through one with door, again through the reset terminal of the 3rd latch 21 of the signal controlling behind the delayer of a 40ns and the reset terminal of time-delay reset counter 22, thereby realizes resetting to the 3rd latch 21 and time-delay reset counter 22 itself; Concrete, this time-delay reset counter 22, it comprises quad latch 23 and the 5th latch 24, thereby can realize 1 clock cycle of time-delay reset write command signal.
This write operation buffer storage 3 has Data Buffer Memory 31 and address buffer memory 32, and the input of this Data Buffer Memory 31 is connected with the write data input, and output then is connected with the write data output; The input of this address buffer memory 32 is connected with the write address input; Concrete, because present embodiment only carries out a bytes of memory, so this Data Buffer Memory 31 all can adopt the LATCH of 1 byte to come practical implementation with address buffer memory 32.
These addressing circuit 4, two inputs are connected with the output of reading address input end and address buffer memory 32 respectively, and output then is connected with address output end, and control end then links to each other with the read command input.Concrete, it adopts selects door to realize, and the positive input terminal of this addressing circuit 4 with read address input end and link to each other, negative input end then links to each other with the output of address buffer.Promptly when the read command input was high level, then the address of address output end output was a signal of reading address input end; And when the read command input was low level, then the address of address output end output was the address in the address buffer memory 32.
As shown in Figure 3, second embodiment of its a kind of SPRAM full-duplex communication control circuit 100 for the utility model relates to, it specifically is to be used to realize the multibyte buffer-stored, promptly it is applicable to that continuous read/write conflict maximum is the situation of a plurality of bytes.
Need to prove that the structural principle of this second embodiment and first embodiment is basic identical, so both identical parts are not described in detail, the difference part in the face of second embodiment is elaborated down:
At first in order to realize multibyte buffering; This Data Buffer Memory 31 and address buffer memory 32 all adopt the push-up storage of multibyte storage; It has the characteristics of first in first out, thereby can let the repeatedly write order that during a read command, takes place write successively in the SPRAM body 300 according to time order and function.Secondly; For just write order can after write data finishes fully, be stopped; The clock end of this time-delay reset counter 22 links to each other with the output of Data Buffer Memory 31; And the output of this Data Buffer Memory 31 also links to each other with the clock end of the 3rd latch 21, thus be used to control write order continue carry out.
Please with reference to shown in Figure 4, the course of work that the utility model relates to a kind of SPRAM full-duplex communication control circuit 100 is following:
When SPRAM read-write control circuit 200 sends read command and write order simultaneously; This read command meeting directly arrives SPRAM body 300; This is read the address and also arrives SPRAM body 300 through addressing circuit 4 backs through address output end, thereby guarantees preferentially carrying out of read command; This write order then can be recorded in first latch 11; Write data and write address then are stored through Data Buffer Memory 31 and address buffer memory 32 respectively; After in case second latch 12 detects the read command end; Then can notify the 3rd latch 21 immediately, and send write order to SPRAM body 300 by the write order output.
In addition, when write order when free time of read command produces, because this write order input directly links to each other with the clock end of the 3rd latch 21, so also can send write order to SPRAM body 300 by the write order output.
Thus; Compared with prior art; The utility model can let SPRAM body 300 realize full duplex; And because the SPRAM full-duplex communication control circuit 100 that the utility model relates to is less compared to the volume that the DPRAM body increases, thus the chip layout of saving area had, and then the effect of practicing thrift chip cost.
Product form of the foregoing description and graphic and non-limiting the utility model and style, the those of ordinary skill of any affiliated technical field all should be regarded as not breaking away from the patent category of the utility model to its suitable variation or modification of doing.
Claims (4)
1. a SPRAM full-duplex communication control circuit is characterized in that, comprising:
The read/write conflict memory circuit is connected with read command input and write order input, has to be used for being recorded in first latch of read operation process write order and to link to each other with first latch and second latch of output control command when read command finishes;
The write order control circuit; Has the 3rd latch; The reset terminal of the 3rd latch links to each other with the read command input, and clock end then links to each other with the output of the write order input and second latch and receives control command, and output then is connected with the write order output;
The write operation buffer storage has Data Buffer Memory and address buffer memory, and the input of this Data Buffer Memory is connected with the write data input, and output then is connected with the write data output; The input of this address buffer memory is connected with the write address input;
Addressing circuit, two inputs are connected with the output of reading address input end and address buffer memory respectively, and output then is connected with address output end, and control end then links to each other with the read command input.
2. a kind of SPRAM full-duplex communication control circuit as claimed in claim 1; It is characterized in that; This write order control circuit also has the time-delay reset counter; The clock end of this time-delay reset counter and the usage quantity output of read-write clock end and write order output or Data Buffer Memory do with logic after output link to each other; The output of this time-delay reset counter then through one with behind the door, again through the reset terminal of signal controlling the 3rd latch behind delayer and the reset terminal of time-delay reset counter.
3. a kind of SPRAM full-duplex communication control circuit as claimed in claim 1 is characterized in that, the positive input terminal of this addressing circuit with read address input end and link to each other, negative input end then links to each other with the output of address buffer.
4. a kind of SPRAM full-duplex communication control circuit as claimed in claim 1 is characterized in that, this Data Buffer Memory and address buffer memory all adopt the push-up storage of multibyte storage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200327791U CN202455364U (en) | 2012-02-02 | 2012-02-02 | Single port random access memory (SPRAM) full-duplex communication control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200327791U CN202455364U (en) | 2012-02-02 | 2012-02-02 | Single port random access memory (SPRAM) full-duplex communication control circuit |
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| Publication Number | Publication Date |
|---|---|
| CN202455364U true CN202455364U (en) | 2012-09-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012200327791U Withdrawn - After Issue CN202455364U (en) | 2012-02-02 | 2012-02-02 | Single port random access memory (SPRAM) full-duplex communication control circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571314A (en) * | 2012-02-02 | 2012-07-11 | 矽恩微电子(厦门)有限公司 | Full-duplex communication control circuit for single port random access memory (SPRAM) |
-
2012
- 2012-02-02 CN CN2012200327791U patent/CN202455364U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571314A (en) * | 2012-02-02 | 2012-07-11 | 矽恩微电子(厦门)有限公司 | Full-duplex communication control circuit for single port random access memory (SPRAM) |
| CN102571314B (en) * | 2012-02-02 | 2015-11-18 | 矽恩微电子(厦门)有限公司 | A kind of SPRAM full-duplex communication control circuit |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120926 Effective date of abandoning: 20151118 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |