CN202405269U - Bridging grain polysilicon thin-film transistor - Google Patents
Bridging grain polysilicon thin-film transistor Download PDFInfo
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- CN202405269U CN202405269U CN 201120488284 CN201120488284U CN202405269U CN 202405269 U CN202405269 U CN 202405269U CN 201120488284 CN201120488284 CN 201120488284 CN 201120488284 U CN201120488284 U CN 201120488284U CN 202405269 U CN202405269 U CN 202405269U
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Abstract
The utility model discloses a bridging grain polysilicon thin-film transistor. The bridging grain polysilicon thin-film transistor comprises an active layer which is made of a low-temperature polysilicon semiconductor material, and a glass substrate which is used for supporting the semiconductor material, wherein the active layer is provided with a plurality of transverse conducting bridges; the positions of the transverse conducting bridges are perpendicular to the flow direction of current required in a channel region, and are parallel to the flow direction of current required by source/drain areas; and a source area and a drain area in the active layer are constructed at symmetrical or asymmetrical positions.
Description
Technical field
The utility model relates generally to polycrystalline grain thin-film transistor (TFT), more specifically, relates to a kind of polycrystalline SiTFT and manufacturing approach thereof that does not have the bridged-grain structures of source-drain electrode doping treatment.
Background technology
For realizing the industrialization manufacturing of multi-crystal TFT Active Matrix Display panel, need very high-quality polysilicon film.It need satisfy following requirement: low temperature process, can on large-area glass lining, realize, low manufacturing cost, stable manufacturing process, high-performance, consistent characteristic and the high reliability of crystal silicon TFT.
The high temperature polysilicon technology can be used for realizing high performance TFT, but it can not be used for the simple glass substrate that commercial display pannel uses.Under such situation, must use low temperature polycrystalline silicon (LTPS).Three kinds of main LTPS technology are arranged: (1) is through the solid-phase crystallization (SPC) at 600 ℃ of long term annealings; (2) PRK crystallization (ELC) or flash lamp annealing; And (3) crystallization inducing metal (MIC) and relevant variant thereof.But ELC produces best result is expensive, but the minimum time spent of SPC cost is long, and these technology all can not satisfy above-mentioned low cost and high performance all requirements.
What all polycrystal film materials were common is, the crystal grain of film is in size, crystal orientation and random distribution basically in shape.Crystal boundary is also harmful to the formation of good TFT usually, and when this polycrystal film was used as the active layer among the TFT, electrical characteristics depended on how much crystal grain of existence and crystal boundary in active channel.
The common issue with of all prior aries is that they form many crystal grain with unpredictable pattern (pattern) in the TFT active channel.The distribution of crystal grain is at random, and some is inhomogeneous on substrate to make the electrical characteristics of TFT.The wide distribution of these electrical characteristics is harmful and cause problem, for example mura defective and brightness irregularities to the performance of display.
The transistorized crystal grain of polycrystal film forms network at random.For any semi-conducting material for example silicon, germanium, sige alloy, iii v compound semiconductor and organic semiconductor, the fact is not always the case.The inner conduction of crystal grain is almost identical with crystalline material, and it is poorer and cause mobility, the threshold voltage of overall loss and increase to stride across the conduction of crystal boundary.Active channel at the thin-film transistor of being processed by this polycrystal film (TFT) is inner, and grainiess almost is the two-dimensional random network.Randomness and consequential variable-conductance influence display performance and picture quality unfriendly.
Typical polysilicon structure shown in Fig. 1 a, low temperature polycrystalline silicon film 101 comprises crystal grain 102.Tangible crystal boundary 103 is arranged between adjacent crystal grain 102.The length scale of each crystal grain 102 to several microns, and is considered to monocrystalline from tens nanometer.The defect distribution of many dislocations, stacking fault and dangling bonds is in said crystal boundary 103.Because different preparation, low temperature polycrystalline silicon film 101 inner crystal grain 102 can the definite orientation of random distribution or edge.As for the low temperature polycrystalline silicon film 101 of routine, serious defective is arranged, shown in Fig. 1 b in crystal boundary 103.Major defect in crystal boundary 103 will be introduced high potential barrier 104.To influence the initial condition and the ability of charge carrier perpendicular to the said potential barrier 104 (or vertical component of inclination potential barrier) of charge carrier 105 transmission directions.For the thin-film transistor of on this low temperature polycrystalline silicon film 101, making, threshold voltage and field-effect mobility receive 104 restrictions of crystal boundary potential barrier.When high reverse gate voltage was applied among the TFT, the crystal boundary 103 that is distributed in the tie region also caused big leakage current.
At U.S. Pat 2010/0171546A1 (full content of this patent all technology be incorporated herein) as a setting, disclosed the polycrystalline SiTFT (TFT) of a kind of bridged-grain (BG) structure.Adopt doping BG polysilicon lines, intrinsic-OR light dope passage is separated into a plurality of zones.Single gate has covered the whole active channel that comprises the doping line, is used for the flowing of Control current.The source drain region of BG TFT needs further secondary heavy doping to handle.Fig. 2 is the source and the sketch map that leaks injection of the polycrystalline SiTFT of bridged-grain (BG) structure.As shown in Figure 2, dosage is 4*10
14/ cm
2Boron ion 903 utilize gate electrode 802 to be injected into raceway groove as the ion barrier layer.The source is formed with leakage 902.Raceway groove 901 below the gate electrode 802 does not mix.Use the BG polysilicon as active layer, TFT is designed to make current vertical to flow through the parallel lines at the passage crystal region, and the influence of crystal boundary can reduce.Compare with traditional low temperature polycrystalline silicon TFT, the reliability of BG multi-crystal TFT, uniformity and electric property all are significantly improved.
The utility model content
The purpose of the utility model is for better layout and the manufacturing process of simplifying the BG polycrystalline SiTFT are provided.Utilize the new layout that is disclosed, source/drain electrode doping treatment there is no need.Thereby simplified manufacturing process and manufacturing cycle, reduced cost.Owing to there is not source/drain electrode doping process, the processing of dopant activation also there is no need.Therefore, there is source/drain electrode electrode dopant activation problem of the n type TFT of metal gates also to be readily solved.
The application discloses a kind of bridge formation crystallization polycrystalline SiTFT and manufacture process thereof of new construction.
Wherein a kind of bridged-grain polycrystalline SiTFT comprises one by low temperature polycrystalline silicon semi-conducting material active layer that constitutes and the glass substrate that supports above-mentioned semi-conducting material, has a plurality of transverse conductance bridges in the active layer; It is characterized in that the position of transverse conductance bridge is perpendicular to required flow of current direction in the channel region, the position of transverse conductance bridge is parallel to required flow of current direction in source/drain region; Source area in the active layer and drain region are configured to symmetry or asymmetric position.
Source area in the active layer and drain region are configured to an asymmetric position, and channel region connects an end of source area and the other end of drain region respectively, and active layer is designed to zigzag.
Active layer is configured to up and down symmetry of source/drain region, and channel region is positioned at that the source/left side, drain region is with connection source/drain region, and active layer is designed to the C font.
Transverse conductance bridge width in the active layer is less than 10 μ m, and spacing is less than 10 μ m.
Semiconductor is the low temperature polycrystalline silicon material that is formed by laser annealing, solid phase crystallization or metal-induced crystallization.
Source/drain and semiconductor regions take shape in a common layer that is made up of low temperature polycrystalline silicon.
Grid covers the half the part that surpasses of above-mentioned active channel, comprises a plurality of high resistance and low-resistance traversed zone, and grid and the insulation of above-mentioned active channel.Traversed zone mixes and forms parallel lines.The unit are dosage of traversed zone dopant is 1 * 10
14/ cm
2-1 * 10
16/ cm
2, be preferably 2 * 10
15/ cm
2-4 * 10
15/ cm
2
The manufacture process that this forms the bridged-grain polycrystalline SiTFT comprises the steps: step 1, makes polysilicon membrane, forms an active region; Step 2, a plurality of leads of almost parallel each other of manufacturing; The position of lead is perpendicular to required flow of current direction in the channel region in the active region; Simultaneously, the position of lead is parallel in the active region required flow of current direction in source/drain region.
Through using the new construction that is disclosed, source/drain electrode doping treatment no longer is necessary.Two ion implantation process disclosed in traditional BGTFT can reduce to one.
Through technique scheme, the utility model provides advantage: improve electrical property; Improve field-effect mobility; Improve the uniformity of making current.Reduce cost; Reduce threshold voltage and leakage current; The randomness of grain mobility and grain boundary resistance reduces; In " connection " state, reduce potential barrier and improve carrier mobility; In " shutoff " state, reduce leakage current; Simplify technology and shortened the processing time; After forming metal gates, no longer need activate the source-drain electrode alloy.
Description of drawings
Fig. 1 a is a typical polysilicon structure in the prior art;
Fig. 1 b is the figure of the corresponding potential barrier of Fig. 1 a;
Fig. 2 is the source and the sketch map that leaks injection of U.S. Pat 2010/0171546A1 polycrystalline SiTFT;
Fig. 3 is the anisotropy test structure layout of the conductivity of BG line;
Fig. 4 is the test result of BG line conductivity;
Fig. 5 is first embodiment of bridged-grain polycrystalline SiTFT layout;
Fig. 6 is second embodiment of bridged-grain polycrystalline SiTFT layout;
Fig. 7 is the transmission characteristic of first embodiment of bridged-grain polycrystalline SiTFT layout;
Fig. 8 is the transmission characteristic of second embodiment of bridged-grain polycrystalline SiTFT layout.
Embodiment
A kind of there is not the bridged-grain polycrystalline SiTFT of source-drain electrode doping treatment to be described in detail below in conjunction with accompanying drawing and specific embodiment to what the utility model provided.
Here do simultaneously is that more detailed in order to make embodiment, following embodiment be the best, preferred embodiment, also can adopt other alternative and implements for some known technology those skilled in the art with explanation; Simultaneously, accompanying drawing is not strict in proportion the drafting, and its emphasis only is to be placed on the disclosed principle.
The BG TFTs layout of institute's utility model is utilized the anisotropy (electric current is parallel to BG line direction and current vertical is inequality in the electrology characteristic of BG line direction) of BG line conductivity, to eliminate the source/drain doping process in the patent that U.S. Patent number is US2010/0171546A1.
The BG line is the doped region along Y direction.When applying voltage, just there is not energy barrier in current flow path along the BG line.Therefore, the BG structural table reveals lower resistivity.On the contrary, several when the BG line is applied voltage when striding across, high resistivity will appear in the BG structure, contacts knot because the there has formed the semiconductor that is formed by a series of doping BG lines (301) and doped region (302) not.Fig. 3 has provided the test of BG structural conductive rate.
Testing procedure and result are as shown in Figure 4.When between electrode 11 and 12, applying voltage, then measure the electric current of pA order magnitude range.When between electrode 11 and 21, applying voltage, then measurement result is the electric current of mA order magnitude range.This presentation of results, the direction of parallel and vertical BG line, resistivity have very big difference.In the direction that is parallel to the BG line, resistance is very little.And in the direction perpendicular to the BG line, resistance is very big.The resistivity of two directions differs and reaches 9 one magnitude.
Based on above such fact; According to the utility model first embodiment; Design a kind of new bridged-grain polycrystalline SiTFT active layer layout; Wherein this bridged-grain polycrystalline SiTFT comprises an active layer that is made up of the low temperature polycrystalline silicon semi-conducting material, in active layer, has a plurality of transverse conductance bridges.Wherein the position of transverse conductance bridge is perpendicular to required flow of current direction in the channel region; Simultaneously, the position of transverse conductance bridge is parallel to required flow of current direction in source/drain region.
In Fig. 5, a zigzag active layer is proposed, the source area and the drain region that are about in the active layer are configured to an asymmetric position, and channel region connects an end of source area and the other end of drain region respectively, thereby active layer is designed to zigzag.Preferably, this transverse conductance bridge width is less than 10 μ m, and spacing is less than 10 μ m; The transverse conductance bridge is to form through channel layer is mixed; More preferably, wherein the semiconductor of low temperature polycrystalline silicon semi-conducting material is the low temperature polycrystalline silicon material that is formed by laser annealing, solid phase crystallization or metal-induced crystallization.
Simultaneously, adopt glass substrate to support above-mentioned semi-conducting material, and covered the major part of active channel, comprise a plurality of high resistance and low-resistance traversed zone, and grid insulate with above-mentioned active channel with grid.Traversed zone wherein can be preferably to mix and form parallel lines, and the scope of choosing of the unit are dosage of above-mentioned traversed zone dopant is 1 * 10
14/ cm
2-1 * 10
16/ cm
2, be preferably 2 * 10
15/ cm
2-4 * 10
15/ cm
2Doped region forms with the ion injection mode.Device with p type raceway groove is an example, and a back bias voltage on the grid is opened TFT, and drain electrode adds negative voltage.Electric current flows to channel region along the BG line from source electrode.Back bias voltage on the grid is induced the active layer transoid.Raceway groove therefore conducts electricity and electric current is gone into the drain region along the BG linear flow.Filled arrows is represented current direction in the regions and source.At the device shuts off state, positive bias-voltage imposes on grid, and raceway groove is non-conductive.A series of reverse biased junctions have hindered electric current.As a result, the electric current channel region of can not flowing through.
The main distinction of the design and U.S. Pat 2010/0171546A1 is:
In U.S. Pat 2010/0171546A1, the BG line all is perpendicular to direction of current flow in device channel and source drain zone.The formation of source drain is to carry out secondary doping by other ion implantation technology to realize.
In the design, made full use of the anisotropy of the conductivity of BG line.In the source drain zone, make flow of current direction and BG line parallel.And in device channel, make direction of current flow vertical with the BG line.
Preamble is verified, and in the direction along the BG line length, resistance is very little, and the conductivity of BG line is very high.Therefore in the source drain zone, if electric current is along flowing with BG line parallel direction, the resistance in this path is very little, does not therefore need to carry out second time ion implantation technology again and mixes.
And in the device channel zone, sense of current is vertical with the BG line.Design makes the device of this patent design keep all mentioned advantages of U.S. Pat 2010/0171546A1 like this.
In the specific embodiment of the utility model, the relative direction of the flow direction of Control current and BG line is (with respect to the design of traditional rectangular active layer) that the shape (Z type and C type) by the brand-new design active layer realizes.
According to the utility model second embodiment, design a kind of new bridged-grain polycrystalline SiTFT active layer layout, as shown in Figure 6.Propose a C shape active layer, active layer is configured to source/drain region symmetry up and down, and channel region is positioned at source/left side, drain region, with connection source/drain region, thereby active layer is designed to the C font.The operation principle of second embodiment is identical with the Z-shaped equipment of first embodiment design of the utility model.Filled arrows is represented the flow direction of electric current in the regions and source.Dotted arrow is represented the flow direction of electric current in the raceway groove.Wherein this bridged-grain polycrystalline SiTFT comprises an active layer that is made up of the low temperature polycrystalline silicon semi-conducting material, in active layer, has a plurality of transverse conductance bridges.Wherein the position of transverse conductance bridge is perpendicular to required flow of current direction in the channel region; Simultaneously, the position of transverse conductance bridge is parallel to required flow of current direction in source/drain region.Preferably, this transverse conductance bridge width is less than 10 μ m, and spacing is less than 10 μ m; The transverse conductance bridge is to form through channel layer is mixed; More preferably, wherein the semiconductor of low temperature polycrystalline silicon semi-conducting material is the low temperature polycrystalline silicon material that is formed by laser annealing, solid phase crystallization or metal-induced crystallization.Simultaneously, adopt glass substrate to support above-mentioned semi-conducting material, and covered the major part of active channel, comprise high resistance and low-resistance a plurality of traversed zone, and grid insulate with above-mentioned active channel with grid.Traversed zone wherein can be preferably to mix and form parallel lines, and the scope of choosing of the unit are dosage of above-mentioned a plurality of traversed zone dopants is 1 * 10
14/ cm
2-1 * 10
16/ cm
2, be preferably 2 * 10
15/ cm
2-4 * 10
15/ cm
2Doped region forms with the ion injection mode.
The application of the new layout of TFT among above-mentioned two kinds of embodiment, device manufacturing process are that BG TFT utility model is identical among the U.S. Pat 2010/0171546A1 with U.S. Patent number almost.Unique difference is that this utility model does not have source/drain doping process or the activation of mixing after being etched into gate electrode.It is understandable that to those skilled in the art simultaneously; Though what in embodiment one or two, form is zigzag active layer or C font active layer; Yet this only is preferred embodiment; Be appreciated that according to specification and accompanying drawing thereof other distortion of any embodiment also are conspicuous to those skilled in the art, such as other asymmetric active layers; Or U font and reverse C font etc., also all can realize the utility model.Certainly,, also can make H font or I-shaped line, the diagonal angle or be positioned at getting final product of raceway groove one side as source-drain electrode in order to increase the convenience of wiring.
Next, the utility model provides a kind of method that forms polycrystalline silicon semiconductor film of making according to above-mentioned new bridged-grain polycrystalline SiTFT active layer layout, at first makes polysilicon membrane, forms an active region; Make a plurality of leads of almost parallel each other then; Wherein the position of lead is perpendicular to required flow of current direction in the channel region in the active region; Simultaneously, the position of lead is parallel in the active region required flow of current direction in source/drain region.
This lead is the transverse conductance bridge; The source area and the drain region that wherein are about in the active layer are configured to an asymmetric position, and channel region connects an end of source area and the other end of drain region respectively, thereby active layer is designed to zigzag; Or active layer is configured to up and down symmetry of source/drain region, and channel region is positioned at source/left side, drain region, with connection source/drain region, thereby active layer is designed to the C font.Said conductor width less than 10 μ m, spacing less than 10 μ m.
Forming polysilicon membrane by amorphous silicon membrane can change with the order of making a plurality of leads.Thereby and when forming polycrystalline silicon semiconductor film, carry out doped polycrystalline silicon film and form lead.Doping process wherein can select for use mask plate photoetching technique, two bundle coherent laser beams optical interference photoetching technique, or utilize the nano impression process.
Further, in making the method that forms polycrystalline silicon semiconductor film, adopt the transverse area of large-area grating manufacturing technology or electron beam direct writing in patterning semiconductive thin film and doping to form an active region, direction of current flow strides across transverse area; Simultaneously, form regions and source, direction of current flow is the zone transversely; Depositing insulating layer forms grid then at the active region top on active region; Above-mentioned gate pattern covers the whole active channels that are used to form source electrode and drain region except the thin-film transistor two ends; The photoetching insulating barrier forms source electrode and drain electrode electrically contacts.Grid forms the back source electrode or the drain region does not need extra doping or activation.
Below each section meeting provide experimental result and analyze.
Experimental result
TFT with structure that preceding text design is created and is tested.Being used for demonstration, is the thick solid-phase crystallization polysilicon of 100nm as the material of active layer.Gate medium is the thick low temperature LPCVD precipitated silica of 70nm.
The device transmission characteristic of using first embodiment and second embodiment is respectively like Fig. 7 and shown in Figure 8.Transistorized size is W=24 μ m, L1=L2=L3=20 μ m, and W and L1-L3 are defined in mark among Fig. 5 and Fig. 6.
Compare for ease, do not have the BG line but equipment with source/drain ion implantation process with same size also shown in Fig. 7 and Fig. 8 as a reference.
The important parameter of equipment performance is listed in following table: (use W/L=24/60, V
Ds=-5V calculates).
| First embodiment | Second embodiment | Parametric device |
| V th(V) | -12.7 | -12.1 | -15.8 |
| SS(mV/dec) | 1600 | 1575 | 2260 |
| ON-OFF?ratio | 5.96E+06 | 4.92E+06 | 5.21E+05 |
| μ FE(cm 2/Vs) | 35.78 | 42.14 | 14.33 |
Can know from above form and to see that the TFT structure and the manufacturing process of institute's utility model have been improved the equipment various aspects of performance.Threshold voltage reduces about 3V, and SS has reduced about 600mV/dec, and the switch ratio has improved an about one magnitude, and field-effect mobility (μ
FE) improved 2.5 to 3 times.
Comprise in each step in specific embodiment some preferably, more detailed implementation step, but be not steps necessary.
What should explain at last is; Above embodiment only limits in order to the technical scheme of description the utility model rather than to the present technique method; The utility model can extend to other modification, variation, application and embodiment on using, and therefore thinks that all such modifications, variation, application, embodiment are in the spirit and teachings of the utility model.
Claims (10)
1. a bridged-grain polycrystalline SiTFT comprises one by low temperature polycrystalline silicon semi-conducting material active layer that constitutes and the glass substrate that supports above-mentioned semi-conducting material, has a plurality of transverse conductance bridges in the active layer; It is characterized in that the position of transverse conductance bridge is perpendicular to required flow of current direction in the channel region, the position of transverse conductance bridge is parallel to required flow of current direction in source/drain region; Source area in the active layer and drain region are configured to symmetry or asymmetric position.
2. transistor as claimed in claim 1 is characterized in that, source area in the active layer and drain region are configured to an asymmetric position, and channel region connects an end of source area and the other end of drain region respectively, and active layer is designed to zigzag.
3. transistor as claimed in claim 1 is characterized in that, active layer is configured to up and down symmetry of source/drain region, and channel region is positioned at that the source/left side, drain region is with connection source/drain region, and active layer is designed to the C font.
4. transistor as claimed in claim 1 is characterized in that, the transverse conductance bridge width in the active layer is less than 10 μ m, and spacing is less than 10 μ m.
5. transistor as claimed in claim 1 is characterized in that, semiconductor is the low temperature polycrystalline silicon material that is formed by laser annealing, solid phase crystallization or metal-induced crystallization.
6. like claim 2 or 3 described transistors, it is characterized in that source/drain and semiconductor regions take shape in a common layer that is made up of low temperature polycrystalline silicon.
7. 6 transistor as claimed in claim is characterized in that, grid covers the half the part that surpasses of above-mentioned active channel, comprises a plurality of high resistance and low-resistance traversed zone, and grid insulate with above-mentioned active channel.
8. transistor as claimed in claim 6 is characterized in that, traversed zone mixes and forms parallel lines.
9. transistor as claimed in claim 7 is characterized in that, the unit are dosage of traversed zone dopant is 1 * 10
14/ cm
2-1 * 10
16/ cm
2
10. transistor as claimed in claim 7 is characterized in that, the unit are dosage of traversed zone dopant is 2 * 10
15/ cm
2-4 * 10
15/ cm
2
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103413898A (en) * | 2013-08-29 | 2013-11-27 | 深圳市华星光电技术有限公司 | Organic light emitting diode anode connecting structure and manufacturing method thereof |
| CN103560152A (en) * | 2013-11-15 | 2014-02-05 | 中国科学院上海微系统与信息技术研究所 | Tunneling field effect transistor of vertical structure and preparation method thereof |
| CN103558254A (en) * | 2013-11-15 | 2014-02-05 | 中国科学院上海微系统与信息技术研究所 | Biosensor based on vertical-structure tunneling field effect transistor and preparation method thereof |
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2011
- 2011-11-30 CN CN 201120488284 patent/CN202405269U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103413898A (en) * | 2013-08-29 | 2013-11-27 | 深圳市华星光电技术有限公司 | Organic light emitting diode anode connecting structure and manufacturing method thereof |
| CN103413898B (en) * | 2013-08-29 | 2015-11-11 | 深圳市华星光电技术有限公司 | Organic Light Emitting Diode anode syndeton and preparation method thereof |
| CN103560152A (en) * | 2013-11-15 | 2014-02-05 | 中国科学院上海微系统与信息技术研究所 | Tunneling field effect transistor of vertical structure and preparation method thereof |
| CN103558254A (en) * | 2013-11-15 | 2014-02-05 | 中国科学院上海微系统与信息技术研究所 | Biosensor based on vertical-structure tunneling field effect transistor and preparation method thereof |
| CN103558254B (en) * | 2013-11-15 | 2015-09-16 | 中国科学院上海微系统与信息技术研究所 | A kind of biology sensor based on vertical stratification tunneling field-effect transistor and preparation method thereof |
| CN103560152B (en) * | 2013-11-15 | 2016-02-17 | 中国科学院上海微系统与信息技术研究所 | Tunneling field-effect transistor of a kind of vertical stratification and preparation method thereof |
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Granted publication date: 20120829 Termination date: 20121130 |