CN202363459U - Gate oxide breakdown antifuse configuration unit structure applicable to FPGA - Google Patents
Gate oxide breakdown antifuse configuration unit structure applicable to FPGA Download PDFInfo
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- CN202363459U CN202363459U CN 201120467472 CN201120467472U CN202363459U CN 202363459 U CN202363459 U CN 202363459U CN 201120467472 CN201120467472 CN 201120467472 CN 201120467472 U CN201120467472 U CN 201120467472U CN 202363459 U CN202363459 U CN 202363459U
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- programming
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- fuse
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Abstract
The utility model relates to a gate oxide breakdown antifuse configuration unit structure applicable to FPGA, comprising an antifuse memory cell based on gate oxide breakdown, a programming selection controlling pipe, a programming isolating pipe, and a switch pipe for controlling the FPGA wiring channel. The configuration unit has its power supply connected to a programming high voltage VPP during the antifuse programming phase. When the FPGA completes configuration, the power supply is connected to the standard voltage VDD. One end of the antifuse memory cell, i.e., the gate is connected to the programming selection controlling pipe, with the other end thereof being grounding. The antifuse data output is connected to the programming isolating pipe. The lower level of the programming isolating pipe is the FPGA wiring channel switch pipe, realizing the control over the layout and wiring of the FPGA circuit. The gate oxide breakdown antifuse configuration unit of the utility model adopts a tetra-pipe gate oxide breakdown antifuse configuration unit structure and is capable of realizing the antifuse configuration unit function of the FPGA over a common CMOS technology line. The gate oxide breakdown antifuse configuration unit structure features high circuit density, low power consumption, nonvolatile programming, high reliability, and long service lifetime.
Description
Technical field
The utility model relates to the grid oxygen breakdown antifuse dispensing unit structure of a kind of FPGA of being applicable to, belongs to CMOS IC design technical field.
Background technology
Grid oxygen punctures the anti-fuse of mode and is different from traditional anti-fuse structures.Traditional anti-fuse structures mainly contains two kinds of the anti-fuse of MTM (Metal to Metal) and the anti-fuses of ONO (Oxide-Nitride-Oxide), and these two kinds of anti-fuse structures need special process, can't adopt the common CMOS technology of existing commercialization to realize.
The biggest advantage that grid oxygen punctures the anti-fuse of mode is to utilize common CMOS processing line just can realize, does not need special technology level and step, and its anti-fuse dielectric is exactly a grid oxygen separator.In the ordinary course of things, the impedance that grid oxygen separator can show T Ω level, isolated gate and the following active area of grid level effectively.When after grid and active area two ends apply a suitable program voltage and electric current, dielectric can form the conduction pathway (＜1k Ω) of a connection electrode, with two electrode conductions, utilizes the conducting of anti-fuse whether to realize information stores.Grid oxygen punctures the anti-fuse of mode as a kind of novel storage organization; Compare with the traditional cmos structure memory; It can provide a kind of high current densities, low-power consumption, the combination of non-volatile programming and high reliability, high life, thereby be widely used in the programmable storage (PROM).
Grid oxygen punctures mode anti-fuse cell reliability and in extensive programmable storage, obtains checking, but is not applied to as yet in the programmable logic array (like FPGA).Because grid oxygen punctures characteristic such as the anti-fuse programming voltage of mode and the classical inverse fuse is distinguished to some extent, must suitable programming structure be set to satisfy application demand based on this anti-fuse programming characteristic.
Summary of the invention
The purpose of the utility model is that grid oxygen breakdown antifuse structure technology is applied in the programmable logic array, has proposed a kind of grid oxygen breakdown antifuse dispensing unit structure of the FPGA of being applicable to circuit.
For realizing above-mentioned purpose; The described grid oxygen breakdown antifuse dispensing unit structure that is applicable to FPGA of the utility model; Comprise a programming isolated tube and a switching tube of controlling the FPGA wiring channel of isolating based on grid oxygen breakdown antifuse memory cell, a programming selection control valve, a protection internal logic and the high pressure of programming; Said based on grid oxygen breakdown antifuse memory cell grid connection programming selection control valve drain electrode and programming isolated tube source electrode, based on the active area ground connection of grid oxygen breakdown antifuse memory cell; Programming selects the control valve grid by the exterior arrangement signal controlling, and programming selects control valve source electrode and substrate to connect supply voltage; Whether programming isolated tube grid is opened by external control signal control; Programming isolated tube substrate connects power supply; The drain electrode of programming isolated tube connects the switching tube grid of control FPGA wiring channel; The switching tube source electrode and the drain electrode of control FPGA wiring channel are connected in the external signal passage, the switching tube substrate ground connection of control FPGA wiring channel.
Said supply voltage is divided into dispensing unit normal working voltage VDD and anti-fuse storage unit program voltage VPP, and VPP>VDD.
The utility model is configured the unit by the configuration code-point of said exterior arrangement signal, and output configuration store information.
Be specially, programming selects control valve whether to be opened by the code stream control that the FPGA configuration software produces, and when the data of configuration code-point were " 1 ", programming selected control valve to close, and is not programmed based on grid oxygen breakdown antifuse memory cell; When the configuration code point data was " 0 ", programming selected control valve to open, and be voltage VPP based on grid oxygen breakdown antifuse memory cell one end this moment; Other end ground connection; After keeping one effective programming period, saidly be programmed based on grid oxygen breakdown antifuse memory cell, realize low resistance connection.
At working stage, that has programmed makes the switching tube grid of said control FPGA wiring channel be connected to ground based on grid oxygen breakdown antifuse memory cell through low resistance connection, keeps the switching tube of said control FPGA wiring channel and closes; That does not programme selects the subthreshold value leakage current characteristic of control valve based on grid oxygen breakdown antifuse memory cell owing to programme, and makes based on grid oxygen breakdown antifuse memory cell gate end and charges to voltage VDD, keeps the switching tube unlatching of said control FPGA wiring channel.
Said programming selects control valve and programming isolated tube to be the high voltage PMOS pipe, and the switching tube of said control FPGA wiring channel is the NMOS pipe.
The utility model has the advantages that: adopt four pipe grid oxygen breakdown antifuse dispensing unit structures; Can on common CMOS processing line, realize the anti-fuse dispensing unit function of FPGA, have the high and low power consumption of current densities, non-volatile programming and high reliability, the characteristics of high life.
Description of drawings
Fig. 1 is the circuit theory diagrams of the utility model grid oxygen breakdown antifuse dispensing unit structure.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is described further.The utility model is considered as follows grid oxygen breakdown antifuse dispensing unit structural design scheme.
1. to the requirement of large-scale F PGA integrated level, reduce dispensing unit structure transistor number as far as possible.
2. along with the increase of FPGA door number; The circuit power consumption problem becomes the restriction main points that circuit scale increases; The utility model utilizes metal-oxide-semiconductor subthreshold value leakage current characteristic that FPGA wiring channel pipe is opened control on the one hand; On the other hand, utilize the low-resistance characteristic of the anti-fuse of having programmed to make FPGA wiring channel tube grid be shorted to GND, overall power is reduced greatly.
3. the idea of the utility model is improved based on the FPGA structure of SRAM dispensing unit; FPGA structure based on the SRAM dispensing unit is controlled by bi-stable latch; And be at least six tubular constructions, there is current path in inside, inevitably causes the increase of circuit power consumption.
As shown in Figure 1; The grid oxygen breakdown antifuse dispensing unit structure (hereinafter to be referred as dispensing unit) of the said FPGA of being applicable to of the utility model comprises: programming isolated tube M2, a switching tube M3 who controls the FPGA wiring channel (to call the wiring switching tube in the following text) who isolates based on grid oxygen breakdown antifuse memory cell FUSE (to call anti-fuse cell in the following text), a programming selection control valve M1, a protection internal logic and the high pressure of programming; Wherein programming selects control valve M1 and programming isolated tube M2 to be the high voltage PMOS pipe, and wiring switching tube M3 is common NMOS pipe.Anti-fuse storage unit FUSE grid connects programming and selects control valve M1 drain electrode and programming isolated tube M2 source electrode, based on the active area ground connection of grid oxygen breakdown antifuse memory cell FUSE; Programming selects control valve M1 grid by the exterior arrangement signal controlling, and programming selects control valve M1 source electrode and substrate to connect supply voltage; Whether programming isolated tube M2 grid is opened by external control signal control; Programming isolated tube M2 substrate connects power supply; Programming isolated tube M2 drain electrode connects the switching tube M3 grid of control FPGA wiring channel; The switching tube M3 source electrode and the drain electrode of control FPGA wiring channel are connected in the external signal passage, the switching tube M3 substrate ground connection of control FPGA wiring channel.
Said supply voltage is divided into dispensing unit normal working voltage VDD and anti-fuse storage unit program voltage VPP, and VPP>VDD.
Programming selects control valve M1 whether to be opened by the code stream control that the FPGA configuration software produces, and when the data of configuration code-point were " 1 ", programming selected control valve M1 to close, and anti-fuse cell FUSE is not programmed; When the configuration code point data was " 0 ", programming selected control valve M1 to open, and this moment, anti-fuse cell FUSE one end was VPP, an end ground connection, and after keeping one effective programming period, anti-fuse cell FUSE is programmed, and realizes low resistance connection.Thereby two different conditions of the corresponding anti-fuse cell FUSE of different configuration code-points, and switch and the shutoff of two inverse state of anti-fuse cell FUSE and then control FPGA wiring switching tube M3 realize the FPGA configuration feature.
This circuit working is divided into two stages, i.e. programming phases and programming back normal work stage.
1. programming phases
Before the programming beginning, programming selects control valve M1 to close, and supply voltage is VPP.When the FPGA configuration data loads, select control valve M1 that the anti-fuse dispensing unit FUSE that will programme is selected by programming, programming selects the grid of control valve M1 to be determined by configuration data; When this dispensing unit need be programmed; Programming selects control valve M1 to open, and the VPP high pressure is passed to anti-fuse cell FUSE grid end, because anti-fuse cell FUSE source ground; Anti-fuse cell FUSE two ends reach the required high-voltage value of programming, after keeping certain programming time, can be programmed.When dispensing unit designs, must isolate with the logic low voltage service area, be necessary to introduce programming isolated tube M2, this isolated tube can bear the programming high pressure, keeps shut in programming phases, isolates program regions and peripheral logical unit.If this dispensing unit need not programmed, programming selects control valve M1 to close, and anti-fuse cell FUSE is not programmed, thereby dispensing unit is realized the storage of two configuration statuses " 0 " and " 1 ".
2. normal work stage after programming
After the configuration of FPGA integrated circuit was accomplished, programming selected control valve M1 to close all the time, and this dispensing unit supply voltage takes back VDD.For the anti-fuse cell FUSE that has programmed; Show as the low-resistance characteristic; The isolated tube M2 that programmes this moment opens, and FPGA wiring switching tube M3 receives ground GND by the anti-fuse cell FUSE that has programmed, thereby this wiring switching tube M3 closes; Output logic low level " 0 ", this logic level is corresponding with the configuration code-point.
For the anti-fuse cell FUSE that is not programmed; Though programming selects control valve M1 to close; But the intrinsic subthreshold value leakage current characteristic of metal-oxide-semiconductor can make anti-fuse cell FUSE grid end charge to VDD, and in normal work stage, programming isolated tube M2 opens; Wiring switching tube M3 also is charged to VDD simultaneously; Wiring switching tube M3 opens, output logic high level " 1 ", and this is not programmed corresponding with these dispensing unit code-point data of previous programming phases for " 1 " makes programming select control valve M1 to close anti-fuse cell FUSE yet.
The described grid oxygen of the utility model breakdown antifuse dispensing unit structure can be applicable in the anti-fuse FPGA circuit; Have technological merits such as simple in structure, that integrated level is high, configuration information is non-volatile, good reliability, low in energy consumption and life-span are long, can satisfy the requirement that IC project is used.
Claims (2)
1. be applicable to the grid oxygen breakdown antifuse dispensing unit structure of FPGA; It is characterized in that: comprise a programming isolated tube (M2) and a switching tube (M3) of controlling the FPGA wiring channel of isolating based on grid oxygen breakdown antifuse memory cell (FUSE), a programming selection control valve (M1), a protection internal logic and the high pressure of programming; Said based on grid oxygen breakdown antifuse memory cell (FUSE) grid connection programming selection control valve (M1) drain electrode and programming isolated tube (M2) source electrode, based on the active area ground connection of grid oxygen breakdown antifuse memory cell (FUSE); Programming selects control valve (M1) grid to connect the exterior arrangement signal, and programming selects control valve (M1) source electrode and substrate to connect supply voltage; Whether programming isolated tube (M2) grid is opened by external control signal control; Programming isolated tube (M2) substrate connects power supply; Programming isolated tube (M2) drain electrode connects switching tube (M3) grid of control FPGA wiring channel; Switching tube (M3) source electrode and the drain electrode of control FPGA wiring channel are connected in the external signal passage, switching tube (M3) the substrate ground connection of control FPGA wiring channel.
2. according to the said grid oxygen breakdown antifuse dispensing unit structure that is applicable to FPGA of claim 1; It is characterized in that; Said programming selects control valve (M1) and programming isolated tube (M2) to be the high voltage PMOS pipe, and the switching tube (M3) of said control FPGA wiring channel is the NMOS pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120467472 CN202363459U (en) | 2011-11-22 | 2011-11-22 | Gate oxide breakdown antifuse configuration unit structure applicable to FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120467472 CN202363459U (en) | 2011-11-22 | 2011-11-22 | Gate oxide breakdown antifuse configuration unit structure applicable to FPGA |
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| CN202363459U true CN202363459U (en) | 2012-08-01 |
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| CN 201120467472 Withdrawn - After Issue CN202363459U (en) | 2011-11-22 | 2011-11-22 | Gate oxide breakdown antifuse configuration unit structure applicable to FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427076A (en) * | 2011-11-22 | 2012-04-25 | 中国电子科技集团公司第五十八研究所 | Gate oxide breakdown antifuse configuration unit structure applied to FPGA |
-
2011
- 2011-11-22 CN CN 201120467472 patent/CN202363459U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427076A (en) * | 2011-11-22 | 2012-04-25 | 中国电子科技集团公司第五十八研究所 | Gate oxide breakdown antifuse configuration unit structure applied to FPGA |
| CN102427076B (en) * | 2011-11-22 | 2013-06-26 | 中国电子科技集团公司第五十八研究所 | Gate oxide breakdown antifuse configuration unit structure applied to FPGA |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120801 Effective date of abandoning: 20130626 |
|
| RGAV | Abandon patent right to avoid regrant |