CN202363441U - Improved stacking type wafer packaging structure - Google Patents

Improved stacking type wafer packaging structure Download PDF

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Publication number
CN202363441U
CN202363441U CN2011204880290U CN201120488029U CN202363441U CN 202363441 U CN202363441 U CN 202363441U CN 2011204880290 U CN2011204880290 U CN 2011204880290U CN 201120488029 U CN201120488029 U CN 201120488029U CN 202363441 U CN202363441 U CN 202363441U
Authority
CN
China
Prior art keywords
wafer
adhesion layer
thermosetting adhesion
welding
base plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2011204880290U
Other languages
Chinese (zh)
Inventor
彭兰兰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN2011204880290U priority Critical patent/CN202363441U/en
Application granted granted Critical
Publication of CN202363441U publication Critical patent/CN202363441U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present utility model discloses an improved stacking type wafer packaging structure. The structure comprises a line substrate, a two-phase thermosetting adhesion layer, a first wafer, a second wafer and a glue body, the two-phase thermosetting adhesion layer is glued on the middle part of the upper surface of the first wafer, the upper surface of the two-phase thermosetting adhesion layer is provided with the second wafer, the two-phase thermosetting adhesion layer also comprises an annular protruding part, and the periphery of two end faces of the first wafer is surrounded by the annular protruding part; the upper surface of the second wafer is provided with a plurality of second welding pads, and the second welding pads are electrically connected on the upper surface of the line substrate through a plurality of welding wires; the lower surface of the first wafer is provided with a plurality of first welding pads, and the first welding pads are electrically connected with the line substrate through a plurality of welding flux protruding blocks; and the first wafer, the second wafer, the welding wires and the welding flux protruding blocks are wrapped by the glue body. The structure is simple in structure and reasonable in design, and has wide market value and huge market potential.

Description

The stacking type wafer packaging structure of improvement
Technical field
The utility model relates to a kind of semiconductor element, especially a kind of stacking type wafer packaging structure that solves the improvement of adhesion layer pollution load of overflow bonding wire electric connection regional issue.
Background technology
Wafer in the integrated circuit is by steps such as wafer manufacturing, circuit design, light shield manufacture and cutting crystal wafers and accomplish; Each cuts formed wafer by wafer; After electrically connecting, with colloidal materials wafer is coated again via weld pad on the wafer and outside signal; The purpose of its encapsulation is to prevent that wafer from receiving the influence of moisture, heat, noise, and provide wafer and external circuit between the media that electrically connects.
Existing encapsulating structure comprises wafer; Circuit base plate; Adhesion layer, many bonding wires and colloid; Wafer is engaged on the circuit base plate through the adhesion layer that has epoxy resin to process, and a plurality of weld pads on the upper wafer surface electrically connect colloid coating wafer, adhesion layer and those bonding wires through a plurality of bonding wires and circuit base plate.Because adhesion layer has flowability, the pressurization of adhesion layer makes other zones of adhesion layer overflow to circuit base plate easily, even contamination line base board and the zone that those bonding wires electrically connect, and causes and reduces the yield that encapsulates.
Therefore, prior art awaits improving and improving.
Summary of the invention
For overcoming the problems referred to above that exist in the prior art, the purpose of this invention is to provide a kind of stacking type wafer packaging structure that adhesion layer pollution load of overflow bonding wire electrically connects the improvement of regional issue that solves.
For realizing above-mentioned purpose; The utility model is realized through following technological means: a kind of stacking type wafer packaging structure; Comprise circuit base plate, two stage thermosetting adhesion layers, first wafer, second wafer and colloid; The upper surface middle part of described first wafer is sticked together has two stage thermosetting adhesion layers; The upper surface of this two stages thermosetting adhesion layer is provided with second wafer, and described two stage thermosetting adhesion layers also have an annular relief, and this annular relief is surrounded on the both ends of the surface periphery of first wafer; A plurality of second weld pads that the upper surface of described second wafer is provided with electrically connect the upper surface of circuit base plate through many bonding wires; The lower surface of described first wafer also is provided with a plurality of first weld pads, and these a plurality of first weld pads electrically connect through a plurality of solder projections and circuit base plate; Described colloid coats first wafer, second wafer, those bonding wires and those solder projections.
Compared with prior art; The beneficial effect of the utility model is: because two stage thermosetting adhesion layers of the chip package structure of the utility model can be cured as the thermosetting adhesion layer of solid-state or gel state in advance; Therefore carry out follow-up when wafer is pressure bonded to circuit base plate or wafer is pressure bonded to the fabrication steps of another wafer; Two stage thermosetting adhesion layers can overflow to circuit base plate or other zones of another wafer, and then the zone that electrically connects of contamination line base board or another wafer and bonding wire.The utility model is simple in structure, reasonable in design, has market value and huge market potential widely.
Description of drawings
Accompanying drawing 1 is the structural representation of the stacking type wafer packaging structure of the utility model improvement.
Each label is respectively among the figure: (1) circuit base plate, (2) two stage thermosetting adhesion layers, (3) first wafers, (4) second wafers; (5) colloid, (6) first weld pads, (7) second weld pads; (8) bonding wire, (9) solder projection, (10) annular relief.
Embodiment
Below in conjunction with accompanying drawing the utility model is done further to specify:
Referring to Fig. 1, the stacking type wafer packaging structure of a kind of improvement of the utility model comprises circuit base plate 1; Two stage thermosetting adhesion layers, 2, the first wafers 3, second wafer 4 and colloid 5, the upper surface middle part of described first wafer 3 is sticked together has two stage thermosetting adhesion layers 2; The upper surface of this two stages thermosetting adhesion layer 2 is provided with second wafer 4;, described two stage thermosetting adhesion layers 2 also have an annular relief 10, and this annular relief 10 is surrounded on the both ends of the surface periphery of first wafer 3; A plurality of second weld pads 7 that the upper surface of described second wafer 4 is provided with electrically connect the upper surface of circuit base plate 1 through many bonding wires 8; The lower surface of described first wafer 3 also is provided with a plurality of first weld pads 6, and these a plurality of first weld pads 6 electrically connect through a plurality of solder projections 9 and circuit base plate 1; Described colloid 5 coats first wafer 3, second wafer 4, those bonding wires 8 and those solder projections 9.
The above; It only is the preferred embodiment of the utility model; Be not that the utility model is done any pro forma restriction; Any professional and technical personnel of being familiar with possibly utilize the technology contents of above-mentioned announcement to change or be modified to the equivalent embodiment of equivalent variations; But all the utility model technical scheme contents that do not break away from, all still belong in the scope of the utility model technical scheme any simple modification, equivalent variations and modification that above embodiment did according to the technical spirit of the utility model.

Claims (1)

1. stacking type wafer packaging structure; Comprise circuit base plate, two stage thermosetting adhesion layers, first wafer, second wafer and colloid; It is characterized in that: the upper surface middle part of described first wafer is sticked together has two stage thermosetting adhesion layers; The upper surface of this two stages thermosetting adhesion layer is provided with second wafer, and described two stage thermosetting adhesion layers also have an annular relief, and this annular relief is surrounded on the both ends of the surface periphery of first wafer; A plurality of second weld pads that the upper surface of described second wafer is provided with electrically connect the upper surface of circuit base plate through many bonding wires; The lower surface of described first wafer also is provided with a plurality of first weld pads, and these a plurality of first weld pads electrically connect through a plurality of solder projections and circuit base plate; Described colloid coats first wafer, second wafer, those bonding wires and those solder projections.
CN2011204880290U 2011-11-30 2011-11-30 Improved stacking type wafer packaging structure Expired - Fee Related CN202363441U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011204880290U CN202363441U (en) 2011-11-30 2011-11-30 Improved stacking type wafer packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011204880290U CN202363441U (en) 2011-11-30 2011-11-30 Improved stacking type wafer packaging structure

Publications (1)

Publication Number Publication Date
CN202363441U true CN202363441U (en) 2012-08-01

Family

ID=46574604

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011204880290U Expired - Fee Related CN202363441U (en) 2011-11-30 2011-11-30 Improved stacking type wafer packaging structure

Country Status (1)

Country Link
CN (1) CN202363441U (en)

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120801

Termination date: 20121130