CN202334549U - Three-dimensional switching chaotic circuit - Google Patents
Three-dimensional switching chaotic circuit Download PDFInfo
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- CN202334549U CN202334549U CN 201120437545 CN201120437545U CN202334549U CN 202334549 U CN202334549 U CN 202334549U CN 201120437545 CN201120437545 CN 201120437545 CN 201120437545 U CN201120437545 U CN 201120437545U CN 202334549 U CN202334549 U CN 202334549U
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Abstract
The utility model relates to a three-dimensional switching chaotic circuit. The three-dimensional switching chaotic circuit comprises an integrated operational amplifier U1, an integrated operational amplifier U2, an integrated operational amplifier U3 and a multiplier U4, a multiplierU5, a switch S1 and a switch S2, wherein the integrated operational amplifiers realize addition, antiphase and integrating functions and realize a linear part in a system; the multipliers realize a multiplication function and realize a non-linear part of the system, and the switches realize a switching function; the multiplier U4 is connected with the integrated operational amplifier U2, the multiplier U5 is connected with the integrated operational amplifier U3, and the switch S1 and the switch S2 are connected with the multiplier U5; and manual switching of two or three chaotic systems can be realized, and randomization of the system is improved.
Description
Technical field
The utility model relates to a kind of chaos circuit, particularly a kind of three-dimensional chaos circuit that switches.
Background technology
For improving the security performance of communication system, utilize multisystem switching chaos to carry out secure communication and can effectively improve confidentiality, but can not carrying out two or more systems, existing chaos system switches, this is the weak point of prior art.
Summary of the invention
The utility model will be dealt with problems and provided a kind of three-dimensional chaos circuit that switches.The technical scheme that the utility model adopts is: be made up of integrated operational amplifier U1, integrated operational amplifier U2, integrated operational amplifier U3 and multiplier U4, multiplier U5 and switch S 1, switch S 2; Integrated operational amplifier is realized addition, anti-phase, integrating function, the linear segment in the realization system; Multiplier is realized multiplication function; Non-linear partial in the realization system, switch is realized handoff functionality, multiplier U4 connects integrated operational amplifier U2; Multiplier U5 connects integrated operational amplifier U3, and switch S 1 is connected multiplier U5 with switch S 2.
The 1st pin of said integrated operational amplifier U1 joins through resistance R x and the 2nd pin, and the 2nd pin joins through potentiometer R11 and the 14th pin, and the 7th pin through potentiometer R12 and integrated operational amplifier U2 joins; The 3rd pin, 5 pins, 10 pins, 12 pin ground connection, the 4th pin meets VCC, and the 6th pin joins through resistance R 1 and the 1st pin; Join through capacitor C 1 and the 7th pin; The 8th pin joins through resistance R 25 and the 9th pin, and the 9th pin joins through the 7th pin of resistance R 24 with integrated operational amplifier U2, and the 11st pin meets VEE; The 13rd pin joins through resistance R 13 and the 7th pin, joins through resistance R 14 and the 14th pin.
The 1st pin of said integrated operational amplifier U2 joins through resistance R y and the 2nd pin, and the 7th pin through potentiometer R22 and integrated operational amplifier U1 joins, and joins through potentiometer R23 and the 7th pin; The 3rd pin, 5 pins, 10 pins, 12 pin ground connection, the 4th pin meets VCC, and the 6th pin joins through resistance R 2 and the 1st pin; Join through capacitor C 2 and the 7th pin; The 8th pin joins through capacitor C 3 and the 9th pin, and the 9th pin joins through the 1st pin of resistance R 3 with integrated operational amplifier U3, and the 11st pin meets VEE; The 13rd pin joins through resistance R 33 and the 8th pin, joins through resistance R 34 and the 14th pin.
The 1st pin of said integrated operational amplifier U3 joins through resistance R z and the 2nd pin; The 2nd pin joins through the 14th pin of potentiometer R32 and integrated operational amplifier U2, the 3rd pin ground connection; The 4th pin meets VCC; The 1st pin that the 5th pin, 6 pins, 7 pins, 8 pins, 9 pins, 10 pins, 12 pins, 13 pins, 14 pin ground connection, the 11st pin meet the said integrated operational amplifier U3 of VEE joins through resistance R z and the 2nd pin; The 2nd pin joins through the 14th pin of potentiometer R32 and integrated operational amplifier U2, the 3rd pin ground connection; The 4th pin meets VCC; The 5th pin, 6 pins, 7 pins, 8 pins, 9 pins, 10 pins, 12 pins, 13 pins, 14 pin ground connection, the 11st pin meets VEE.
The 1st pin of said multiplier U4 and the 7th pin of integrated operational amplifier U1 join, the 2nd pin, 4 pins, 6 pin ground connection, and the 8th pin of the 3rd pin and integrated operational amplifier U2 joins; The 5th pin meets VEE; The 7th pin joins through the 2nd pin of potentiometer R21 and integrated operational amplifier U2, and the 8th pin connects the 1st pin of the said multiplier U4 of VCC and the 7th pin of integrated operational amplifier U1 joins, the 2nd pin, 4 pins, 6 pin ground connection; The 8th pin of the 3rd pin and integrated operational amplifier U2 joins; The 5th pin meets VEE, and the 7th pin joins through the 2nd pin of potentiometer R21 and integrated operational amplifier U2, and the 8th pin meets VCC.
The 1st pin of said multiplier U5 and the 2nd pin of switch S 1 join; The 2nd pin, the 4th pin, the 6th pin ground connection; The 2nd pin of the 3rd pin and switch S 2 joins; The 5th pin meets VEE; The 7th pin joins through the 2nd pin of potentiometer R31 and integrated operational amplifier U3; The 8th pin meets VCC.
The 1st pin of said switch S 1 and the 7th pin of integrated operational amplifier U1 join, and 1 pin of the 2nd pin and multiplier U5 joins, and the 7th pin of the 3rd pin and integrated operational amplifier U2 joins.
The 1st pin of said switch S 2 and the 7th pin of integrated operational amplifier U1 join, and 3 pins of the 2nd pin and integrated operational amplifier U5 join, and the 7th pin of the 3rd pin and integrated operational amplifier U2 joins.
Beneficial effect: solve the deficiency of prior art, can in two or more chaos systems, switch.
Description of drawings
Fig. 1 is the circuit structure diagram of the utility model.
Fig. 2 is the circuit theory diagrams of the utility model.
Embodiment
Below in conjunction with accompanying drawing the utility model is made detailed description further.
Referring to Fig. 1, the three-dimensional chaos circuit that switches is made up of integrated operational amplifier U1, integrated operational amplifier U2, integrated operational amplifier U3 and multiplier U4, multiplier U5 and switch S 1, switch S 2; Integrated operational amplifier is realized addition, anti-phase, integrating function, the linear segment in the realization system; Multiplier is realized multiplication function; Non-linear partial in the realization system, switch is realized handoff functionality, multiplier U4 connects integrated operational amplifier U2; Multiplier U5 connects integrated operational amplifier U3, and switch S 1 is connected multiplier U5 with switch S 2.
Referring to Fig. 2, the 1st pin of said integrated operational amplifier U1 joins through resistance R x and the 2nd pin, and the 2nd pin joins through potentiometer R11 and the 14th pin; The 7th pin through potentiometer R12 and integrated operational amplifier U2 joins; The 3rd pin, 5 pins, 10 pins, 12 pin ground connection, the 4th pin meets VCC, and the 6th pin joins through resistance R 1 and the 1st pin; Join through capacitor C 1 and the 7th pin; The 8th pin joins through resistance R 25 and the 9th pin, and the 9th pin joins through the 7th pin of resistance R 24 with integrated operational amplifier U2, and the 11st pin meets VEE; The 13rd pin joins through resistance R 13 and the 7th pin, joins through resistance R 14 and the 14th pin.
The 1st pin of said integrated operational amplifier U2 joins through resistance R y and the 2nd pin, and the 7th pin through potentiometer R22 and integrated operational amplifier U1 joins, and joins through potentiometer R23 and the 7th pin; The 3rd pin, 5 pins, 10 pins, 12 pin ground connection, the 4th pin meets VCC, and the 6th pin joins through resistance R 2 and the 1st pin; Join through capacitor C 2 and the 7th pin; The 8th pin joins through capacitor C 3 and the 9th pin, and the 9th pin joins through the 1st pin of resistance R 3 with integrated operational amplifier U3, and the 11st pin meets VEE; The 13rd pin joins through resistance R 33 and the 8th pin, joins through resistance R 34 and the 14th pin.
The 1st pin of said integrated operational amplifier U3 joins through resistance R z and the 2nd pin; The 2nd pin joins through the 14th pin of potentiometer R32 and integrated operational amplifier U2, the 3rd pin ground connection; The 4th pin meets VCC; The 1st pin that the 5th pin, 6 pins, 7 pins, 8 pins, 9 pins, 10 pins, 12 pins, 13 pins, 14 pin ground connection, the 11st pin meet the said integrated operational amplifier U3 of VEE joins through resistance R z and the 2nd pin; The 2nd pin joins through the 14th pin of potentiometer R32 and integrated operational amplifier U2, the 3rd pin ground connection; The 4th pin meets VCC; The 5th pin, 6 pins, 7 pins, 8 pins, 9 pins, 10 pins, 12 pins, 13 pins, 14 pin ground connection, the 11st pin meets VEE.
The 1st pin of said multiplier U4 and the 7th pin of integrated operational amplifier U1 join, the 2nd pin, 4 pins, 6 pin ground connection, and the 8th pin of the 3rd pin and integrated operational amplifier U2 joins; The 5th pin meets VEE; The 7th pin joins through the 2nd pin of potentiometer R21 and integrated operational amplifier U2, and the 8th pin connects the 1st pin of the said multiplier U4 of VCC and the 7th pin of integrated operational amplifier U1 joins, the 2nd pin, 4 pins, 6 pin ground connection; The 8th pin of the 3rd pin and integrated operational amplifier U2 joins; The 5th pin meets VEE, and the 7th pin joins through the 2nd pin of potentiometer R21 and integrated operational amplifier U2, and the 8th pin meets VCC.
The 1st pin of said multiplier U5 and the 2nd pin of switch S 1 join; The 2nd pin, the 4th pin, the 6th pin ground connection; The 2nd pin of the 3rd pin and switch S 2 joins; The 5th pin meets VEE; The 7th pin joins through the 2nd pin of potentiometer R31 and integrated operational amplifier U3; The 8th pin meets VCC.
The 1st pin of said switch S 1 and the 7th pin of integrated operational amplifier U1 join, and 1 pin of the 2nd pin and multiplier U5 joins, and the 7th pin of the 3rd pin and integrated operational amplifier U2 joins.
The 1st pin of said switch S 2 and the 7th pin of integrated operational amplifier U1 join, and 3 pins of the 2nd pin and integrated operational amplifier U5 join, and the 7th pin of the 3rd pin and integrated operational amplifier U2 joins.
Claims (8)
1. the three-dimensional chaos circuit that switches, it is characterized in that: be made up of integrated operational amplifier U1, integrated operational amplifier U2, integrated operational amplifier U3 and multiplier U4, multiplier U5 and switch S 1, switch S 2, integrated operational amplifier is realized addition, anti-phase; Integrating function; Linear segment in the realization system, multiplier is realized multiplication function, the non-linear partial in the realization system; Switch is realized handoff functionality; Multiplier U4 connects integrated operational amplifier U2, and multiplier U5 connects integrated operational amplifier U3, and switch S 1 is connected multiplier U5 with switch S 2.
2. according to the said three-dimensional chaos circuit that switches of claim 1, it is characterized in that: the 1st pin of said integrated operational amplifier U1 joins through resistance R x and the 2nd pin, and the 2nd pin joins through potentiometer R11 and the 14th pin; The 7th pin through potentiometer R12 and integrated operational amplifier U2 joins; The 3rd pin, 5 pins, 10 pins, 12 pin ground connection, the 4th pin meets VCC, and the 6th pin joins through resistance R 1 and the 1st pin; Join through capacitor C 1 and the 7th pin; The 8th pin joins through resistance R 25 and the 9th pin, and the 9th pin joins through the 7th pin of resistance R 24 with integrated operational amplifier U2, and the 11st pin meets VEE; The 13rd pin joins through resistance R 13 and the 7th pin, joins through resistance R 14 and the 14th pin.
3. according to the said three-dimensional chaos circuit that switches of claim 1, it is characterized in that: the 1st pin of said integrated operational amplifier U2 joins through resistance R y and the 2nd pin, and the 7th pin through potentiometer R22 and integrated operational amplifier U1 joins; Join through potentiometer R23 and the 7th pin; The 3rd pin, 5 pins, 10 pins, 12 pin ground connection, the 4th pin meets VCC, and the 6th pin joins through resistance R 2 and the 1st pin; Join through capacitor C 2 and the 7th pin; The 8th pin joins through capacitor C 3 and the 9th pin, and the 9th pin joins through the 1st pin of resistance R 3 with integrated operational amplifier U3, and the 11st pin meets VEE; The 13rd pin joins through resistance R 33 and the 8th pin, joins through resistance R 34 and the 14th pin.
4. according to the said three-dimensional chaos circuit that switches of claim 1, it is characterized in that: the 1st pin of said integrated operational amplifier U3 joins through resistance R z and the 2nd pin; The 2nd pin joins through the 14th pin of potentiometer R32 and integrated operational amplifier U2, the 3rd pin ground connection; The 4th pin meets VCC; The 5th pin, 6 pins, 7 pins, 8 pins, 9 pins, 10 pins, 12 pins, 13 pins, 14 pin ground connection, the 11st pin meets VEE.
5. according to the said three-dimensional chaos circuit that switches of claim 1; It is characterized in that: the 1st pin of said multiplier U4 and the 7th pin of integrated operational amplifier U1 join; The 2nd pin, 4 pins, 6 pin ground connection, the 8th pin of the 3rd pin and integrated operational amplifier U2 joins, and the 5th pin meets VEE; The 7th pin joins through the 2nd pin of potentiometer R21 and integrated operational amplifier U2, and the 8th pin meets VCC.
6. according to the said three-dimensional chaos circuit that switches of claim 1, it is characterized in that: the 1st pin of said multiplier U5 and the 2nd pin of switch S 1 join; The 2nd pin, the 4th pin, the 6th pin ground connection; The 2nd pin of the 3rd pin and switch S 2 joins; The 5th pin meets VEE; The 7th pin joins through the 2nd pin of potentiometer R31 and integrated operational amplifier U3; The 8th pin meets VCC.
7. according to the said three-dimensional chaos circuit that switches of claim 1; It is characterized in that: the 1st pin of said switch S 1 and the 7th pin of integrated operational amplifier U1 join; 1 pin of the 2nd pin and multiplier U5 joins, and the 7th pin of the 3rd pin and integrated operational amplifier U2 joins.
8. according to the said three-dimensional chaos circuit that switches of claim 1; It is characterized in that: the 1st pin of said switch S 2 and the 7th pin of integrated operational amplifier U1 join; 3 pins of the 2nd pin and integrated operational amplifier U5 join, and the 7th pin of the 3rd pin and integrated operational amplifier U2 joins.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN 201120437545 CN202334549U (en) | 2011-11-08 | 2011-11-08 | Three-dimensional switching chaotic circuit |
Applications Claiming Priority (1)
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CN 201120437545 CN202334549U (en) | 2011-11-08 | 2011-11-08 | Three-dimensional switching chaotic circuit |
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CN202334549U true CN202334549U (en) | 2012-07-11 |
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CN 201120437545 Expired - Fee Related CN202334549U (en) | 2011-11-08 | 2011-11-08 | Three-dimensional switching chaotic circuit |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108347329A (en) * | 2018-02-28 | 2018-07-31 | 沈阳建筑大学 | It is a kind of complexity switching law under three-dimensional switching chaotic circuit |
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2011
- 2011-11-08 CN CN 201120437545 patent/CN202334549U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108347329A (en) * | 2018-02-28 | 2018-07-31 | 沈阳建筑大学 | It is a kind of complexity switching law under three-dimensional switching chaotic circuit |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120711 Termination date: 20121108 |