CN204272149U - A kind of five rank amplitude limit type Jerk hyperchaotic circuits - Google Patents
A kind of five rank amplitude limit type Jerk hyperchaotic circuits Download PDFInfo
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- CN204272149U CN204272149U CN201420802445.7U CN201420802445U CN204272149U CN 204272149 U CN204272149 U CN 204272149U CN 201420802445 U CN201420802445 U CN 201420802445U CN 204272149 U CN204272149 U CN 204272149U
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Abstract
A kind of five rank amplitude limit type Jerk hyperchaotic circuits, its first, second, third and fourth, five operational amplifier A
1, A
2, A
3, A
4, A
5form linear inverting integrator, output is respectively chaotic signal output X
1, X
2, X
3, X
4, X
5; 7th operational amplifier A 7 forms non-linear inverting amplifier; Inverting integrator A
1with inverting integrator A
2connect; Inverting integrator A
2respectively with inverting integrator A
3, amplifier A
6connect; Inverting integrator A
3respectively with inverting integrator A
4, non-linear inverting amplifier A
7connect; Inverting integrator A
4with inverting integrator A
5connect; Inverting integrator A
5with inverting amplifier A
8connect; The utility model is chaos circuit, can export the various waveforms of five rank amplitude limit type Jerk hyperchaoses, phasor and chaos and develop curve, can form chaotic secret communication system.
Description
Technical field the utility model belongs to nonlinear circuit, often claims chaos circuit, is specifically related to a kind of five rank amplitude limit type Jerk hyperchaotic circuits.
Background technology Jerk chaos circuit is a pith of nonlinear circuit, its patent No. is the patent " chaotic circuit of cascade reversed-phase integrator " of ZL200810233851.5, wherein the 4th circuit is the non-linear Jerk circuit of a kind of three rank amplitude limit, 3 oscillograms and 3 phasors can only be exported, chaotic characteristic is simple, the chaotic secret communication circuit security performance formed with this circuit is more weak, is the deficiency of existing Jerk circuit engineering.
Utility model content the purpose of this utility model is the deficiency solved the problem, a kind of one five rank amplitude limit type Jerk hyperchaotic circuit of eight grades of operational amplifiers composition is provided, 5 oscillograms and 10 phasors can be exported, can five rank amplitude limit type Jerk hyperchaos signals of stable output, the chaotic communication circuit of stronger security performance can be formed based on this circuit.
The utility model solves the technical scheme that its technical problem adopts: a kind of five rank amplitude limit type Jerk hyperchaotic circuits, is made up of, wherein: the first operational amplifier (A eight operational amplifiers and resistance and electric capacity
1) inverting input and the 3rd resistance (R
3), the 4th resistance (R
4), the 5th resistance (R
5) connect, in-phase input end ground connection, be connected the first electric capacity (C in parallel between inverting input with output
1) and the 6th resistance (R
6), output and the 7th resistance (R
7) connect, output is X
1output; Second operational amplifier (A
2) inverting input and the 7th resistance (R
7), the 8th resistance (R
8) connect, in-phase input end ground connection, connects the second electric capacity (C between inverting input and output
2), output and the 9th resistance (R
9), the 12 resistance (R
12) connect, output is X
2output; 3rd operational amplifier (A
3) inverting input and the 9th resistance (R
9) connect, in-phase input end ground connection, connects the 3rd electric capacity (C between inverting input and output
3), output and the first resistance (R
1), the tenth resistance (R
10) connect, output is X
3output; Four-operational amplifier (A
4) inverting input and the tenth resistance (R
10), the 13 resistance (R
13) connect, in-phase input end ground connection, connects the 4th electric capacity (C between inverting input and output
4), output and the 8th resistance (R
8), the 14 resistance (R
14) connect, output is X
4output; 5th operational amplifier (A
5) inverting input and the 14 resistance (R
14) connect, in-phase input end ground connection, be connected the 5th electric capacity (C in parallel between inverting input with output
5) and the 15 resistance (R
15), output and the 16 resistance (R
16) connect, output is X
5output; 6th operational amplifier (A
6) inverting input and the 12 resistance (R
12) connect, in-phase input end ground connection, is connected the 11 resistance (R between inverting input with output
11), output and the 5th resistance (R
5) connect; 7th operational amplifier (A
7) inverting input and the first resistance (R
1) connect, in-phase input end ground connection, is connected the second resistance (R between inverting input with output
2), output and the 4th resistance (R
4) connect; 8th operational amplifier (A
8) inverting input and the 16 resistance (R
16) connect, in-phase input end ground connection, is connected the 17 resistance (R between inverting input with output
17), output and the 13 resistance (R
13) connect.
Described 4th resistance (R
4) be variable resistor, the various curves that the chaos can observing a kind of five rank amplitude limit type Jerk hyperchaotic circuits develops.
The beneficial effects of the utility model are: can export X
1, X
2, X
3, X
4with X
5five chaotic waves signals and X
1-X
2, X
1-X
3, X
1-X
4, X
1-X
5, X
2-X
3, X
2-X
4, X
2-X
5, X
3-X
4, X
3-X
5, X
4-X
5ten chaos phasors; Above-mentioned various chaotic signal can be shown on oscilloscope; By some specific electrical resistance such as the 4th resistance (R
4) replaced by variable resistor after, the chaotic characteristic of the above various chaotic signal can be changed, the various curves that the chaos that can show five rank amplitude limit type Jerk hyperchaotic circuits on oscilloscope develops, can also carry out other various experiment of five rank amplitude limit type Jerk hyperchaotic circuits.The utility model is applicable to university's chaos education of science, experimental teaching and demonstration, scientific popularization experimental demonstration etc.
Description of drawings 1 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit schematic diagrams.
Fig. 2 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
1-X
2export phasor.
Fig. 3 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
1-X
3export phasor.
Fig. 4 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
1-X
4export phasor.
Fig. 5 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
1-X
5export phasor.
Fig. 6 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
2-X
3export phasor.
Fig. 7 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
2-X
4export phasor.
Fig. 8 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
2-X
5export phasor.
Fig. 9 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
3-X
4export phasor.
Figure 10 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
3-X
5export phasor.
Figure 11 is a kind of five rank amplitude limit type Jerk hyperchaotic circuit X
4-X
5export phasor.
Embodiment is with reference to accompanying drawing 1, and the utility model embodiment is made up of eight operational amplifiers and resistance and electric capacity, wherein: the first operational amplifier A 1 inverting input and the 3rd resistance R
3, the 4th resistance R
4, the 5th resistance R
5connect, in-phase input end ground connection, between inverting input with output, be connected the first electric capacity C in parallel
1with the 6th resistance R
6, output and the 7th resistance R
7connect, output is X
1output; Second operational amplifier A
2inverting input and the 7th resistance R
7, the 8th resistance R
8connect, in-phase input end ground connection, connects the second electric capacity C between inverting input and output
2, output and the 9th resistance R
9, the 12 resistance R
12connect, output is X
2output; 3rd operational amplifier A
3inverting input and the 9th resistance R
9connect, in-phase input end ground connection, connects the 3rd electric capacity C between inverting input and output
3, output and the first resistance R
1, the tenth resistance R
10connect, output is X
3output; Four-operational amplifier A
4inverting input and the tenth resistance R
10, the 13 resistance R
13connect, in-phase input end ground connection, connects the 4th electric capacity C between inverting input and output
4, output and the 8th resistance R
8, the 14 resistance R
14connect, output is X
4output; 5th operational amplifier A
5inverting input and the 14 resistance R
14connect, in-phase input end ground connection, between inverting input with output, be connected the 5th electric capacity C in parallel
5with the 15 resistance R
15, output and the 16 resistance R
16connect, output is X
5output; 6th operational amplifier A
6inverting input and the 12 resistance R
12connect, in-phase input end ground connection, is connected the 11 resistance R between inverting input with output
11, output and the 5th resistance R
5connect; 7th operational amplifier A
7inverting input and the first resistance R
1connect, in-phase input end ground connection, is connected the second resistance R between inverting input with output
2, output and the 4th resistance R
4connect; 8th operational amplifier A
8inverting input and the 16 resistance R
16connect, in-phase input end ground connection, is connected the 17 resistance R between inverting input with output
17, output and the 13 resistance R
13connect.
By X in Fig. 1
1output, X
2output, X
3output, X
4output and X
5output is connected to oscilloscope signal input or computer concerned interface, can show X
1, X
2, X
3, X
4with X
5waveform, use oscillographic phasor mode to observe, X
1-X
2output phasor signal as shown in Figure 2, X
1-X
3output phasor signal as shown in Figure 3, X
1-X
4output phasor signal as shown in Figure 4, X
1-X
5output phasor signal as shown in Figure 5, X
2-X
3output phasor signal as shown in Figure 6, X
2-X
4output phasor signal as shown in Figure 7, X
2-X
5output phasor signal as shown in Figure 8, X
3-X
4output phasor signal as shown in Figure 9, X
3-X
5output phasor signal as shown in Figure 10, X
4-X
5output phasor signal as shown in figure 11.By Fig. 2 to Figure 11, demonstrate validity of the present utility model.If the 4th resistance R
4being replaced by variable resistor, continuously change resistance value, the various curves that chaos develops can be observed, by two identical circuit through suitably connecting, the various experiments such as the synchronous of a kind of five rank amplitude limit type Jerk hyperchaotic circuits and chaotic secret communication can be carried out.
The component parameter of the utility model embodiment is as follows: A
1~ A
8model is TL082 or TL084, R
1=R
5=R
7=R
9=R
10=R
11=R
12=R
16=R
17=10k Ω, R
2=120k Ω, R
3=3.3k Ω, R
4=36k Ω (variable resistor), R
6=21k Ω, R
8=70k Ω, R
13=20k Ω, R
14=30k Ω, R
15=60k Ω, C
1~ C
5=0.01 μ F.
Claims (2)
1. five rank amplitude limit type Jerk hyperchaotic circuits, are made up of eight operational amplifiers and resistance and electric capacity, it is characterized in that: described eight operational amplifiers, wherein: the first operational amplifier (A
1) inverting input and the 3rd resistance (R
3), the 4th resistance (R
4), the 5th resistance (R
5) connect, in-phase input end ground connection, be connected the first electric capacity (C in parallel between inverting input with output
1) and the 6th resistance (R
6), output and the 7th resistance (R
7) connect, output is X
1output; Second operational amplifier (A
2) inverting input and the 7th resistance (R
7), the 8th resistance (R
8) connect, in-phase input end ground connection, connects the second electric capacity (C between inverting input and output
2), output and the 9th resistance (R9), the 12 resistance (R
12) connect, output is X
2output; 3rd operational amplifier (A
3) inverting input and the 9th resistance (R
9) connect, in-phase input end ground connection, connects the 3rd electric capacity (C between inverting input and output
3), output and the first resistance (R
1), the tenth resistance (R
10) connect, output is X
3output; Four-operational amplifier (A
4) inverting input and the tenth resistance (R
10), the 13 resistance (R
13) connect, in-phase input end ground connection, connects the 4th electric capacity (C between inverting input and output
4), output and the 8th resistance (R
8), the 14 resistance (R
14) connect, output is X
4output; 5th operational amplifier (A
5) inverting input and the 14 resistance (R
14) connect, in-phase input end ground connection, be connected the 5th electric capacity (C in parallel between inverting input with output
5) and the 15 resistance (R
15), output and the 16 resistance (R
16) connect, output is X
5output; 6th operational amplifier (A
6) inverting input and the 12 resistance (R
12) connect, in-phase input end ground connection, is connected the 11 resistance (R between inverting input with output
11), output and the 5th resistance (R
5) connect; 7th operational amplifier (A
7) inverting input and the first resistance (R
1) connect, in-phase input end ground connection, is connected the second resistance (R between inverting input with output
2), output and the 4th resistance (R
4) connect; 8th operational amplifier (A
8) inverting input and the 16 resistance (R
16) connect, in-phase input end ground connection, is connected the 17 resistance (R between inverting input with output
17), output and the 13 resistance (R
13) connect.
2. a kind of five rank amplitude limit type Jerk hyperchaotic circuits according to claim 1, is characterized in that: described 4th resistance (R
4) be variable resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420802445.7U CN204272149U (en) | 2014-12-17 | 2014-12-17 | A kind of five rank amplitude limit type Jerk hyperchaotic circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420802445.7U CN204272149U (en) | 2014-12-17 | 2014-12-17 | A kind of five rank amplitude limit type Jerk hyperchaotic circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204272149U true CN204272149U (en) | 2015-04-15 |
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ID=52806994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420802445.7U Withdrawn - After Issue CN204272149U (en) | 2014-12-17 | 2014-12-17 | A kind of five rank amplitude limit type Jerk hyperchaotic circuits |
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| Country | Link |
|---|---|
| CN (1) | CN204272149U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104486063A (en) * | 2014-12-17 | 2015-04-01 | 山东外国语职业学院 | Five-stage amplitude limiting Jerk hyperchaotic circuit |
-
2014
- 2014-12-17 CN CN201420802445.7U patent/CN204272149U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104486063A (en) * | 2014-12-17 | 2015-04-01 | 山东外国语职业学院 | Five-stage amplitude limiting Jerk hyperchaotic circuit |
| CN104486063B (en) * | 2014-12-17 | 2017-12-08 | 山东外国语职业学院 | A kind of five rank amplitude limit type Jerk hyperchaotic circuits |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150415 Termination date: 20151217 |
|
| EXPY | Termination of patent right or utility model | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20150415 Effective date of abandoning: 20171208 |
|
| AV01 | Patent right actively abandoned |