CN202259309U - Isolation structure for high voltage drive circuit - Google Patents
Isolation structure for high voltage drive circuit Download PDFInfo
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- CN202259309U CN202259309U CN2011203085465U CN201120308546U CN202259309U CN 202259309 U CN202259309 U CN 202259309U CN 2011203085465 U CN2011203085465 U CN 2011203085465U CN 201120308546 U CN201120308546 U CN 201120308546U CN 202259309 U CN202259309 U CN 202259309U
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Abstract
The utility model relates to an isolation structure for a high voltage drive circuit, comprising a P-type substrate and a P-type epitaxial layer, wherein a high-voltage region, a low-voltage region and a high-low-voltage junction terminal region are arranged on the P-type epitaxial layer; the first P-type junction isolation region is arranged between the high-low-voltage junction terminal region and the low-voltage region; a high-voltage insulated gate field-effect transistor exists between the high-voltage region and the low-voltage region; the isolation structure on two sides of the high-voltage insulated gate field-effect transistor and between the high-voltage insulated gate field-effect transistor and the high side is the second P-type junction isolation region; the second P-type well region concentration of the second P-type junction isolation region gradually reduces from the high-voltage region to the low-voltage region through the injection changes of an N-type well region; the second P-type junction isolation region between the high-voltage insulated gate field-effect transistor and the high side is only formed by the second P-type well region; and the second P-type junction isolation region is designed based on the complete exhaustion of the P-type junction isolation region under different high voltage and non punchthrough of the P-type junction isolation region in an on state. The isolation structure for a high voltage drive circuit solves the problem that the incomplete exhaustion of the P-type junction isolation structure causes the P-type junction isolation structure to meet localized breakdown, thus making the isolated regions be isolated from the periphery effectively.
Description
Technical field
The utility model relates to the high voltage half-bridge grid drive circuit in the high-voltage power integrated circuit, is a kind of about the isolation structure in the integrated high voltage drive circuit.
Background technology
High pressure grid drive circuit can be used for various fields, like electron rectifier in motor-driven, the fluorescent lamp and power management etc.Level shift circuit is the key component of entire circuit in the high pressure grid drive circuit; The electric property of the High-Voltage Insulation gate field-effect transistor LDMOS of composition level shift circuit and the coupling of the electricity between high-voltage LDMOS can influence the performance of shift circuit; The big electric current of high-voltage LDMOS source end and drain terminal can cause also that with big voltage thereby other the regional ghost effects of whole integrated circuit influence the electric property of whole integrated circuit; So the electric property of level shift circuit mesohigh LDMOS and the isolation of high-voltage LDMOS are undoubtedly the important content of high pressure grid drive circuit performance and technical study; The design of isolation structure is the high voltage integrated circuit key for design always in the high voltage integrated circuit, yet is faced with withstand voltage on the isolation structure design technology and Leakage Current two big difficult points.High voltage integrated circuit is that novel high-pressure power device, high-low pressure logic control circuit and protective circuit are integrated in the circuit on the single silicon chip; Because the advantage in its system: high reliability and stability and low-power consumption, volume, weight and cost, HVIC has great significance to miniaturization, intellectuality and energy-conservationization that realizes devices such as household electrical appliance, automotive electronics.High voltage integrated circuit can be divided into high lateral circuit, low lateral circuit and height again and tie the termination environment; For preventing the influence of high-tension circuit to its peripheral circuits; Crosstalking each other between cross influence between high voltage power device and high-tension circuit and the device; The isolation technology of high voltage integrated circuit is high voltage integrated circuit basis normal, that effectively work, also is the key components that form high-low pressure compatible technology platform.
Isolation between level shift circuit mesohigh LDMOS is the emphasis that half-bridge drive circuit research is paid close attention to always; Existing multiple isolation method in the existing half-bridge driven chip; The most effective and outstanding isolation method in these isolation methods for isolated high-voltage LDMOS in the high pressure grid drive circuit of mentioning in the U.S. Pat 7655979 of fairchild company; High pressure grid drive circuit comprises the higher-pressure region; Low-pressure area and high-low pressure knot termination environment; High-voltage LDMOS is between higher-pressure region and low-pressure area and adopt part to tie the termination environment as its drift region; Between high-low pressure knot termination environment and the low-pressure area, between high-voltage LDMOS and the high and low nip, all adopt isolating of P type trap and p type buried layer between high-voltage LDMOS and the high-low pressure knot termination environment to leading to isolation structure; Be around the whole high-voltage LDMOS with P type trap and p type buried layer logical isolation structure is kept apart other parts of high-voltage LDMOS and circuit, this is with its p type buried layer district down the logical P type that is extended to substrate that runs through that constitutes to be tied the isolation realization by the P type trap on the extension to logical the isolation, such can play isolated high-voltage LDMOS and the effect of other partial circuits on every side to leading to isolation structure.Yet; When the higher-pressure region connect high pressure, tying isolated area near the P type of higher-pressure region isolated part can exhaust fully, isolated away from the P type knot of higher-pressure region isolated part then can not exhaust fully; Thereby the partial breakdown phenomenon takes place, the withstand voltage reduction of the whole isolated structure that makes.
Summary of the invention
The utility model provides a kind of isolation structure of high-voltage driving circuit, and the P type knot isolated area that the utility model has solved away from the higher-pressure region can not exhaust the partial breakdown problem that causes fully, has improved the withstand voltage of isolation structure.
The utility model adopts following technical scheme:
A kind of isolation structure of high-voltage driving circuit; Comprise: P type substrate; On P type substrate, be provided with P type epitaxial loayer; On P type epitaxial loayer, be provided with low-pressure area and higher-pressure region; Between low-pressure area and higher-pressure region, being provided with high-low pressure knot termination environment, is P type knot isolated area between high-low pressure knot termination environment and low-pressure area, and described P type knot isolated area is made up of a p type buried layer and a P type well region; Being provided with the 2nd P type knot isolated area and the 2nd P type knot isolated area at the interior zone of P type knot isolated area ties isolated area with a P type and surrounds formation by area of isolation; In by area of isolation, be provided with and utilize the High-Voltage Insulation gate field-effect transistor of high-low pressure knot termination environment as the drift region, the part of said higher-pressure region is positioned at by area of isolation, is positioned at by the part higher-pressure region of area of isolation to comprise first dark N type trap that is located at P type substrate and a N-type well region that is located at P type epitaxial loayer; And N-type well region is positioned on the upper surface of the first dark N type trap; Be positioned at by the outer part higher-pressure region of area of isolation and comprise second dark N type trap that is located at P type substrate and the 2nd N-type well region that is located at P type epitaxial loayer, and N-type well region is positioned on the upper surface of the second dark N type trap, the described first dark N type trap is tied the termination environment to termination environment extension of high-low pressure knot and entering high-low pressure; The described second dark N type trap extends and gets into high-low pressure to high-low pressure knot termination environment ties the termination environment; It is characterized in that the 2nd P type knot isolated area is that the 2nd P type well region and the 2nd P type well region that is located in the P type epitaxial loayer is located on the P type substrate surface, the 2nd P type well region in the 2nd P type knot isolated area subregion that is positioned at high-low pressure knot terminal area is substituted by N type well region; And N type well region is positioned on the P type extension and by the 2nd P type well region and surrounds, and the injection area of the N type well region in the unit are of the 2nd P type knot isolated area points to low-pressure area along the higher-pressure region direction increases gradually.
The isolation structure that is used for high-voltage driving circuit is compatible mutually with existing technology, and compares with existing other isolation technologies, the utlity model has following advantage:
(1) in the traditional structure, adopted ring-shaped P type knot to isolate by isolated area (High-Voltage Insulation gate field-effect transistor)
The district surrounds and isolates; It all adopts the dark P type of high concentration trap isolation structure with the isolation of high-low pressure knot termination environment on every side or adopts the P type knot isolation structure to logical p type buried layer and P type well region; Promptly the isolation structure of all from the higher-pressure region to the low-pressure area all adopts the P type knot isolation structure of same concentrations, and when the higher-pressure region connect high pressure, high-voltage potential reduced along the drift region gradually; Because so current potential very high isolated part P type knot isolation structure near the higher-pressure region in higher-pressure region can exhaust fully; Puncture voltage very high (with reference to Figure 10), yet withstand voltage along with the drift region, electromotive force reduce the isolation structure both sides electromotive force that causes away from the higher-pressure region gradually in the drift region high and P type knot isolation structure is exhausted fully; Partial breakdown takes place in isolation structure easily here, finally causes the withstand voltage reduction of whole isolated structure.In the utility model; Be provided with the N type well region that changes the injection window in the P type knot isolated area away from the higher-pressure region gradually; Sensing low-pressure area direction reduces gradually along the higher-pressure region thereby reach the 2nd P type well region concentration, and the P type knot isolation structure under the different potentials can both be exhausted fully, has improved the puncture voltage of isolation structure; Suppress the generation of partial breakdown phenomenon, made segregation and peripheral part effectively isolate.
(2) the injection window flexibility of N type well region is very big in the utility model, only needs to guarantee that the 2nd P type well region is dense
Degree reduces from the higher-pressure region to the low-pressure area gradually, break-through can not take place under the simultaneously whole P type knot isolation structure ON state.
(3) the utility model and existing process compatible do not increase extra processing step, and preparation is simple.
Description of drawings
Fig. 1 is the high pressure grid drive circuit isolation structure sketch map that comprises the High-Voltage Insulation gate field-effect transistor in the utility model, and wherein 150 is high pressure lateral isolation gate field-effect transistor;
Fig. 2 is second kind of form of expression sketch map of the utility model isolation structure;
Fig. 3 is the third form of expression sketch map of the utility model isolation structure;
Fig. 4 is the 4th a kind of form of expression sketch map of the utility model isolation structure;
Fig. 5 is the 5th a kind of form of expression sketch map of the utility model isolation structure;
Fig. 6 is the transverse cross-sectional view along the I-I ' line of Fig. 1, and isolation structure wherein has the N buried regions as under 140 (a) and its;
Fig. 7 is the transverse cross-sectional view along the II-II ' line of Fig. 1, and isolation structure wherein has the N buried regions as under 140 (a) and its, and is the profile near low-pressure area 130 here, and the isolation structure both sides do not have dark N type trap DN;
Fig. 8 is the transverse cross-sectional view of isolation structure along the III-III ' line of Fig. 1, and 150 are the High-Voltage Insulation gate field-effect transistor, and that surround the High-Voltage Insulation gate field-effect transistor is isolation structure 140 (a) and 140 (b);
When Fig. 9 adds high pressure for the isolation structure both sides, the equipotential lines sketch map of N type well region isolation structure, visible among the figure, P type knot isolated area exhausts fully, and dotted line is the depletion region border among the figure;
When Figure 10 adds high pressure for the isolation structure both sides, the equipotential lines sketch map of no N buried regions district isolation structure, visible among the figure, P type knot isolated area exhausts fully, and wherein, dotted line 100 is the depletion region border, and solid line 101 is an equipotential lines.
Embodiment
A kind of isolation structure of high-voltage driving circuit; Comprise: P type substrate 1; On P type substrate 1, be provided with P type epitaxial loayer 2; On P type epitaxial loayer 2, be provided with low-pressure area 130 and higher-pressure region 110; Between low-pressure area 130 and higher-pressure region 110, be provided with high-low pressure knot termination environment 120; Between high-low pressure knot termination environment 120 and low-pressure area 130 P type knot isolated area 140a; Described P type knot isolated area 140a is made up of a p type buried layer 4 and a P type well region 71; Being provided with the 2nd P type knot isolated area 140b and the 2nd P type knot isolated area 140b at the interior zone of P type knot isolated area 140a ties isolated area 140a with a P type and surrounds formation by area of isolation; In by area of isolation, be provided with and utilize the High-Voltage Insulation gate field-effect transistor 150 of high-low pressure knot termination environment 120 as the drift region, the part of said higher-pressure region 110 is positioned at by area of isolation, is positioned at by the part higher-pressure region 110 of area of isolation to comprise the first dark N type trap 31 and a N-type well region 61 that is located at P type epitaxial loayer 2 that is located at P type substrate 1; And N-type well region 61 is positioned on the upper surface of the first dark N type trap 31; Be positioned at by the outer part higher-pressure region 110 of area of isolation and comprise the second dark N type trap 32 and the 2nd N-type well region 62 that is located at P type epitaxial loayer 2 that is located at P type substrate 1, and N-type well region 62 is positioned on the upper surface of the second dark N type trap (32), the described first dark N type trap 31 is tied termination environment 120 extensions and the entering high-low pressure is tied termination environment 120 to high-low pressure; The described second dark N type trap 32 extends and gets into high-low pressure to high-low pressure knot termination environment 120 ties termination environment 120; It is characterized in that the 2nd P type knot isolated area 140b is that the 2nd P type well region 72 and the 2nd P type well region 72 that is located in the P type epitaxial loayer 2 is located on P type substrate 1 surface, the 2nd P type well region 72 in the 2nd P type knot isolated area 140b subregion that is positioned at 120 zones, high-low pressure knot termination environment is substituted by N type well region 5; And N type well region 5 is positioned on the P type extension 2 and by the 2nd P type well region 72 and surrounds, and the direction of injection area 110 sensing low-pressure areas 130 along the higher-pressure region of the N type well region 5 in the unit are of the 2nd P type knot isolated area 140b increases gradually.The injection window of said N type well region 5 is for embarking on journey and spaced rectangle (with reference to Fig. 1), and 110 point to low-pressure area 130 directions along the higher-pressure region, and N type well region 5 injects the big or small constant of window but the spacing of N type well region 5 injection windows is dwindled gradually.The injection area that the N type well region 5 that injects window through the big or small rectangle of the grade of varied pitch reaches the 2nd P type knot isolated area 140b unit are N type well region 5 along the higher-pressure region 110 point to low-pressure areas 130 direction increase gradually, thereby the concentration that makes the 2nd P type well region 72 110 is pointed to low-pressure areas 130 directions and is reduced gradually along the higher-pressure region.The 2nd P type well region 72 that concentration reduces gradually can under high pressure exhaust fully, and what prevent the partial breakdown phenomenon makes the withstand voltage raising of isolation structure.
Embodiment 2
A kind of isolation structure of high-voltage driving circuit; Comprise: P type substrate 1; On P type substrate 1, be provided with P type epitaxial loayer 2; On P type epitaxial loayer 2, be provided with low-pressure area 130 and higher-pressure region 110; Between low-pressure area 130 and higher-pressure region 110, be provided with high-low pressure knot termination environment 120; Between high-low pressure knot termination environment 120 and low-pressure area 130 P type knot isolated area 140a; Described P type knot isolated area 140a is made up of a p type buried layer 4 and a P type well region 71; Being provided with the 2nd P type knot isolated area 140b and the 2nd P type knot isolated area 140b at the interior zone of P type knot isolated area 140a ties isolated area 140a with a P type and surrounds formation by area of isolation; In by area of isolation, be provided with and utilize the High-Voltage Insulation gate field-effect transistor 150 of high-low pressure knot termination environment 120 as the drift region, the part of said higher-pressure region 110 is positioned at by area of isolation, is positioned at by the part higher-pressure region 110 of area of isolation to comprise the first dark N type trap 31 and a N-type well region 61 that is located at P type epitaxial loayer 2 that is located at P type substrate 1; And N-type well region 61 is positioned on the upper surface of the first dark N type trap 31; Be positioned at by the outer part higher-pressure region 110 of area of isolation and comprise the second dark N type trap 32 and the 2nd N-type well region 62 that is located at P type epitaxial loayer 2 that is located at P type substrate 1, and N-type well region 62 is positioned on the upper surface of the second dark N type trap (32), the described first dark N type trap 31 is tied termination environment 120 extensions and the entering high-low pressure is tied termination environment 120 to high-low pressure; The described second dark N type trap 32 extends and gets into high-low pressure to high-low pressure knot termination environment 120 ties termination environment 120; It is characterized in that the 2nd P type knot isolated area 140b is that the 2nd P type well region 72 and the 2nd P type well region 72 that is located in the P type epitaxial loayer 2 is located on P type substrate 1 surface, the 2nd P type well region 72 in the 2nd P type knot isolated area 140b subregion that is positioned at 120 zones, high-low pressure knot termination environment is substituted by N type well region 5; And N type well region 5 is positioned on the P type extension 2 and by the 2nd P type well region 72 and surrounds, and the direction of injection area 110 sensing low-pressure areas 130 along the higher-pressure region of the N type well region 5 in the unit are of the 2nd P type knot isolated area 140b increases gradually.The injection window of said N type well region 5 is the rectangle (with reference to Fig. 2) of embarking on journey and arranging continuously, and 110 point to low-pressure area 130 directions along the higher-pressure region, and N type well region 5 injects window and narrows down gradually.The injection area that the N type well region that injects window through embarking on journey of narrowing down gradually and the rectangle arranged continuously reaches the 2nd P type knot isolated area 140b unit are N type well region 5 along the higher-pressure region 110 point to low-pressure areas 130 direction increase gradually, thereby the concentration that makes the 2nd P type well region 72 110 is pointed to low-pressure areas 130 directions and is reduced gradually along the higher-pressure region.The 2nd P type well region 72 that concentration reduces gradually can under high pressure exhaust fully, and what prevent the partial breakdown phenomenon makes the withstand voltage raising of isolation structure.
Embodiment 3
A kind of isolation structure of high-voltage driving circuit; Comprise: P type substrate 1; On P type substrate 1, be provided with P type epitaxial loayer 2; On P type epitaxial loayer 2, be provided with low-pressure area 130 and higher-pressure region 110; Between low-pressure area 130 and higher-pressure region 110, be provided with high-low pressure knot termination environment 120; Between high-low pressure knot termination environment 120 and low-pressure area 130 P type knot isolated area 140a; Described P type knot isolated area 140a is made up of a p type buried layer 4 and a P type well region 71; Being provided with the 2nd P type knot isolated area 140b and the 2nd P type knot isolated area 140b at the interior zone of P type knot isolated area 140a ties isolated area 140a with a P type and surrounds formation by area of isolation; In by area of isolation, be provided with and utilize the High-Voltage Insulation gate field-effect transistor 150 of high-low pressure knot termination environment 120 as the drift region, the part of said higher-pressure region 110 is positioned at by area of isolation, is positioned at by the part higher-pressure region 110 of area of isolation to comprise the first dark N type trap 31 and a N-type well region 61 that is located at P type epitaxial loayer 2 that is located at P type substrate 1; And N-type well region 61 is positioned on the upper surface of the first dark N type trap 31; Be positioned at by the outer part higher-pressure region 110 of area of isolation and comprise the second dark N type trap 32 and the 2nd N-type well region 62 that is located at P type epitaxial loayer 2 that is located at P type substrate 1, and N-type well region 62 is positioned on the upper surface of the second dark N type trap (32), the described first dark N type trap 31 is tied termination environment 120 extensions and the entering high-low pressure is tied termination environment 120 to high-low pressure; The described second dark N type trap 32 extends and gets into high-low pressure to high-low pressure knot termination environment 120 ties termination environment 120; It is characterized in that the 2nd P type knot isolated area 140b is that the 2nd P type well region 72 and the 2nd P type well region 72 that is located in the P type epitaxial loayer 2 is located on P type substrate 1 surface, the 2nd P type well region 72 in the 2nd P type knot isolated area 140b subregion that is positioned at 120 zones, high-low pressure knot termination environment is substituted by N type well region 5; And N type well region 5 is positioned on the P type extension 2 and by the 2nd P type well region 72 and surrounds, and the direction of injection area 110 sensing low-pressure areas 130 along the higher-pressure region of the N type well region 5 in the unit are of the 2nd P type knot isolated area 140b increases gradually.The injection window of said N type well region 5 is triangle (with reference to Fig. 3), and 110 point to low-pressure area 130 directions along the higher-pressure region, and it is triangle that N type well region 5 injects window.The injection area that the N type well region 5 that injects window through triangle reaches the 2nd P type knot isolated area 140b unit are N type well region 5 along the higher-pressure region 110 point to low-pressure areas 130 direction increase gradually, thereby the concentration that makes the 2nd P type well region 72 110 is pointed to low-pressure areas 130 directions and is reduced gradually along the higher-pressure region.The 2nd P type well region 72 that concentration reduces gradually can under high pressure exhaust fully, and what prevent the partial breakdown phenomenon makes the withstand voltage raising of isolation structure.
A kind of isolation structure of high-voltage driving circuit; Comprise: P type substrate 1; On P type substrate 1, be provided with P type epitaxial loayer 2; On P type epitaxial loayer 2, be provided with low-pressure area 130 and higher-pressure region 110; Between low-pressure area 130 and higher-pressure region 110, be provided with high-low pressure knot termination environment 120; Between high-low pressure knot termination environment 120 and low-pressure area 130 P type knot isolated area 140a; Described P type knot isolated area 140a is made up of a p type buried layer 4 and a P type well region 71; Being provided with the 2nd P type knot isolated area 140b and the 2nd P type knot isolated area 140b at the interior zone of P type knot isolated area 140a ties isolated area 140a with a P type and surrounds formation by area of isolation; In by area of isolation, be provided with and utilize the High-Voltage Insulation gate field-effect transistor 150 of high-low pressure knot termination environment 120 as the drift region, the part of said higher-pressure region 110 is positioned at by area of isolation, is positioned at by the part higher-pressure region 110 of area of isolation to comprise the first dark N type trap 31 and a N-type well region 61 that is located at P type epitaxial loayer 2 that is located at P type substrate 1; And N-type well region 61 is positioned on the upper surface of the first dark N type trap 31; Be positioned at by the outer part higher-pressure region 110 of area of isolation and comprise the second dark N type trap 32 and the 2nd N-type well region 62 that is located at P type epitaxial loayer 2 that is located at P type substrate 1, and N-type well region 62 is positioned on the upper surface of the second dark N type trap (32), the described first dark N type trap 31 is tied termination environment 120 extensions and the entering high-low pressure is tied termination environment 120 to high-low pressure; The described second dark N type trap 32 extends and gets into high-low pressure to high-low pressure knot termination environment 120 ties termination environment 120; It is characterized in that the 2nd P type knot isolated area 140b is that the 2nd P type well region 72 and the 2nd P type well region 72 that is located in the P type epitaxial loayer 2 is located on P type substrate 1 surface, the 2nd P type well region 72 in the 2nd P type knot isolated area 140b subregion that is positioned at 120 zones, high-low pressure knot termination environment is substituted by N type well region 5; And N type well region 5 is positioned on the P type extension 2 and by the 2nd P type well region 72 and surrounds, and the direction of injection area 110 sensing low-pressure areas 130 along the higher-pressure region of the N type well region 5 in the unit are of the 2nd P type knot isolated area 140b increases gradually.The injection window of said N type well region 5 points to the low-pressure area direction for embarking on journey and spaced circle (with reference to Fig. 4, Fig. 5) along the higher-pressure region, and the injection window of N type well region 5 is for embarking on journey and spaced circle.The injection area that the N type well region 5 that big small circular shape such as grade through varied pitch or the equally spaced circle that increases are gradually injected window reaches N type well region 5 under the 2nd P type knot isolated area 140b unit are along the higher-pressure region 110 point to low-pressure areas 130 direction increase gradually, thereby the concentration that makes the 2nd P type well region 72 110 is pointed to low-pressure areas 130 directions and is reduced gradually along the higher-pressure region.The 2nd P type well region 72 that concentration reduces gradually can under high pressure exhaust fully, and what prevent the partial breakdown phenomenon makes the withstand voltage raising of isolation structure.
The isolation structure preparation method of said high-voltage driving circuit is following:
The first step: P type silicon substrate 1 is prepared; Growth oxide layer, deposit silicon nitride, photoetching, ion inject phosphorus, annealing generates dark N type well region 31 and 32; Remove silicon nitride, photoetching, boron ion implantation, annealing generate p type buried regions 4;
Second step: growing P-type epitaxial loayer 2; Growth oxide layer, deposit silicon nitride, photoetching, ion inject phosphorus,, annealing forms N- type well region 61 and 62, photoetching, ion inject phosphorus, annealing forms N type well region 5, this moment N-trap 61 with 62 with N type well region 5 surperficial generate 5000 oxide layer.
The 3rd step: the general notes boron of all silicon nitrides of etching ion, annealing generate P type knot isolation well region 71 and 72;
The 4th step: remove above-mentioned 5000 oxide layer; Deposit silicon nitride, etch silicon nitride, living long field oxide form place and active area;
The 5th step: at the active area layer thickness of growing is 1000 gate oxide, and ion injects the adjustment of boron fluoride threshold value, carries out deposit, the etching of polysilicon gate then;
The 6th step: photoetching, ion inject phosphorus and arsenic generates N type source region 9 and N type drain region 8; Photoetching, ion inject boron fluoride and generate P type contact zone 10; Deposit dielectric isolation oxide layer, contact hole etching, depositing metal aluminium, etching aluminium carries out the medium Passivation Treatment at last to form metal connecting line.
Claims (5)
1. the isolation structure of a high-voltage driving circuit; Comprise: P type substrate (1); On P type substrate (1), be provided with P type epitaxial loayer (2); On P type epitaxial loayer (2), be provided with low-pressure area (130) and higher-pressure region (110); Between low-pressure area (130) and higher-pressure region (110), be provided with high-low pressure knot termination environment (120); It between high-low pressure knot termination environment (120) and low-pressure area (130) P type knot isolated area (140a); Described P type knot isolated area (140a) is made up of a p type buried layer (4) and a P type well region (71); Be provided with the 2nd P type knot isolated area (140b) and the 2nd P type knot isolated area (140b) surrounds formation by area of isolation with P type knot isolated area (140a) at the interior zone of P type knot isolated area (140a); In by area of isolation, be provided with and utilize the High-Voltage Insulation gate field-effect transistor (150) of high-low pressure knot termination environment (120) as the drift region; The part of said higher-pressure region (110) is positioned at by area of isolation; Be positioned at by the part higher-pressure region (110) of area of isolation and comprise first a dark N type trap (31) that is located at P type substrate (1) and a N-type well region (61) that is located at P type epitaxial loayer (2); And N-type well region (61) is positioned on the upper surface of the first dark N type trap (31); Be positioned at by the outer part higher-pressure region (110) of area of isolation and comprise the second dark N type trap (32) that is located at P type substrate (1) and the 2nd N-type well region (62) that is located at P type epitaxial loayer (2), and N-type well region (62) is positioned on the upper surface of the second dark N type trap (32), the described first dark N type trap (31) is tied termination environment (120) extension and the entering high-low pressure is tied termination environment (120) to high-low pressure; The described second dark N type trap (32) extends and gets into high-low pressure to high-low pressure knot termination environment (120) ties termination environment (120); It is characterized in that the 2nd P type knot isolated area (140b) is located on P type substrate (1) surface for the 2nd P type well region (72) and the 2nd P type well region (72) that is located in the P type epitaxial loayer (2), the 2nd P type well region (72) in the 2nd P type knot isolated area (140b) subregion that is positioned at zone, high-low pressure knot termination environment (120) is substituted by N type well region (5); And the P type extension (2) that is positioned at N type well region (5) goes up and is surrounded by the 2nd P type well region (72), and the direction of the injection area of the N type well region (5) in the unit are of the 2nd P type knot isolated area (140b) (110) sensing low-pressure areas (130) along the higher-pressure region increases gradually.
2. the isolation structure of high-voltage driving circuit according to claim 1 is characterized in that, the injection window of N type well region (5) is for embarking on journey and spaced rectangle.
3. the isolation structure of high-voltage driving circuit according to claim 1 is characterized in that, the injection window of N type well region (5) is the rectangle of embarking on journey and arranging continuously.
4. the isolation structure of high-voltage driving circuit according to claim 1 is characterized in that, the injection window of N type well region (5) is a triangle.
5. the isolation structure of high-voltage driving circuit according to claim 1 is characterized in that, the injection window of N type well region (5) is for embarking on journey and spaced circle.
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| CN2011203085465U CN202259309U (en) | 2011-08-23 | 2011-08-23 | Isolation structure for high voltage drive circuit |
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| CN2011203085465U CN202259309U (en) | 2011-08-23 | 2011-08-23 | Isolation structure for high voltage drive circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306656A (en) * | 2011-08-23 | 2012-01-04 | 东南大学 | Isolation structure of high voltage driver circuit |
| CN105874597A (en) * | 2014-07-02 | 2016-08-17 | 富士电机株式会社 | Semiconductor integrated-circuit device |
| CN111615254A (en) * | 2020-06-19 | 2020-09-01 | 苏州浪潮智能科技有限公司 | Printed circuit board and power supply design method thereof |
-
2011
- 2011-08-23 CN CN2011203085465U patent/CN202259309U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306656A (en) * | 2011-08-23 | 2012-01-04 | 东南大学 | Isolation structure of high voltage driver circuit |
| CN105874597A (en) * | 2014-07-02 | 2016-08-17 | 富士电机株式会社 | Semiconductor integrated-circuit device |
| CN111615254A (en) * | 2020-06-19 | 2020-09-01 | 苏州浪潮智能科技有限公司 | Printed circuit board and power supply design method thereof |
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