CN202189209U - Lead structure, liquid crystal display lead zone structure and liquid crystal display - Google Patents
Lead structure, liquid crystal display lead zone structure and liquid crystal display Download PDFInfo
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- CN202189209U CN202189209U CN2011203315965U CN201120331596U CN202189209U CN 202189209 U CN202189209 U CN 202189209U CN 2011203315965 U CN2011203315965 U CN 2011203315965U CN 201120331596 U CN201120331596 U CN 201120331596U CN 202189209 U CN202189209 U CN 202189209U
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- lead
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Abstract
The utility model discloses a lead structure, a liquid crystal display lead zone structure and a liquid crystal display, which solve the problem that in the prior art, during a process that corrosion forms a through hole, bottom angle of gradient of a gate insulation layer is oversized due to drilling, so that pixel electrode on grid layers is broken, display signals can not be loaded on a display area, passing rate of the liquid crystal display is lowered. The lead structure comprises a glass substrate, a lead electrode is arranged on the glass substrate, an insulation structure is arranged on the lead electrode, the through hole is arranged on the insulation structure above the lead electrode, and a connecting electrode is arranged in the through hole and on the insulation structure and closely covered on the lead electrode exposed out from the through hole. At least three insulation layers are arranged on the insulation structure, and the compactness of the insulation layer on the lower most layer is largest.
Description
Technical field
The utility model relates to a kind of pin configuration, LCDs lead district structure and LCDs, relates in particular to a kind of LCDs that can effectively avoid boring pin configuration, the LCDs lead district structure at quarter and have this lead district structure.
Background technology
LCDs is in light weight because of it, and thin thickness and characteristics such as low in energy consumption are widely used in the electronic product.Be connected with the LCDs viewing area, also be provided with lead district.The glass substrate of lead district is provided with grid layer, gate insulator structure, source electrode insulation course and pixel electrode; After the source electrode insulation course forms, need carry out etching, to form via hole to it; After the etching, the pixel deposition electrode; This pixel electrode is connected with the grid layer of lower floor, and shows signal can be transferred on the thin film transistor (TFT) of viewing area through grid.
In said process, as shown in Figure 1, through in the cavity of etching apparatus, being blown into etching gas lead district is carried out etching, in gate insulator 3 bottoms, etching gas carries out etching along grid layer 5 parallel directions to gate insulator 3.For improving the homogeneity of etching, need to increase etching time, then can in the via hole 6 of gate insulator 3 bottoms, cause this moment and bore the situation of carving, the bottom angle of gradient of gate insulator 3 is increased.In the process of pixel electrode deposition; Pixel electrode deposits in the via hole, because of the pixel electrode that is deposited is thinner, and then 6 pixel electrodes, 1 fracture at the via hole place; Shows signal on the pixel electrode 1 can't be loaded on the grid layer 5; Then shows signal can't be transferred on the thin film transistor (TFT) of viewing area, causes the linear bad of LCD, thereby has reduced the yields of LCDs.
The utility model content
The embodiment of the utility model provides a kind of LCDs that can effectively avoid boring pin configuration, the LCDs lead district structure at quarter and have this lead district structure.
For achieving the above object, the embodiment of the utility model adopts following technical scheme:
A kind of pin configuration comprises glass substrate; This glass substrate is provided with the lead-in wire electrode; This lead-in wire electrode is provided with insulation system; Insulation system above the said lead-in wire electrode is provided with via hole; In this via hole, be provided with connection electrode, the lead-in wire electrode that this connection electrode closely covers in the via hole to be exposed with the insulation system surface; Said insulation system is provided with three-layer insulated at least layer, and the compactness of undermost insulation course is maximum.
A kind of LCDs lead district structure comprises glass substrate; This glass substrate is provided with grid layer; This grid layer is provided with the gate insulator structure; This gate insulator structure is provided with the source electrode insulation course; Source electrode insulation course and gate insulator structure above the said grid layer are provided with via hole; In this via hole, be provided with pixel electrode, the grid layer that this pixel electrode closely covers in the via hole to be exposed with the source electrode surface of insulating layer; Said gate insulator structure is provided with at least three layers of gate insulator, and the compactness of undermost gate insulator is maximum.
A kind of LCDs comprises lead district; This lead district comprises glass substrate; This glass substrate is provided with grid layer; This grid layer is provided with the gate insulator structure; This gate insulator structure is provided with the source electrode insulation course; Source electrode insulation course and gate insulator structure above the said grid layer are provided with via hole; In this via hole, be provided with pixel electrode, the grid layer that this pixel electrode closely covers in the via hole to be exposed with the source electrode surface of insulating layer; Said gate insulator structure is provided with at least three layers of gate insulator, and the compactness of undermost gate insulator is maximum.
A kind of pin configuration that the utility model embodiment provides, LCDs lead district structure and LCDs; Through the three-layer insulated at least layer of deposition on the lead-in wire electrode; And the compactness of the insulation course of below is maximum; The insulation course that is lower floor is difficult to etching; Increasing under the level and smooth situation of the etching time assurance etching homogeneity and the via hole angle of gradient, avoid undermost lead wire insulation layer to bore the generation of carving, improved the yields of pin configuration with the LCDs production of using this kind pin configuration.
Description of drawings
Fig. 1 is that a kind of LCDs lead district structure is bored the synoptic diagram at quarter in the background technology;
Fig. 2 is the synoptic diagram of a kind of pin configuration of the utility model;
Fig. 3 is the structural representation of a kind of LCDs lead district of the utility model.
Embodiment
Below in conjunction with accompanying drawing a kind of pin configuration of the utility model embodiment, LCDs lead district structure and LCDs are described in detail.
A kind of pin configuration, as shown in Figure 2, comprise glass substrate 4; This glass substrate 4 is provided with lead-in wire electrode 5; This lead-in wire electrode 5 is provided with insulation system 3; Insulation system 3 above the said lead-in wire electrode 5 is provided with via hole 6; In this via hole 6, be provided with connection electrode 1 with insulation system 3 surfaces, this connection electrode 1 closely covers the lead-in wire electrode 5 that is exposed in the via hole 6; Said insulation system 3 is provided with three-layer insulated at least layer, and the compactness of undermost insulation course is maximum.
According to the needs of etching, multilayer dielectric layer structure 3 can be set, the integral thickness of said insulation system 3 is a fixed value.
In the process of film forming, at first glass substrate 4 is moved in the cavity of first splashing device, be inclined in cavity; At this cavity opposite side; Be provided with target, form lead-in wire electrode 5 through this target, the material of said lead-in wire electrode 5 is a kind of in aluminium, tungsten, chromium, tantalum or the molybdenum.In cavity, feed inert gas, for example argon gas.At this moment, glass substrate 4 loads high voltage with the target outside in cavity, makes and forms electric field in the cavity, and add loaded magnetic field in glass substrate 4 outsides.Under the action of high voltage that in cavity, is loaded, argon gas forms plasma, and under effect of electric field, makes the plasma bombardment target of argon gas, and target is pounded target atom, and in the effect deposit in magnetic field on glass substrate 4, form lead-in wire electrode 5.
The glass substrate 4 of deposition of wire electrode 5 is taken out, and on this lead-in wire electrode 5, spray photoresist; Glass substrate 4 is inserted in the exposure sources, make public; After the exposure, this glass substrate 4 is put into developer solution develop, this moment, the photoresist of exposed portion dissolved under the effect of developer solution, the remaining unexposed part of photoresist on glass substrate 4.
Be to form insulation system 3, the material of said insulation system 3 is a silicon nitride, after accomplishing the peeling off of photoresist, glass substrate 4 is put into the cavity of second splashing device, and this moment, glass substrate 4 was positioned over the cavity bottom; Reacting gas is fed in the cavity, like SiH
3Or SiH
4Gas and NH
3The mixed gas of gas is when the pressure in the cavity reaches certain value, at glass substrate 4 downsides and cavity top on-load voltage; Load HF voltage on the diode in cavity, make reacting gas carry out glow discharge, produce the plasma of reacting gas, on glass substrate 4 and lead-in wire electrode 5, and get rid of reacted gas in the effect of electric field deposit.In the cavity of second splashing device,, can carry out deposition three times for forming three-layer insulated at least layer; In three depositions, added voltage has nothing in common with each other on the diode, thereby makes the discharge power of reacting gas different; When being undermost first insulation course 32 deposition, the voltage that loads on the diode is minimum, and gas discharge power is minimum; Deposition is slowly carried out, and makes the compactness of first insulation course 32 maximum; When depositing the second middle insulation course 31, the voltage that is loaded on the diode is higher than the voltage that deposits first insulation course 32, and gas discharge power increases, and sedimentation velocity is accelerated, and makes the compactness of second insulation course 31 be lower than first insulation course 32; When the 3rd insulation course 30 of the deposition the superiors, the voltage that is loaded on the diode is higher than the voltage that deposits second insulation course 31, and gas discharge power increases once more, and sedimentation velocity is accelerated once more, makes the compactness of the 3rd insulation course 30 be lower than second insulation course 31.
At this moment, spray photoresist 7 on the insulation system 3, and in exposure machine, photoresist 7 is carried out exposure-processed, the exposed portion with photoresist 7 in developer solution dissolves.
For forming via hole 6 glass substrate 4 and last square structure are put into etching apparatus, in this equipment, feed etching gas, insulation system 3 is carried out etching.Wherein after etching into insulation system 3, the compactness of the insulation course 30 of the superiors is lower, and etching is easier to, and the compactness of undermost insulation course 32 is higher, and more difficult etching is exposed for lead-in wire electrode 5 is accomplished, and improves the homogeneity of etching, can increase etching time.Because insulation system 3 is provided with multilayer dielectric layer; And the compactness of orlop insulation course is maximum; Promptly when insulation system 3 was carried out etching, the 3rd insulation course 30 and second insulation course 31 on upper strata were easier to etching, the more difficult etching of the insulation course of below; The compactness of having avoided all insulation courses is all than higher, thereby improved the efficient of etching; On the other hand; Bigger with the compactness of lead-in wire electrode 5 contacted first insulation courses 32; When under the inhomogeneity prerequisite that guarantees etching, increasing etching time; Avoid making the angle of gradient of first insulation course, 32 bottoms excessive, thereby avoid when deposition connection electrode 5, connection electrode 5 being ruptured because of the angle of gradient of insulation course is excessive because of boring to carve.
After via hole 6 forms, with the photoresist lift off on the insulation system 3, and deposition connection electrode 1, accomplish the formation of pin configuration.
The material of said connection electrode 1 is an indium tin oxide.
Corresponding with said a kind of pin configuration, the utility model also provides a kind of LCDs lead district structure.
A kind of LCDs lead district structure, as shown in Figure 3, comprise glass substrate 4; This glass substrate 4 is provided with grid layer 10; This grid layer 10 is provided with gate insulator structure 9; This gate insulator structure 9 is provided with source electrode insulation course 8; Source electrode insulation course 8 above the said grid layer 5 is provided with via hole 6 with gate insulator structure 3; In this via hole 6, be provided with pixel electrode 7 with source electrode insulation course 8 surfaces, this pixel electrode 7 closely covers the grid layer 5 that is exposed in the via hole 6; Said gate insulator structure 3 is provided with at least three layers of gate insulator, and the compactness of undermost gate insulator is maximum.
Said grid layer 10 is identical with lead-in wire electrode 5 effects in the pin configuration as shown in Figure 1;
Said gate insulator structure 9 is identical with insulation system 3 effects in the pin configuration as shown in Figure 1;
Said pixel electrode 7 is identical with connection electrode 1 effect in the pin configuration as shown in Figure 1.
The material of said source electrode insulation course 8 is a silicon nitride, and the density of this source electrode insulation course 8 is less than the density of gate insulator.
After having deposited grid layer 10 and gate insulator structure 9 on the glass substrate, will be above the said gate insulator structure 9 that comprises three layers of gate insulator, deposition source electrode insulation course 8; After these source electrode insulation course 8 depositions are accomplished, source electrode insulation course 8 and gate insulator structure 9 are carried out etching, form via hole 6; Pixel electrode 7 is deposited in source electrode insulation course 8 surfaces and the via hole 6, and pixel electrode 7 is closely covered on the grid layer 10 in via hole 6 and the via hole 6.
Corresponding with above-mentioned a kind of LCDs lead district structure, the utility model also provides a kind of LCDs.
A kind of LCDs comprises lead district; This lead district comprises glass substrate; This glass substrate is provided with grid layer; This grid layer is provided with the gate insulator structure; This gate insulator structure is provided with the source electrode insulation course; Source electrode insulation course and gate insulator structure above the said grid layer are provided with via hole; In this via hole, be provided with pixel electrode, the grid layer that this pixel electrode closely covers in the via hole to be exposed with the source electrode surface of insulating layer; Said gate insulator structure is provided with at least three layers of gate insulator, and the compactness of undermost gate insulator is maximum.
A kind of pin configuration that the utility model embodiment provides, LCDs lead district structure and LCDs; Through the three-layer insulated at least layer of deposition on the lead-in wire electrode; And the compactness of the insulation course of below is maximum; The insulation course that is lower floor is difficult to etching; Increasing under the level and smooth situation of the etching time assurance etching homogeneity and the via hole angle of gradient, avoid undermost lead wire insulation layer to bore the generation of carving, improved the yields of pin configuration with the LCDs production of using this kind pin configuration.
The above; Be merely the embodiment of the utility model; But the protection domain of the utility model is not limited thereto; Any technician who is familiar with the present technique field can expect changing or replacement in the technical scope that the utility model discloses easily, all should be encompassed within the protection domain of the utility model.Therefore, the protection domain of the utility model should be as the criterion by said protection domain with claim.
Claims (8)
1. a pin configuration comprises glass substrate; This glass substrate is provided with the lead-in wire electrode; This lead-in wire electrode is provided with insulation system; Insulation system above the said lead-in wire electrode is provided with via hole; In this via hole, be provided with connection electrode with the insulation system surface, the lead-in wire electrode that this connection electrode closely covers in the via hole to be exposed is characterized in that, said insulation system is provided with three-layer insulated at least layer, and the compactness of undermost insulation course is maximum.
2. pin configuration according to claim 1 is characterized in that, the integral thickness of said insulation system is a fixed value.
3. pin configuration according to claim 1 is characterized in that, the material of said lead-in wire electrode is a kind of in aluminium, tungsten, chromium, tantalum or the molybdenum.
4. pin configuration according to claim 1 is characterized in that, the material of said insulation system is a silicon nitride.
5. pin configuration according to claim 1 is characterized in that, the material of said connection electrode is an indium tin oxide.
6. a LCDs lead district structure comprises glass substrate; This glass substrate is provided with grid layer; This grid layer is provided with the gate insulator structure; This gate insulator structure is provided with the source electrode insulation course; Source electrode insulation course and gate insulator structure above the said grid layer are provided with via hole; In this via hole, be provided with pixel electrode with the source electrode surface of insulating layer; The grid layer that this pixel electrode closely covers in the via hole to be exposed; It is characterized in that said gate insulator structure is provided with at least three layers of gate insulator, and the compactness of undermost gate insulator is maximum.
7. LCDs lead district structure according to claim 6 is characterized in that the material of said source electrode insulation course is a silicon nitride.
8. a LCDs comprises lead district; This lead district comprises glass substrate; This glass substrate is provided with grid layer; This grid layer is provided with the gate insulator structure; This gate insulator structure is provided with the source electrode insulation course; Source electrode insulation course and gate insulator structure above the said grid layer are provided with via hole; In this via hole, be provided with pixel electrode with the source electrode surface of insulating layer; The grid layer that this pixel electrode closely covers in the via hole to be exposed; It is characterized in that said gate insulator structure is provided with at least three layers of gate insulator, and the compactness of undermost gate insulator is maximum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203315965U CN202189209U (en) | 2011-09-05 | 2011-09-05 | Lead structure, liquid crystal display lead zone structure and liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203315965U CN202189209U (en) | 2011-09-05 | 2011-09-05 | Lead structure, liquid crystal display lead zone structure and liquid crystal display |
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| Publication Number | Publication Date |
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| CN202189209U true CN202189209U (en) | 2012-04-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011203315965U Expired - Lifetime CN202189209U (en) | 2011-09-05 | 2011-09-05 | Lead structure, liquid crystal display lead zone structure and liquid crystal display |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103231570A (en) * | 2013-04-11 | 2013-08-07 | 合肥京东方光电科技有限公司 | A thin film layer and a manufacturing method thereof, a substrate for display, and a liquid crystal display |
| WO2016029612A1 (en) * | 2014-08-28 | 2016-03-03 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method therefor, display substrate and display device |
| WO2016112684A1 (en) * | 2015-01-14 | 2016-07-21 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display device |
| CN106444183A (en) * | 2016-12-09 | 2017-02-22 | 深圳市华星光电技术有限公司 | Ultra-narrow frame terminal area structure, manufacturing method and display panel |
| CN110112212A (en) * | 2019-04-25 | 2019-08-09 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and array substrate |
-
2011
- 2011-09-05 CN CN2011203315965U patent/CN202189209U/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103231570A (en) * | 2013-04-11 | 2013-08-07 | 合肥京东方光电科技有限公司 | A thin film layer and a manufacturing method thereof, a substrate for display, and a liquid crystal display |
| CN103231570B (en) * | 2013-04-11 | 2016-03-30 | 合肥京东方光电科技有限公司 | A kind of thin layer and preparation method thereof, substrate for display, liquid crystal display |
| US9502571B2 (en) | 2013-04-11 | 2016-11-22 | Boe Technology Group Co., Ltd. | Thin film layer and manufacturing method thereof, substrate for display and liquid crystal display |
| WO2016029612A1 (en) * | 2014-08-28 | 2016-03-03 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method therefor, display substrate and display device |
| US9589991B2 (en) | 2014-08-28 | 2017-03-07 | Boe Technology Group Co., Ltd. | Thin-film transistor, manufacturing method thereof, display substrate and display device |
| WO2016112684A1 (en) * | 2015-01-14 | 2016-07-21 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display device |
| US9825063B2 (en) | 2015-01-14 | 2017-11-21 | Boe Technology Group Co., Ltd. | Display panel and method of fabricating the same, and display device |
| CN106444183A (en) * | 2016-12-09 | 2017-02-22 | 深圳市华星光电技术有限公司 | Ultra-narrow frame terminal area structure, manufacturing method and display panel |
| CN106444183B (en) * | 2016-12-09 | 2019-12-31 | 深圳市华星光电技术有限公司 | Ultra-narrow frame terminal area structure, manufacturing method and display panel |
| CN110112212A (en) * | 2019-04-25 | 2019-08-09 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and array substrate |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120411 |
|
| CX01 | Expiry of patent term |