CN202160161U

CN202160161U - Multifunctional clock generator based on field programmable gate array (FPGA)

Info

Publication number: CN202160161U
Application number: CN2011202909576U
Authority: CN
Inventors: 朱磊
Original assignee: Sichuan Jiuzhou Electric Group Co Ltd
Current assignee: Sichuan Jiuzhou Electric Group Co Ltd
Priority date: 2011-08-11
Filing date: 2011-08-11
Publication date: 2012-03-07
Anticipated expiration: 2021-08-11

Abstract

The utility model discloses a multifunctional clock generator based on a field programmable gate array (FPGA), which relates to the technology of a digital circuit and aims at providing a clock generator capable of being transplanted to an FPGA digital circuit. The technical scheme is that the multifunctional clock generator comprises a reference clock generator, a clock unit counter based on the FPGA and a read-write controller based on the FPGA. The clock unit counter is provided with a count pulse input end and a carry enabling output end. The reference clock generator is connected with the count pulse input end of the clock unit counter. The read-write controller is a read-write port of the clock unit counter. The carry enabling output end of the clock unit counter serves as the clock pulse output end. The multifunctional clock generator has various functions such as timing, time erasing, time modification and the like, can adapt to timing of a leap year, a common year, a leap month and a February of a common year, can be transplanted to any FPGA chip, is good in compatibility, and is mainly used for providing a reliable and controllable clock for the digital circuit based on the FPGA.

Description

A kind of multifunction timepiece generator based on FPGA

Technical field

The utility model relates to Digital Electronic Technique, particularly based on the clock-signal generator of FPGA.

Background technology

FPGA (Field Programmable Gate Array; Field programmable gate array) is a kind of novel high-performance programmable logic device; Its integrated level is very high; Extremely complicated sequential and combinational logic circuit function be can accomplish, high speed, highdensity digital circuit logic design field are applicable to.FPGA develops rapidly in fields such as communication, network, military affairs, household electrical appliances, becomes most popular hardware designs basis, becomes the preceding the best checking design sample of special-purpose asic chip flow simultaneously, can reduce expensive ASIC flow risk greatly.

In the plurality of applications of FPGA; All need provide the overall situation unified clock reference, the high accuracy clock signal is stepping with minimum time unit, provides system's operation required time reference; And can be controlled functions such as completion resets, time read-write, time adjustment by the microcontroller of periphery.

At present, all be to adopt an independent clock chip to provide digital circuit work necessary clock reference in the digital circuit that FPGA realizes, this not only increased circuit complexity also increased production cost.

The utility model content

The goal of the invention of the utility model is: the problem to above-mentioned existence provides a kind of clock generator that can conveniently be transplanted on any a FPGA digital circuit, and has avoided increasing extra clock reference circuit.

The technical scheme that the utility model adopts is such:

A kind of multifunction timepiece generator based on FPGA comprises reference clock generator, based on clock-unit's counter of FPGA, based on the read-write controller of FPGA; Has the count pulse input on the said clock-unit counter and carry enables output; Said reference clock generator is connected with the count pulse input of clock-unit's counter; Read-write controller is the read-write interface of clock-unit's counter; The carry of said clock-unit counter enables output as output terminal of clock pulse.

Preferably, also comprise based on the every month fate determining device of FPGA and leap year determining device based on FPGA;

The pulse signal frequency of said reference clock generator output is 80MHz, and clock-unit's timer comprises minimum time counter, microsecond counter, 10 microsecond counters, 0.1 millisecond counter, 1 millisecond counter, 10 millisecond counters, 100 millisecond counters, second counter, minute counter, hour counter, day counter, month counter, year counter;

Said reference clock generator is connected with the count pulse input of minimum time counter, and the carry of minimum time counter enables the pulse signal that the output output cycle is 1 microsecond; Minimum time counter, microsecond counter, 10 microsecond counters, 0.1 millisecond counter, 1 millisecond counter, 10 millisecond counters, 100 millisecond counters, second counter, minute counter, hour counter, day counter, month counter, a year counter are linked in sequence, and the carry of low counter enables output and is connected with the count pulse input of the counter of high one of which position;

The fate determining device was connected with sky counter, month counter simultaneously in said every month, was used to read the current counting of month counter, write the counting upper limit of day counter;

The fate determining device had leap year judgement signal input part in every month, and the output of said leap year determining device judges that with the leap year signal input part is connected;

The leap year determining device also with year counter be connected, be used to read the current counting of year counter.

Preferably, any one carry enables output as output terminal of clock pulse in said each unit clock counter.

Preferably, any one carry enables output as the pulse interrupt output in said each unit clock counter.

In sum, owing to adopted technique scheme, the beneficial effect of the utility model is:

1, can accomplish multiple functions such as timing, time are wiped, time modification;

2, adapt to leap year, non-leap year automatically, the leap month, the timing February of a non-leap year;

3, be minimum time stepping self-clocking with 1 microsecond, can provide the current time value according to demand simultaneously and supply the digital circuit of FPGA to use;

4, externally provide second, multiple pulse interrupt grades;

5, data/address bus, read-write interface externally are provided, can compatible easily various peripheral microprocessors, single-chip microcomputer;

6, can compatible all FPGA devices, directly on existing FPGA digital circuit, realize, to digital circuit dependable performance, controllable clock are provided, need not extra employing clock reference circuit.

Description of drawings

Fig. 1 is the internal structure schematic diagram of the utility model.

What Fig. 2 showed is the signaling interface of the clock generator of the utility model.

Among the figure: 1 reference clock input port, 2 clock enable signal input ports, 3 read ports, 4 write ports, 5 address ports; 6 data-in ports, 7 work index signal ports, 8 pulse interrupt output/output terminal of clock pulse, 9 data-out ports, 10 microseconds and 10 microsecond counters; 11 0.1 milliseconds and 1 millisecond counter, 12 10 milliseconds and 100 millisecond counters, 13 seconds counters, 14 minute counters; 15 hour counters, 16 daily counters, 17 month counters, 18 years low counter; 19 time high-positioned counters, 20 calendar month fate determining devices, 21 leap year determining devices, 22 read-write controllers.

Embodiment

Below in conjunction with accompanying drawing, the utility model is done detailed explanation.

For the purpose, technical scheme and the advantage that make the utility model is clearer,, the utility model is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.

The utility model utilizes Verilog HDL hardware language to accomplish the design based on the clock-signal generator of FPGA.

The disclosed clock-signal generator of the utility model is to utilize FPGA to realize, and is simple in structure, as long as just comprise reference clock generator, clock-unit's counter, read-write controller can realize timing, time wipe, the time modification function; Has the count pulse input on the said clock-unit counter and carry enables output; Said reference clock generator is connected with the count pulse input of clock-unit's counter; Read-write controller is the read-write interface of clock-unit's counter; The carry of said clock-unit counter enables output also as output terminal of clock pulse.

As shown in Figure 1, mark 10 to 19 all is clock-unit's counter of core among the figure, is all realized by the register of 8bit.Wherein microsecond counter, 10 microsecond counters, 0.1 millisecond counter, 1 millisecond counter, 10 millisecond counters, 100 millisecond counters are 4bit; The low 4bit of corresponding one by one register 10, high 4bit; The low 4bit of register 11, high 4bit, the low 4bit of register 12, high 4bit.Second counter, minute counter, hour counter, day counter, month counter are 8bit, corresponding one by one register 13 ~ 17.Year counter is 16bit, takies register 18,19.In addition, when the pulse signal cycle of clock reference generator generation was not 1 microsecond, clock-unit's counter also need comprise the minimum time counter, and the figure place of minimum time counter is by the pulse signal cycle decision of clock reference generator output.Said each unit clock counter has the count pulse input, carry enables output.

This constant-temperature crystal oscillator of sentencing 80MHz is an example, and a specific embodiment of the utility model is described.The cycle of clock reference generator output is that the pulse signal of 0.0125 microsecond is connected to the minimum time counter; The minimum time counter is at least 7bit; Its count pulse input is connected with the output of constant-temperature crystal oscillator; Its carry enables output and is connected with the microsecond counter, during minimum time rolling counters forward to 80 pulse period (1 microsecond), to pulse of microsecond counter output; Enable 10 microsecond counters after the microsecond rolling counters forward full 10; And the like, each clock-unit's counter carries out accumulated counts according to system (the counting upper limit) separately, and the rudimentary register in the full back of counting enables output count pulse of clock-unit's counter output to high its one-level through carry.

The utility model also comprises every month fate determining device 20 and leap year determining device 21.Leap year determining device 21 is connected with a year counter 18,19; Be used to read the current counting of year counter 18,19; And judge whether when the year before last be the leap year, if the leap year then transfers to out every month fate determining device 20 output useful signals, fate determining device 20 was connected with sky counter 16, month counter 17 simultaneously in every month; Be used to read month counter 17 current countings; And according to intrinsic fate setting in every month when counter 16 the counting upper limit day before yesterday, special, when every month fate determining device 20 reads month counter 17 current countings when being February; And the counting upper limit with sky counter 16 during leap year determining device 21 output useful signals is made as 29, if then the counting upper limit of sky counter 16 is not made as 28 when leap year determining device 21 is exported useful signal.

The utility model also comprises read-write controller 22, and read-write controller 22 externally provides read port 3, write port 4, address port 5, data-in port 9 and data-out port 6.Read port 3 is used for connecting control chips such as peripheral various microprocessors, single-chip microcomputer, DSP, CPLD, realizes the read operation of control chip to various clock-units counter.Write port 4 is used for connecting control chips such as peripheral various microprocessors, single-chip microcomputer, DSP, CPLD, realizes the write operation of control chip to various clock-units counter, thus the numerical value change of change from the microsecond counter to the year counter.Address port 5 provides external address bus, distributes various clock-units counter address.Data-in port 9 provides 16 outside bit data to go into passage.Data-out port 6 provides 16 outside bit data to go out passage.

Like Fig. 2, the utility model also externally provides reference clock input port 1, clock enable signal input port 2, work index signal port 7.Reference clock signal input port 1 is convenient to the access of said clock reference generator.Clock enable signal input port 2 receives low effective level signal, and when its input signal enables whole clock generator during for low level, otherwise clock generator do not work, and it is generally and cooperates read-write to come clock-unit's counter is operated.Work index signal port 7 can be connected with LED, and the work indication of clock generator is provided.For some external equipment pulse interrupt need be provided; A pulse interrupt output 8 is provided here; Pulse interrupt output 8 can conveniently be designed to as required with second, branch, the time etc. the carry of various clock-units counter enable output and be connected, output second, branch or the time equal time pulse interrupt.Simultaneously, the pulse interrupt output can also be as output terminal of clock pulse, and the output cycle is 1 microsecond, 10 microsecond isochronon pulse signals.

The above is merely the preferred embodiment of the utility model; Not in order to restriction the utility model; Any modification of being done within all spirit and principles at the utility model, be equal to replacement and improvement etc., all should be included within the protection range of the utility model.

Claims

1. the multifunction timepiece generator based on FPGA is characterized in that, comprises reference clock generator, based on clock-unit's counter of FPGA, based on the read-write controller of FPGA; Has the count pulse input on the said clock-unit counter and carry enables output; Said reference clock generator is connected with the count pulse input of clock-unit's counter; Read-write controller is the read-write interface of clock-unit's counter; The carry of said clock-unit counter enables output as output terminal of clock pulse.

2. a kind of multifunction timepiece generator based on FPGA according to claim 1 is characterized in that, also comprises based on the every month fate determining device of FPGA and leap year determining device based on FPGA;

3. a kind of multifunction timepiece generator based on FPGA according to claim 2 is characterized in that any one carry enables output as output terminal of clock pulse in said each unit clock counter.

4. a kind of multifunction timepiece generator based on FPGA according to claim 2 is characterized in that any one carry enables output as the pulse interrupt output in said each unit clock counter.