CN202159672U - Solar cell silicon chip with low cost - Google Patents

Solar cell silicon chip with low cost Download PDF

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Publication number
CN202159672U
CN202159672U CN 201120288398 CN201120288398U CN202159672U CN 202159672 U CN202159672 U CN 202159672U CN 201120288398 CN201120288398 CN 201120288398 CN 201120288398 U CN201120288398 U CN 201120288398U CN 202159672 U CN202159672 U CN 202159672U
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CN
China
Prior art keywords
silicon
solar cell
silicon layer
base plate
silicon chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 201120288398
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Chinese (zh)
Inventor
陈一鸣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WENZHOU SUOLE NEW ENERGY TECHNOLOGY CO LTD
Original Assignee
WENZHOU SUOLE NEW ENERGY TECHNOLOGY CO LTD
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by WENZHOU SUOLE NEW ENERGY TECHNOLOGY CO LTD filed Critical WENZHOU SUOLE NEW ENERGY TECHNOLOGY CO LTD
Priority to CN 201120288398 priority Critical patent/CN202159672U/en
Application granted granted Critical
Publication of CN202159672U publication Critical patent/CN202159672U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model relates to a solar cell silicon chip with low cost, which comprises a baseplate, wherein a silicon layer is arranged on the baseplate, a transition silicon plate and a metal thin film layer are arranged between the baseplate and the silicon layer, a printed circuit is arranged on the baseplate or the silicon layer, the silicon layer is a porous silicon layer, and the thickness of the porous silicon layer is 100-750mum. The solar cell silicon chip has the benefit of saving material for manufacturing the silicon chip; furthermore, the porous silicon layer is utilized, so that the utilization rate of silicon of a solar cell is higher and the high-purity silicon for manufacturing the solar cell is lower in cost and simple in structure.

Description

The silicon chip of solar cell that cost is low
Technical field
The utility model relates to a kind of silicon chip, especially relates to a kind of silicon chip of solar cell.
Background technology
The silicon materials consumption of existing silicon chip is too big; The utilance of general silicon materials has only about 50%, and silicon chip generally can only reach about 200 microns because that technical limitations can not be cut is very thin; And the actual needed silicon wafer thickness of solar cell only needs about 50 microns; Thick like this silicon chip can cause the utilance of silicon of solar cell very low, thereby the cost of HIGH-PURITY SILICON that is used to make solar cell is very high, and silicon chip is the part of the maximum cost of solar cell; Therefore the utilance of low silicon is the high main cause of solar cell price that present silicon chip is made, thereby has influenced popularizing of solar cell.
The utility model content
The utility model provides the low silicon chip of solar cell of a kind of cost, and it mainly is that to solve the silicon materials consumption of existing in prior technology silicon chip too big, and the utilance of general silicon materials has only the problem about 50%; The utility model has also solved thick silicon chip and can cause the utilance of silicon of solar cell very low, thereby is used to make the very high technical problem of cost of the HIGH-PURITY SILICON of solar cell.
To achieve these goals, the utility model solution technical scheme that its technical problem adopted is:
The silicon chip of solar cell that cost is low comprises base plate, and described base plate is provided with silicon layer, is provided with transition silicon plate and metal film layer between base plate and the silicon layer, and base plate or silicon layer are provided with printed circuit, and described silicon layer is a porous silicon layer,
Porous silicon layer thickness is 100-750um.
The beneficial effect of the utility model: practice thrift to make the material of silicon chip, and utilize porous silicon layer, make that the utilance of silicon of solar cell is higher, thereby the cost of HIGH-PURITY SILICON that is used to make solar cell is lower, simple in structure.
Description of drawings
Fig. 1 is the structural representation of the utility model;
Fig. 2 is the A-A cross-sectional view of Fig. 1 of embodiment 1;
Fig. 3 is the A-A cross-sectional view of Fig. 1 of embodiment 2.
Embodiment
The silicon chip of solar cell that cost is low; Comprise base plate 1, described base plate 1 is provided with silicon layer 2, is provided with transition silicon plate 4 and metal film layer 5 between base plate 1 and the silicon layer 2; Base plate or silicon layer are provided with printed circuit 3; Described silicon layer 2 is a porous silicon layer, and its thickness is 100-750um, and described base plate 1 is the low-purity silicon base plate.
Embodiment 1: the low silicon chip of solar cell of a kind of cost of this example, like Fig. 1, Fig. 2, Jie's base plate 1 is arranged, and base plate is the low-purity silicon base plate.Base plate is provided with silicon layer 2, and silicon layer is a porous silicon layer, and its thickness is 500um.Base plate 1 or silicon layer 2 are provided with printed circuit 3.Be provided with transition silicon plate 4 between base plate 4 and the silicon layer 2.
During use, the utility model solar cell of packing into can be used.
Embodiment 2: the low silicon chip of solar cell of a kind of cost of this example, like Fig. 1, Fig. 3, a base plate 1 is arranged, and base plate is the low-purity silicon base plate.Base plate is provided with silicon layer 2, and silicon layer is a porous silicon layer, and its thickness is 500um.Base plate or silicon layer are provided with printed circuit 3.Be provided with metal film layer 5 between base plate and the silicon layer.
During use, the utility model solar cell of packing into can be used.

Claims (2)

1. the low silicon chip of solar cell of cost comprises base plate (1), it is characterized in that; Described base plate (1) is provided with silicon layer (2); Be provided with transition silicon plate (4) and metal film layer (5) between base plate (1) and the silicon layer (2), base plate or silicon layer are provided with printed circuit (3), and described silicon layer (2) is a porous silicon layer.
2. the low silicon chip of solar cell of cost as claimed in claim 1 is characterized in that porous silicon layer thickness is 100-750um.
CN 201120288398 2011-08-10 2011-08-10 Solar cell silicon chip with low cost Expired - Fee Related CN202159672U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201120288398 CN202159672U (en) 2011-08-10 2011-08-10 Solar cell silicon chip with low cost

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201120288398 CN202159672U (en) 2011-08-10 2011-08-10 Solar cell silicon chip with low cost

Publications (1)

Publication Number Publication Date
CN202159672U true CN202159672U (en) 2012-03-07

Family

ID=45767298

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201120288398 Expired - Fee Related CN202159672U (en) 2011-08-10 2011-08-10 Solar cell silicon chip with low cost

Country Status (1)

Country Link
CN (1) CN202159672U (en)

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120307

Termination date: 20140810

EXPY Termination of patent right or utility model