CN202145666U - VGA/TV signal conversion apparatus - Google Patents
VGA/TV signal conversion apparatus Download PDFInfo
- Publication number
- CN202145666U CN202145666U CN 201120238897 CN201120238897U CN202145666U CN 202145666 U CN202145666 U CN 202145666U CN 201120238897 CN201120238897 CN 201120238897 CN 201120238897 U CN201120238897 U CN 201120238897U CN 202145666 U CN202145666 U CN 202145666U
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- vga
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Abstract
The utility model relates to the field of video conversion technology, in particular to a VGA/TV signal conversion apparatus, comprising a VGA interface, a TV interface, an analog/digital conversion unit, a video coding unit and a processor unit, wherein the video signal input end of the analog/digital conversion unit is electrically connected with the VGA interface, the video signal output end of the analog/digital conversion unit is electrically connected with the video signal input end of the video coding unit, the video signal output end of the video coding unit is electrically connected with the TV interface, and the control end of the analog/digital conversion unit and the video coding unit is electrically connected with the processor unit. The VGA/TV signal conversion apparatus is simple in structure and low in cost, can convert VGA signals into digital TV signals with various standards, and can enable monitoring cost to be reduced by using various display devices.
Description
Technical field
The utility model relates to video switch technology field, particularly a kind of VGA/TV chromacoder.
Background technology
In recent years, along with the fast development of IP network, the video monitoring industry had also got into the full networked epoch.The video monitoring industry in full networked epoch just progressively shows the characteristic of IT industry, as the core product NVR (Network Video Recorder) of networked control, from having become IT product in essence.The topmost function of NVR is to receive the digital video bit stream of IPC (web camera), DVS device transmission such as (video encoders) through network, and stores, manages.
In engineering, there is a large amount of display devices, comprise simulated television, LCD TV; Various LCDs are for compatible these equipment, through the present invention; With the VGA conversion of signals is the TV signal, can effectively utilize these outmoded equipment, helps cost control.
VGA/TV chromacoder simple in structure, with low cost is not also arranged in the prior art.
The utility model content
In view of this,, the utility model discloses a kind of VGA/TV chromacoder, can the VGA conversion of signals be become the digital TV signal of various standards in order to address the above problem.
The purpose of the utility model is achieved in that the VGA/TV chromacoder; Comprise VGA interface, TV interface, A/D converter, video encoding unit and processor unit; The video signal input terminal of said A/D converter is electrically connected with the VGA interface; The VT of A/D converter is electrically connected with the video signal input terminal of video encoding unit; The VT of video encoding unit is electrically connected with the TV interface, and the control end of A/D converter and video encoding unit is electrically connected with processor unit.
Said A/D converter comprises three programmable-gain control digital to analog converters compositions and phase-locked loop of mutual electrical connection.
Said processor unit is the MCU microcontroller.
The beneficial effect of the utility model is following: the VGA/TV chromacoder of the utility model is simple in structure, with low cost, can the VGA conversion of signals be become the digital TV signal of various standards, to utilize various display devices, reduces monitoring cost.
Description of drawings
For the purpose, technical scheme and the advantage that make the utility model is clearer, will combine accompanying drawing that the utility model is done further to describe in detail below:
Fig. 1 shows the structural representation of VGA/TV chromacoder;
Fig. 2 shows the schematic flow sheet of VGA/TV chromacoder software section.
Embodiment
Below will carry out detailed description to the preferred embodiment of the utility model.
The VGA/TV chromacoder; Comprise VGA interface, TV interface, IC_1: A/D converter, IC_2: video encoding unit and processor unit; The video signal input terminal of said A/D converter is electrically connected with the VGA interface; The VT of A/D converter is electrically connected with the video signal input terminal of video encoding unit; The VT of video encoding unit is electrically connected with the TV interface, and the control end of A/D converter and video encoding unit is electrically connected with processor unit.Said A/D converter comprises three programmable-gain control digital to analog converters compositions and phase-locked loop of mutual electrical connection; Be to convert the input of RGB analog signal the output of into 8-bit numeral; Support the 1080P video format; Said phase-locked loop can provide high accuracy, low jitter, and 12MHz is to the pixel clock of 150MHz.Said video encoding unit receives the digital signal of A/D converter output, encodes, and passes through the transfer of data of 10 DAC; The vision signal that produces of can encoding and for 480p, 576p, the SD signal Synchronization of 720p and 1080i is used for the form of NTSC and pal mode and high-definition format; Analog rgb output and composite synchronizing signal are also supported.This device accept to comprise RGB and YCbCr (like RGB565, RGB666, RGB888, as the I TU656 etc. of YCbCr) different data formats; Support two interlacing scans and the input data format of lining by line scan; Has 16MSDRAM; Support frame-rate conversion, image rotation, convergent-divergent, convergent-divergent etc.Said processor unit is the MCU microcontroller, is used to carry out the setting of corresponding registers.
Software section in the utility model VGA/TV chromacoder; It is the program that defaults among the MCU; Adopt the C language, in store various configuration data in the memory block is according to the refresh rate and the line synchronizing signal that detect VGA output signal; Judge the size form of video output, and then IC_1 (A/D converter) and IC_2 (video encoding unit) are done corresponding configuration.MCU also is responsible for the control of reset signal.
At first, program resets, and initialization operation.Reset to IC_1, IC_2 carries out reset operation, and initialization makes it reach operating state to the inner various peripheral configuration of MCU.
Next be configuration IC_1, the parameter of IC_2 chip, the result who judges according to next procedure does corresponding configuration, in the time of for the first time, can carry out default configuration to it.
Getting off is exactly refresh rate and the resolution that detects the VGA signal again, through the measurement to frequency, and then learns corresponding refresh rate and resolution.
Be refresh rate and the resolution of judging that current detection arrives at last, whether mate with the value of nearest last time.If coupling explains that configuration does not need to change, program forwards continuation to and " detects the refresh rate and the resolution of VGA signal ".If do not match, explain that configuration needs to change, program forwards " configuration IC_1, the parameter of IC_2 chip " to.
According to such circulation, operation is always gone down, and up to system closedown, stops using.
What the above was merely the utility model preferably is not limited to the utility model, and obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and the scope of the utility model the utility model.Like this, belong within the scope of the utility model claim and equivalent technologies thereof if these of the utility model are revised with modification, then the utility model also is intended to comprise these changes and modification interior.
Claims (3)
1.VGA/TV chromacoder; It is characterized in that: comprise VGA interface, TV interface, A/D converter, video encoding unit and processor unit; The video signal input terminal of said A/D converter is electrically connected with the VGA interface; The VT of A/D converter is electrically connected with the video signal input terminal of video encoding unit; The VT of video encoding unit is electrically connected with the TV interface, and the control end of A/D converter and video encoding unit is electrically connected with processor unit.
2. VGA/TV chromacoder as claimed in claim 1 is characterized in that: said A/D converter comprises three programmable-gain control digital to analog converters compositions and phase-locked loop of mutual electrical connection.
3. according to claim 1 or claim 2 VGA/TV chromacoder, it is characterized in that: said processor unit is the MCU microcontroller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120238897 CN202145666U (en) | 2011-07-07 | 2011-07-07 | VGA/TV signal conversion apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120238897 CN202145666U (en) | 2011-07-07 | 2011-07-07 | VGA/TV signal conversion apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202145666U true CN202145666U (en) | 2012-02-15 |
Family
ID=45581588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120238897 Expired - Fee Related CN202145666U (en) | 2011-07-07 | 2011-07-07 | VGA/TV signal conversion apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202145666U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106534840A (en) * | 2016-10-31 | 2017-03-22 | 青岛海信电器股份有限公司 | Video signal detection method and device |
-
2011
- 2011-07-07 CN CN 201120238897 patent/CN202145666U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106534840A (en) * | 2016-10-31 | 2017-03-22 | 青岛海信电器股份有限公司 | Video signal detection method and device |
| CN106534840B (en) * | 2016-10-31 | 2018-10-26 | 青岛海信电器股份有限公司 | The detection method and device of vision signal |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120215 Termination date: 20190707 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |