CN202135138U - MCTP clock adjusting device - Google Patents
MCTP clock adjusting device Download PDFInfo
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- CN202135138U CN202135138U CN201120226130U CN201120226130U CN202135138U CN 202135138 U CN202135138 U CN 202135138U CN 201120226130 U CN201120226130 U CN 201120226130U CN 201120226130 U CN201120226130 U CN 201120226130U CN 202135138 U CN202135138 U CN 202135138U
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Abstract
The present utility model relates to an MCTP clock adjusting device. The device comprises a line clock obtaining module, an FIFO buffer, a read-write module, a clock frequency difference module, an invalid data length module and a data frame setting module. The line clock obtaining module is used for obtaining a line clock; the read-write module is used for utilizing the line clock to write data of a data frame into the FIFO buffer, and utilizing a local clock to read the data from the FIFO buffer; the clock frequency difference module is used for calculating the clock frequency difference between the line clock and the local clock; the invalid data length module is used for determining the length of invalid data added into or deleted from the data frame; and the data frame setting module is used for setting the local sending data frame. By adopting the technical scheme, the process of using a reference clock to carry out the clock synchronization of MCTP nodes is avoided, and the problem of limited network node number caused by clock error accumulation of clock synchronization of the nodes can be avoided, and the device is very suitable and practical.
Description
Technical field
The utility model relates to the clock adjustment technology, particularly relates to the clock adjusting device of Multi-Channel Transmission Platform (multichannel transmission platform).
Background technology
The clock adjustment technology is a kind of technology commonly used in the communication network, and clock synchronization is a kind of technology commonly used in the clock adjustment technology.
Clock synchronization also is " to clock ", and clock synchronization can be the clock alignment that is distributed in each node (synchronously promptly).Clock synchronization method the most intuitively is exactly a clock transportation, a concrete example: use a standard time clock (being reference clock) to make clock transportation, the clock of each node is all aimed at standard time clock; The example that another is concrete: clock transportation is at first aimed at the standard time clock of system, then, made other hour hands and the clock transportation comparison in the system, thereby make standard time clock unified in other clocks and the system in the system synchronous.
The inventor finds in realizing the utility model process: in the clock synchronization implementation procedure based on standard time clock; Each node is consistent the clock of this node and the clock of a last node through utilizing Phase Lock Technique; Like this, the clock of each node in the whole system can be consistent with reference clock.Yet,, may cause the paralysis of whole network if the reference clock in the network breaks down.In addition,, therefore, there is the frequency deviation of clock accumulation phenomenon in the network, makes that thus the number of nodes in the network can be restricted owing to can not there be certain deviation in the clock of each node with the clock of a last node is identical.
Because the defective that above-mentioned existing Clock Synchronization Technology exists; The inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge; And cooperate the utilization of scientific principle, actively study innovation, in the hope of the clock adjusting device of the MCTP that founds a kind of new structure; Can overcome the problem that existing Clock Synchronization Technology exists, make it have more practicality.Through constantly research, design, and, found out the utility model of true tool practical value finally through after studying sample and improvement repeatedly.
The utility model content
The purpose of the utility model is; Overcome the defective that existing Clock Synchronization Technology exists; And the clock adjusting device of the MCTP of a new structure is provided, technical problem to be solved is, avoids taking place the phenomenon of the whole network paralysis that the reference clock fault causes; And avoid number of nodes in the occurring network to receive the phenomenon of the restriction of the frequency deviation of clock accumulation in the clock synchronization process, be very suitable for practicality.
The purpose of the utility model and solve its technical problem and can adopt following technical scheme to realize.
The clock adjusting device of a kind of MCTP that proposes according to the utility model comprises: the line clock acquisition module, receive the Frame that the upper reaches MCTP node in the network sends, and the line clock that from said Frame, obtains of output; The first in first out buffer; Module for reading and writing; Be connected with said first in first out buffer with said line clock acquisition module; Said module for reading and writing utilizes said line clock in the first in first out buffer, to write the data in the said Frame, and utilizes local clock reading of data from said first in first out buffer; Clock frequency differential mode piece is connected with said module for reading and writing, and the said line clock that output is calculated based on the speedometer of the speed that writes data of said first in first out buffer and reading of data and the clock frequency of said local clock are poor; Invalid data length module is connected with said clock frequency differential mode piece, the length of the invalid data that the said Frame that output is determined based on said clock frequency difference should increase/delete; Frame is provided with module, is connected this locality transmission Frame that output is provided with based on the length of the invalid data of said increase/deletion with said invalid data length module.
Preferable; The clock adjusting device of aforesaid MCTP; Wherein said module for reading and writing comprises: write submodule, be connected with the first in first out buffer with said line clock acquisition module, the said submodule of writing utilizes said line clock in the first in first out buffer, to write the data in the said Frame; Read submodule, be connected with said first in first out buffer, said when reading submodule and in said first in first out buffer, including the data of predetermined bite, utilize local clock reading of data from said first in first out buffer.
Preferable; The clock adjusting device of aforesaid MCTP, wherein said module for reading and writing also comprises: insert submodule, be connected with said first in first out buffer; In the first in first out buffer, write in the process of the data in the said Frame writing submodule; When reading submodule and reading sky, in said first in first out buffer, inserted invalid data by said at said first in first out buffer, in said first in first out buffer, include the data of predetermined bite.
By technique scheme; The clock adjusting device of the MCTP of the utility model has advantage and beneficial effect at least: the utility model is poor through the clock frequency that writing rate and reading rate according to FIFO calculate between line clock and the local clock; And the local included invalid data in the Frame that sends is set according to this clock frequency difference, the MCTP node in the network can be sent the Frame that upper reaches MCTP node sends in its unit interval according to its local clock in its unit interval; Clock in the network of the utility model forms a kind of structure of distributed clock thus; Not only avoided the MCTP node need carry out the process of clock synchronization with reference clock; Also having avoided each node is to carry out the limited problem of number of nodes in the network that clocking error accumulation that clock synchronization produces caused; Thereby the utility model can effectively improve the robustness of network, and improves the expandability of network, is very suitable for practicality.
In sum, the utility model is realizing technical obvious improvement being arranged, and has tangible good effect, really is a novelty, progress, practical new design.
Above-mentioned explanation only is the general introduction of the utility model technical scheme; In order more to know the technological means of understanding the utility model; And can implement according to the content of specification, and for let the above-mentioned of the utility model with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Fig. 1 is the clock adjusting device sketch map of the MCTP of the utility model;
Fig. 2 is the clock adjustment process sketch map of clock adjusting device of the MCTP of the utility model;
Fig. 3 is the Frame sketch map of the utility model;
Fig. 4 is the structure principle chart of clock adjusting device of the MCTP of the utility model.
Embodiment
For further setting forth the utility model is to reach technological means and the effect that predetermined utility model purpose is taked; Below in conjunction with accompanying drawing and preferred embodiment; To its embodiment of clock adjusting device, structure, characteristic, step and the effect of the MCTP that proposes according to the utility model, specify as after.
Fig. 1 is the clock adjusting device sketch map of MCTP.This device is arranged in the MCTP node.
Device shown in Fig. 1 comprises: line clock acquisition module 1, first in first out buffer 2, module for reading and writing 3, clock frequency differential mode piece 4, invalid data length module 5, Frame are provided with module 6.
Line clock acquisition module 1 is mainly used in the Frame that the upper reaches MCTP node from network (like the gigabit ethernet ring network) sends and obtains line clock.
Line clock acquisition module 1 can adopt existing clock extraction method from this Frame, to recover line clock (line clock is the local clock of upper reaches MCTP node) after local MCTP node receives the Frame that upper reaches MCTP node sends, and the utility model does not limit the concrete implementation that line clock acquisition module 1 obtains line clock.
The Frame that the upper reaches MCTP node that local MCTP node receives sends comprises: valid data and invalid data.The length of valid data wherein can allow the clock accuracy of the local clock of MCTP node to set according to network.It is the local clock of the MCTP node that allows of network and the frequency deviation of clock maximum between the preset clock that network allows the clock accuracy of the local clock of MCTP node.Thereby have certain precision as long as guarantee the local clock of each the MCTP node in the network, then the valid data in the Frame just can obtain correct transmission in network.
First in first out buffer 2 in the utility model is an asynchronous FIFO.
Module for reading and writing 3 is mainly used in and utilizes line clock in first in first out buffer 2, to write the data in the Frame, and utilizes local clock reading of data from first in first out buffer 2.
Concrete; The line clock that module for reading and writing 3 can utilize line clock acquisition module 1 to recover writes the valid data in its Frame that receives in FIFO; Certainly, the valid data and the invalid data that in FIFO, write in its Frame that receives also are feasible.For avoiding invalid read operation, module for reading and writing 3 can utilize local clock reading of data from FIFO again after utilizing its line clock that recovers in FIFO, to write the data of predetermined bite.The local clock here is the local clock of module for reading and writing 3 place MCTP nodes.
Above-mentioned predetermined bite can be set according to the precision of the clock frequency of the local clock of each MCTP node that network allowed; Concrete example: under the situation of precision in 125M ± 50ppm scope of the clock frequency of the local clock of each MCTP node that network allowed; Frame length is that the invalid data that 1920 bytes then increase/delete is that 1 byte gets final product, and actually can the invalid data predetermined bite be set to 12 bytes.
Because module for reading and writing 3 is to utilize line clock in first in first out buffer 2, to write valid data; And utilize local clock from first in first out buffer 2, to read valid data; After writing 6 byte valid data in the first in first out buffer 2, begin to read; After module for reading and writing 3 runs through this frame valid data, insert invalid data and in first in first out buffer 2, write 6 byte valid data up to next frame, and the local clock of line clock and MCTP node and inequality, therefore; If under the situation of the reading speed of first in first out buffer 2 greater than the writing speed of first in first out buffer 2; The invalid data that module for reading and writing 3 inserts is many, if instead under the situation of the reading speed of first in first out buffer 2 less than the writing speed of first in first out buffer 2, the invalid data that module for reading and writing 3 inserts is just few.
It is poor that clock frequency differential mode piece 4 is mainly used in according to the clock frequency of the speed calculation line clock of the speed that writes data of first in first out buffer 2 and reading of data and local clock.
Concrete; Clock frequency differential mode piece 4 can be according to the speed that writes data that data conditions obtains FIFO that writes of FIFO; And clock frequency differential mode piece 4 can obtain the speed of the sense data of FIFO according to the situation of the sense data of FIFO; Thus, clock frequency differential mode piece 4 can be on the basis based on the speed of the speed that writes data of FIFO and sense data, and the clock frequency that adopts existing certain account form to calculate line clock and local clock is poor.
Invalid data length module 5 is mainly used in the length of the invalid data that should increase/delete according to clock frequency difference specified data frame.
Concrete; Invalid data length module 5 can still be the invalid data that reduces respective numbers according to the invalid data that the clock frequency difference confirms on the basis of the Frame that receives, to increase respective numbers; To guarantee that Frame that upper reaches MCTP node sends is after local MCTP node place is through the processing of increases/deletion invalid data in its unit interval; Can in its unit interval, be sent by local MCTP node equally, thereby make local MCTP node and upper reaches MCTP nodal clock synchronous.
Frame is provided with the length that module 6 is mainly used in according to the invalid data of increase/deletion the local Frame that sends is set.
Above-mentioned module for reading and writing 3 can specifically comprise: write submodule 31, read submodule 32 and insert submodule 33.
Writing submodule 31 is mainly used in and utilizes line clock in the first in first out buffer, to write the data in the Frame.
After reading submodule 32 and being mainly used in the data that in judging the first in first out buffer, include predetermined bite, utilize local clock reading of data from said first in first out buffer.
Inserting submodule 33 is mainly used in and in first in first out buffer 2, writes in the process of the data in the Frame writing submodule 31; When first in first out buffer 2 is read submodule and is read sky; In first in first out buffer 2, insert invalid data, in first in first out buffer 2, include the data of predetermined bite.
Clock adjusting device below in conjunction with 3 couples of MCTP of accompanying drawing 2 to accompanying drawing describes.
In the gigabit ethernet ring network, be under the situation of 8bit at data bit width, if the local clock of website A (being MCTP node A) is 125M, then website A can send 125 * 10 in its unit interval
6* 8=1000,000, the data of 000bit; If the local clock of website B (being the MCTP Node B) is 125M+10ppm, then website B can send 125 * 10 in its unit interval
6* (1+10 * 10
-6) * 8=1000,010, the data of 000bit; If the local clock of website C (being MCTP node C) is 125M-20ppm, then website C can send 125 * 10 in its unit interval
6* (1-20 * 10
-6) * 8=999,980, the data of 000bit.
Under above-mentioned application scenarios, 1000,000, the data of 000bit when process website B and website C return website A respectively, can be lost a part of data after website A sends out.For avoiding losing of valid data, carry a part of invalid data in the data that website A can send in its unit interval.The precision of the clock frequency that allows at network is that the concrete example that the clock 125M ± 50ppm scope in is adjusted is: website A in the unit interval, send 1000,000, include 999 in the data of 000bit; 900, the valid data of 000bit and 100, the invalid data of 000bit; Like this, after website B receives the data that website A sends, because the local clock of website B is faster than receive clock (being line clock) frequency; Therefore, the data in the unit interval, sent of website B are 999,900; The valid data of 000bit and 110, the invalid data of 000bit; After website C received the data that website B sends, because the local clock of website C is slower than receive clock frequency, therefore, the data that website C sent in the unit interval were 999,900, the valid data of 000bit and 80, the invalid data of 000bit; Thus, the data that website A receives are 999,900, the valid data of 000bit and 80, the invalid data of 000bit.
Can know by above-mentioned concrete example: no matter the data that website A sends are through how many websites; As long as the local clock accuracy guarantee of each website is in 125M ± 50ppm scope; Then the valid data that in its unit interval separately, sent of each website can not change, thereby have guaranteed the correct transmission of valid data.
The clock adjusting device that the clock adjustment process sketch map of the clock adjusting device of the MCTP of Fig. 2 has illustrated the MCTP among the website n is to two processing procedures of uplink and downlink of its data that receive in the unit interval.At first, extract line clock n-1 the Frame (valid data and IGPn-1 invalid data of comprising predetermined length) that the line clock acquisition module 1 among the website n sends from website n-1; Afterwards, the module for reading and writing 3 among the website n utilizes the significant figure in this line clock n-1 sends website n-1 in the unit interval the Frame to write among its FIFO, and this FIFO is an asynchronous FIFO; Module for reading and writing 3 among the website n utilizes its local clock reading of data from FIFO; The data that website n will be read out carry out being sent to the downlink data bus after the descending time slot control and treatment (processing procedure that comprises clock frequency differential mode piece 4 invalid data length modules 5), thereby the data that are read out are in website n internal transmission.Website n carries out ascending time slot control and treatment (comprising that Frame is provided with the processing procedure of module 6) to the data in the upstream data bus; Afterwards; The Frame that website n buffer memory ascending time slot control and treatment produces is to continue to send this Frame downstream; Include the valid data and the individual invalid data of IGPn (invalid data) of predetermined length in the data in buffer frame, the line clock n of this Frame is the local clock of website n.Above-mentioned IGPn and IGPn-1 can the (IGPn-1＞IGPn shown in Fig. 2 inequality; Be the clock frequency that the clock frequency of the local clock of website n-1 is higher than the local clock of website n); Thus; The frame length of the Frame that website n-1 sends is inequality with the frame length of the Frame that website n sends, and the bandwidth that each bit carried in the Frame of the bandwidth that each bit carried in the Frame that sends of website n-1 and website n transmission equates, and then has realized the clock synchronization of website n and website n-1.
Fig. 3 is the Frame sketch map that certain website in the utility model sends.The frame length of the Frame shown in the figure is that 15360bit, valid data are that 15256 bits, invalid data are 104bit.
Fig. 6 is the structure principle chart of the clock adjusting device of the utility model MCTP; The transceiving integrated module of optical fiber adopts the OCM3821 device to realize among the figure; Gigabit ethernet ring network gateway end adopts the BCM5464 chip to realize, utilizes fpga chip EP2S3QF4184 and 125MHz crystal oscillator to realize the function of the required realization of MCTP clock adjusting device.
The above only is the preferred embodiment of the utility model; Be not that the utility model is done any pro forma restriction; Though the utility model discloses as above with preferred embodiment; Yet be not in order to limit the utility model; Any professional and technical personnel of being familiar with makes a little change or is modified to the equivalent embodiment of equivalent variations when the technology contents of above-mentioned announcement capable of using in not breaking away from the utility model technical scheme scope, is the content that does not break away from the utility model technical scheme in every case;, all still belong in the scope of the utility model technical scheme any simple modification, equivalent variations and modification that above embodiment did according to the technical spirit of the utility model.
Claims (3)
1. the clock adjusting device of a MCTP is characterized in that, comprising:
The line clock acquisition module receives the Frame that the upper reaches MCTP node in the network sends, and exports the line clock that from said Frame, obtains;
The first in first out buffer;
Module for reading and writing; Be connected with said first in first out buffer with said line clock acquisition module; Said module for reading and writing utilizes said line clock in the first in first out buffer, to write the data in the said Frame, and utilizes local clock reading of data from said first in first out buffer;
Clock frequency differential mode piece is connected with said module for reading and writing, and the said line clock that output is calculated based on the speedometer of the speed that writes data of said first in first out buffer and reading of data and the clock frequency of said local clock are poor;
Invalid data length module is connected with said clock frequency differential mode piece, the length of the invalid data that the said Frame that output is determined based on said clock frequency difference should increase/delete;
Frame is provided with module, is connected this locality transmission Frame that output is provided with based on the length of the invalid data of said increase/deletion with said invalid data length module.
2. the clock adjusting device of MCTP as claimed in claim 1 is characterized in that, said module for reading and writing comprises:
Write submodule, be connected with the first in first out buffer with said line clock acquisition module, the said submodule of writing utilizes said line clock in the first in first out buffer, to write the data in the said Frame;
Read submodule, be connected with said first in first out buffer, said when reading submodule and in said first in first out buffer, including the data of predetermined bite, utilize local clock reading of data from said first in first out buffer.
3. the clock adjusting device of MCTP as claimed in claim 2 is characterized in that, said module for reading and writing also comprises:
Insert submodule; Be connected with said first in first out buffer; In the first in first out buffer, write in the process of the data in the said Frame writing submodule; When reading submodule and reading sky, in said first in first out buffer, inserted invalid data by said at said first in first out buffer, in said first in first out buffer, include the data of predetermined bite.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120226130U CN202135138U (en) | 2011-06-29 | 2011-06-29 | MCTP clock adjusting device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120226130U CN202135138U (en) | 2011-06-29 | 2011-06-29 | MCTP clock adjusting device |
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| CN202135138U true CN202135138U (en) | 2012-02-01 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237942A (en) * | 2011-06-29 | 2011-11-09 | 北京阳光金力科技发展有限公司 | Clock regulation method and device for multi-channel transmission platform (MCTP) |
| CN106911545A (en) * | 2017-01-23 | 2017-06-30 | 北京东土军悦科技有限公司 | A kind of method and device that ST_BUS data are transmitted by Ethernet |
| CN111124997A (en) * | 2019-12-25 | 2020-05-08 | 海光信息技术有限公司 | Data sending method, data receiving method, data sending device, data receiving device, processor chip and server |
| CN114449192A (en) * | 2020-11-04 | 2022-05-06 | 格科微电子（上海）有限公司 | Virtual active image acquisition equipment and data transmission method, storage medium and terminal thereof |
-
2011
- 2011-06-29 CN CN201120226130U patent/CN202135138U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237942A (en) * | 2011-06-29 | 2011-11-09 | 北京阳光金力科技发展有限公司 | Clock regulation method and device for multi-channel transmission platform (MCTP) |
| CN106911545A (en) * | 2017-01-23 | 2017-06-30 | 北京东土军悦科技有限公司 | A kind of method and device that ST_BUS data are transmitted by Ethernet |
| CN106911545B (en) * | 2017-01-23 | 2020-04-24 | 北京东土军悦科技有限公司 | Method and device for transmitting ST _ BUS data through Ethernet |
| CN111124997A (en) * | 2019-12-25 | 2020-05-08 | 海光信息技术有限公司 | Data sending method, data receiving method, data sending device, data receiving device, processor chip and server |
| CN111124997B (en) * | 2019-12-25 | 2021-07-23 | 海光信息技术股份有限公司 | Data sending method, data receiving method, data sending device, data receiving device, processor chip and server |
| CN114449192A (en) * | 2020-11-04 | 2022-05-06 | 格科微电子（上海）有限公司 | Virtual active image acquisition equipment and data transmission method, storage medium and terminal thereof |
| CN114449192B (en) * | 2020-11-04 | 2024-02-27 | 格科微电子（上海）有限公司 | Virtual active image acquisition device, data transmission method thereof, storage medium and terminal |
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