CN202127352U - Green power inverter - Google Patents

Green power inverter Download PDF

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CN202127352U
CN202127352U CN2010201450421U CN201020145042U CN202127352U CN 202127352 U CN202127352 U CN 202127352U CN 2010201450421 U CN2010201450421 U CN 2010201450421U CN 201020145042 U CN201020145042 U CN 201020145042U CN 202127352 U CN202127352 U CN 202127352U
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郁百超
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Abstract

The utility model discloses a power inverter. A field effect tube Q1 of a unit circuit is an N channel; a field effect tube Q2 is a P channel; a positive pole of a diode D1 is connected with a negative pole of a diode D2 to form an end point A; a drain of the field effect tube Q1 is connected with the negative pole of the diode D1; a source of the field effect tube Q1 is connected with an end point B; the drain of the field effect tube Q2 is connected with the positive pole of the diode D2; the source of the field effect tube Q2 is connected with the end point B; a grid of the field effect tube Q1 is connected with the positive pole of a driving signal V1; the negative pole of the driving signal V1 is connected with the end point B; the grid of the field effect tube Q2 is connected with the negative pole of the driving signal V2; and the positive pole of the driving signal V2 is connected with the end point B. By adopting the utility model, a PWM (pulse width modulation) technology in a traditional power converter is avoided; no power component working at high frequency is arranged in a main circuit, so that EMI (Electro-Magnetic Interference) is not caused; meanwhile, technologies of SBP (symmetry basic primitive), AHM (amplitude height modulation) and DR (dynamic rectification) are adopted, so that very small part of the input power is used for traditional power conversion to obtain the overall output power.

Description

The green power converter
Technical field
The present invention relates to a kind of power inverter.
Background technology
The pulse-width modulation PWM technology is adopted in the conventional power conversion, complicated circuit, adjustment difficulty; All power devices all are operated in high-frequency range, produce strong EMI and disturb, and make the sine voltage of electrical network output seriously distort; Be the greatest contamination source of electric power network, if there is not conventional power converters, then the electric power network world will be a slice blue sky; Except the input or the disconnection of power consumption equipment, other pollutant sources never again.
Whole input powers of conventional power conversion must just can become power output through Power Conversion, and the power of all conversion must pass through core transformers, could arrive output; Input power is carried out the conventional power conversion, means that cost, volume, weight, the more of power consumption of equipment drop into and pay, and the power of conversion means the loss of electrical power through core transformers.
Conventional power converters overall efficiency about 85%; About power factor PFC60%, efficient is low to be the inevitable outcome of carrying out the conventional power conversion, the order of severity that the low explanation of power factor is polluted; Statement of facts, the conventional power converters power consumption is big, efficient is low, not environmental protection, dangerous.
Summary of the invention
Guarantee that electric power network avoids polluting, just can not carry out the conventional power conversion, do not carry out the conventional power conversion, just do not have computer, do not have TV, even also do not have street lamp, then our world will become gloomy.Modern society's civilization and progress, colourful, do not carry out Power Conversion, be impossible, so we sacrifice a slice blue sky in the electric power network world, exchange the colourful of modern society for.The objective of the invention is: should keep the civilization and progress of modern society and colourful, go back a slice blue sky in the electric power network world again, promptly should carry out Power Conversion, electric power network is not produced again and pollute, and conversion efficiency can reach more than 98%.
The present invention adopts following technical scheme:
A kind of power inverter comprises element circuit, it is characterized in that:
The FET Q1 of element circuit is the N raceway groove, and FET Q2 is the P raceway groove; The positive pole of diode D1 links to each other with the negative pole of diode D2, constitutes terminal A, and the drain electrode of FET Q1 links to each other with the negative pole of diode D1; Its source electrode connects terminal B, and the drain electrode of FET Q2 links to each other with the positive pole of diode D2, and its source electrode connects terminal B; The grid of FET Q1 connects the positive pole of drive signal V1; The negative pole of drive signal V1 connects terminal B, and the grid of FET Q2 connects the negative pole of drive signal V2, and the positive pole of drive signal V2 connects terminal B.
Further, comprise basic circuit, it is characterized in that:
Basic circuit is made up of said units circuit and resistance R 1, and the terminal A of element circuit connects the live wire of input voltage vin, and resistance R 1 is connected between the terminal B of zero line and element circuit of input voltage vin, and the terminal B of element circuit is exactly the output of basic circuit; Between the terminal B of element circuit and ground, can also connect boost capacitor network (UPnet) and decompression capacitor network (DNnet), replace resistance R 1;
Further, comprise the active rectification circuit, it is characterized in that:
The active rectification circuit is made up of said units circuit and two resistance R 1, R2; Two FET Q1 of element circuit, the source electrode of Q2 separate, and the end of the source electrode connecting resistance R1 of FET Q1 constitutes exit point P+; The end of the source electrode connecting resistance R2 of FET Q2; Constitute exit point N-,, another termination exit point N of resistance R 1, R2, the terminal A of element circuit constitutes input endpoint L.
Described drive signal V1, V2 are produced by high-frequency driving signal generator (VDrvh) and synchronized signal generator (VDrvs):
1) high-frequency driving signal generator (VDrvh) is made up of integrated circuit NE555 and signal conversion circuit (SPrs), DC power supply V3, V4 series connection, middle ground; The negative pole of direct voltage V3 connects pin GND, the capacitor C 1 of NE555, the end of C2; The positive pole of direct voltage V4 meets pin Vcc, the Reset of NE555, an end of resistance R 7, the pin Thresh of another termination NE555 of capacitor C 1, the pin Cntrl of another termination NE555 of capacitor C 2; The pin Dis of another termination NE555 of resistance; The positive pole of diode D1 meets the pin Dis of NE555, and its negative pole meets the pin Trig of NE555, diode D2 and resistance R 6 series connection; The positive pole of diode D2 meets the pin Thresh of NE555; The pin Dis of another termination NE555 of diode D6, the pin Out of NE555 meets the end points IN of signal conversion circuit SPrs, the end points GND ground connection of signal conversion circuit SPrs through resistance R 3;
2) synchronized signal generator (VDrvs) is made up of integrated circuit LM339 and signal conversion circuit (SPrs); DC power supply V4, V5 series connection, middle ground, the negative pole of direct voltage V4 connect the supply pin of LM339-; The positive pole of direct voltage V5 connect the supply pin of LM339+with an end of resistance R 8; The exit point Gc of another termination LM339 of resistance R 8, an end ground connection of the negative pole of power supply V3 and resistance R 6, the homophase input pin of another termination LM339 of resistance R 6+; The positive pole of power supply V3 through resistance R 7 connect the homophase input pin of LM339+; Anti-phase input pin-ground connection of LM339, the exit point Gc of LM339 meets the end points IN of signal conversion circuit SPrs, the end points GND ground connection of signal conversion circuit (SPrs) through resistance R 3;
3) signal conversion circuit (SPrs) is made up of optocoupler U1, U2, and the diode of optocoupler U1 negative electrode partly meets input endpoint IN, and its anode meets end points GND; The triode of optocoupler U1 emitter partly connects the negative pole of power supply V2 through resistance; Connect the collector electrode of triode Q2 simultaneously, the triode of optocoupler U1 collector electrode partly connects the positive pole of power supply V1, connects the collector electrode of triode Q1 simultaneously;, triode Q1, Q2 emitter be connected together and constitute exit point Gb, meet end points GND through resistance R 2 simultaneously; The diode of optocoupler U2 anode partly meets input endpoint IN; Its negative electrode meets end points GND, and the triode of optocoupler U2 emitter partly connects the negative pole of power supply V2 through resistance, connects the collector electrode of triode Q4 simultaneously; The triode of optocoupler U2 collector electrode partly connects the positive pole of power supply V1; Connect the collector electrode of triode Q3 simultaneously,, the emitter of triode Q3, Q4 is connected together and constitutes exit point Ga, meets end points GND through resistance R 5 simultaneously.
Described boost capacitor network (UPnet) and decompression capacitor network (DNnet) are made up of N rank capacitance network, two arms about every rank all have:
1) left arm of boost capacitor network (UPNet): the negative electrode of diode D1 connects an end of capacitor C 1; Form the starting point Begin1 on these rank, the anode of another terminating diode D3 of capacitor C 1 and the drain electrode of FET Q2, the source electrode of FET forms the terminal point End1 on these rank; The anode of diode connects the input positive source; The negative electrode of diode connects the input power cathode, the right arm of boost capacitor network (UPNet): the anode of diode D2 connects an end of capacitor C 2, forms the starting point Begin2 on these rank; The negative electrode of another terminating diode D4 of capacitor C 2 and the drain electrode of FET Q1; The source electrode of FET Q1 is formed the terminal point End2 on these rank, and the negative electrode of diode connects the input power cathode, and the anode of diode connects the input positive source;
2) left arm of decompression capacitor network (DNnet): the anode of diode D1 connects an end of capacitor C 1, forms the terminal B egin1 on these rank, the negative electrode of another terminating diode D3 of capacitor C 1; Form the end points End1 on these rank, the negative electrode of diode connects the positive pole of output voltage, and the anode of diode connects the negative pole of output voltage; The right arm of decompression capacitor network (DNnet): the negative electrode of diode D2 connects an end of capacitor C 2; Form the terminal B egin2 on these rank, the negative electrode of another terminating diode D4 of capacitor C 2 forms the end points End2 on these rank; The anode of diode connects the negative pole of output voltage, and the negative electrode of diode D4 connects the positive pole of output voltage; The end points End of last single order meets down the terminal B egin of single order, forms multistage boost capacitor network and multistage decompression capacitor network; Envelope is sinusoidal wave square wave driving signal (VEnvl).
The present invention is made up of three kinds of basic circuit SBP-A, SBP-B, SBP-C; Three kinds of basic circuits all are made up of symmetrical primitive SBP (Symmetry Basic Primitive); Three kinds of basic circuits combine panel heights modulation AHM (Amplitude High Modulate) and active rectification DR (Dynamic rectification), can independence or the completion that cooperatively interacts known with potential various Power Conversions.
The present invention has exempted the pulse-width modulation PWM technology in the conventional power converters, and main circuit does not have the power device of high-frequency work, does not produce EMI and disturbs; Adopt symmetrical primitive SBP, panel height modulation AHM and active rectification DR technology simultaneously, only needed to carry out the conventional power conversion to the very little some in the input power, just can obtain whole power outputs; The exhausted major part that is power output both needn't be carried out the conventional power conversion; Also needn't pass through core transformers, the alternating voltage of input needn't rectifying and wave-filtering, does not have big inductance, big electric capacity; Therefore power factor is 1, and total harmonic distortion THD is zero; Transformer is paid the limit and is adopted active rectification, can obtain DC circuit, also can obtain alternating voltage, and the circuit complexity of complete machine, power loss and failure rate all greatly reduce.
The present invention can replace the application of conventional power converters at all spectra, and range of application only limits to each one imagination space and understandability, comprising:
Figure DEST_PATH_GSB00000648644700031
With regard to conventional power converters; Friendship-friendship arranged, hand over-straight, straight-as to hand over, straight-straight four big types; The circuit topography of every big type power inverter is different fully; Even if same big type power inverter, as directly-straight power inverter, single-ended, half-bridge just arranged, recommend, full-bridge, normal shock, anti-multiple topology form such as swash; The present invention tackles in above-mentioned four big types of power inverters, and then tackles the various circuit topographies in each big type of power inverter, and only a kind of circuit form is exactly symmetrical primitive, three kinds of basic circuits being made up of symmetrical primitive in other words conj.or perhaps.
In conventional power converters; No matter be single-end circuit or bridge circuit, also no matter how many duty ratios of work wave is, if there is not direct current to flow through in the transformer; Then the former limit of transformer, pay the area of pulse square wave in the limit; Be symmetry always about time shaft, the area of pulse square wave here, the voltage, electric current or the electrical power that mean wherein to be comprised.The meaning of forward converter rectification is to be sent to load to the area of time shaft top, abandons the area of below; The meaning of anti exciting converter rectification is to be sent to load to the area of time shaft below, abandons the area of top; The meaning of bridge converter rectification is to be sent to load to two areas of paying time shaft top in the winding of limit, abandons the area of below, and " abandoning " here means the increase of power loss and circuit complexity, and the reduction of efficient.
The meaning of rectification of the present invention is, that is the meaning of active rectification DR is: the whole voltages, electric current or the electrical power that are sent in the transformer, no matter be the area that is in the time shaft top, still be in the area of time shaft below, all be sent to load.
Description of drawings
Figure 201020145042110000200032
Figure 201020145042110000200041
Fig. 1 is an A type symmetry primitive, the positive half cycle of civil power, and gate drive signal V2 positive level, the Q2 conducting, electric current gets into from diode D1, behind power device Q2, flows out from its source electrode; The civil power negative half period, gate drive signal V6 negative level, the Q4 conducting, electric current flows into from the source electrode of power device Q4, behind diode D4, flows out from its negative electrode, and the source electrode of Q2 and Q4 is connected together.
Fig. 2 is a Type B symmetry primitive, and gate drive signal V1 is positive and negative symmetrical level, and the positive half cycle of civil power, gate drive signal V1 are positive level, the Q1 conducting, and electric current flows into from the drain electrode of power device Q1, behind diode in the power device Q3 body, flows out from its negative electrode; Civil power negative half period, gate drive signal V1 are negative level, the Q3 conducting, and electric current flows into from the source electrode of power device Q3, behind diode in the power device Q1 body, flows out from its negative electrode.
Symmetry primitive SBP is a kind of marvellous combination of circuits, and is ubiquitous in hundred overpower converters, and in conventional power converters, definitely do not have; It comprises a pair of power diode and a pair of metal-oxide-semiconductor; Its circuit symmetrical so claim symmetrical primitive, is a functional part the most basic, that can assemble as required in the present invention; Can directly handle and operate alternating voltage or direct voltage; Be applied in all links of hundred overpower converters, two kinds of symmetrical primitive functions of A type and Type B are identical, but purposes is slightly variant.The polarity of metal-oxide-semiconductor can be identical in the symmetry primitive; Also can be different, with the direction of its diode that joins, so that electric current can flow and constitute the loop because of the different appropriate change both positive and negative polarities of metal-oxide-semiconductor polarity; In the occasion of handling direct current, the diode that joins with metal-oxide-semiconductor can omit.
Fig. 3 is A type basic circuit SBP-A; If being added in the A point of symmetrical primitive SBP and the voltage V11 between the ground is sine wave signal; Between two grid source electrodes, add constant amplitude square signal V10, V12; Then will on source resistance R5, produce envelope is sinusoidal wave square-wave signal Vb, and this signal is also claimed the voltage cutting signal, and Figure 100 3 is simulation waveforms that A type basic circuit produces the voltage cutting signal.
Fig. 4 is Type B basic circuit SBP-B; If the voltage V19 that is added between transformer and the ground is a sine voltage; The square-wave signal V20, the V22 that on two grids, add constant amplitude will be sinusoidal wave double-side band voltage with paying limit winding generation envelope on the former limit of transformer TX3, and Figure 100 4 is its simulation waveforms; Upper part is the waveform of input voltage V19, partly is the waveform that transformer is paid polygonal voltage Vs down.If do not strengthen capacitor filtering, then to pay the envelope of polygonal voltage waveform be sinusoidal wave to transformer, behind active rectification, obtain and civil power with the sine voltage of homophase frequently.If input voltage is a direct current, then direct current has become interchange, and hundred overpower converters hand over-hand over, straight-as to hand over Power Conversion, is so simple unexpectedly.The Type B basic circuit is used for producing a bucking voltage, and this circuit is also claimed voltage compensating circuit.The Type B basic circuit produces bucking voltage, usefulness be the conventional power conversion, its efficient is about 85%; Bridge rectifier is adopted on the limit of paying of TX3 in the compensating circuit, can obtain DC compensation voltage, and direct current is compensated; Adopt the active rectification circuit, produce AC compensation voltage, interchange is compensated.
Fig. 5 is C type basic circuit SBP-C; If the voltage V24 that is added between transformer and the ground is a sine voltage; Add square-wave signal V28, the V31 of constant amplitude at two grid source electrodes, then will on source resistance R21, produce envelope is sinusoidal wave square-wave voltage, the former limit of transformer TX4 with pay a limit winding and produce the double-side band voltage that an envelope be a sine wave; Figure 100 5 is its simulation waveforms; Is input sine wave voltage, and the centre is that transformer is paid the envelope that the limit produces and is sinusoidal wave double-side band square-wave voltage, is that the envelope of source electrode output is sinusoidal wave square-wave voltage below.
If between the grid of FET Q25, Q26 and ground, add the voltage cutting signal Vb that A type basic circuit produces; No matter which kind of voltage drain electrode adds, and is sinusoidal wave square-wave voltage as long as drain voltage greater than grid voltage, will produce envelope on source resistance; This voltage accurate tracking signal; Be grid voltage such as same, downcut its shape and the identical some of grid voltage to drain voltage, so C type basic circuit SBP-C also claims the voltage cutting circuit sharp sword.
If the grid cutoff signal is sinusoidal wave, drain electrode adds the direct voltage with the killer voltage constant amplitude, then on source resistance, obtain with the direct voltage constant amplitude, with the envelope of killer voltage output voltage, the operation principle of Here it is dc inversion with shape; If the grid cutoff signal is sinusoidal wave; Drain electrode adds with the killer voltage constant amplitude but the alternating voltage of different frequency; Then on source resistance, obtain with the drain voltage constant amplitude, with the output voltage of the public part of grid killer voltage same frequency, two kinds of different frequency voltages, the operation principle of frequency conversion that Here it is.Residue after drain voltage is cut is partly carried out the conventional power conversion in TX4, the course of work is identical with the situation of bucking voltage with the result.
Figure 100 8 is that the transformer that oscilloscope shows is paid the actual waveform of polygonal voltage; The common drain of Type B and C type basic circuit (SBP-B, SBP-C); All be connected to core transformers,, do not have rectifying and wave-filtering again because input voltage is sinusoidal wave; After grid adds square wave driving signal (Figure 100 8 upper parts), the limit of paying of transformer produces the double-side band square-wave voltage that envelope is a sine wave; Look that the positive-negative half-cycle amplitude differs bigger, but the big pulse of amplitude is narrow, the pulse that amplitude is little is wide, and its area or mean value equate.If the duty ratio of driving pulse equals 0.5, then time shaft pulse amplitude up and down equates, it is 0.5 many more that duty ratio departs from, and it is big more that the positive negative pulse stuffing amplitude differs.It is 0.5 more that the driven square wave impulse duty ratio that the upper part of Figure 100 8 shows departs from, thus middle part and the double-side band waveform that partly shows down, its up and down pulse amplitude differ bigger, waveforms do not add filter capacitor in the middle of Figure 100 8, following waveform adds the 10n filter capacitor.
Fig. 6 is high-frequency driving signal generator VDrvh; Integrated circuit NE555 is connected into the fundamental oscillation device of EDM Generator of Adjustable Duty Ratio, and supply power voltage is by V26, V30 series connection, centre-point earth; Output voltage Gc on R22; Gc is a symmetrical square wave voltage with respect to middle heart, and this signal inserts signal conversion circuit SPrs shown in Figure 8, produces complementary, the drive signal Ga of positive and negative symmetry, Gb at last.
Synchronized signal generator VDrvs among Fig. 7, integrated circuit LM339 is connected into the general comparator circuit, and supply power voltage and Fig. 6 are together; Its homophase termination line voltage, end of oppisite phase ground connection is when city's voltage is not equal to zero; The output of comparator produces saltus step, on resistance R 23, produces output voltage Gc, and the middle relatively heart of Gc is a symmetrical square wave voltage; This signal inserts signal conversion circuit SPrs shown in Figure 8, produces complementary, the drive signal Ga of positive and negative symmetry, Gb at last.
Signal conversion circuit SPrs among Fig. 8 is made up of optocoupler U1, U2; Symmetrical square wave signal Gc inserts from In, and during positive half cycle, Gc produces positive pressure drop Va through optocoupler U2 on resistance R 12; This pressure drop is added in the base stage of Q22, Q24 simultaneously; Because emitter resistance R14 connects middle heart, is equivalent to add positive and negative symmetrical square wave voltage for Q22, Q24, therefore on resistance R 12, form the circuit and square-wave Ga of positive and negative symmetry; During negative half period; Gc produces positive pressure drop Vb through optocoupler U1 on resistance R 13; This pressure drop is added in the base stage of Q21, Q23 simultaneously; Because emitter resistance R13 connects middle heart, is equivalent to add positive and negative symmetrical square wave voltage for Q21, Q23, therefore on resistance R 13, form the square-wave voltage Gb of positive and negative symmetry.Signal voltage Ga, the Gb that Fig. 6, Fig. 7 produce be complementary, positive and negative symmetry, isolate, the metal-oxide-semiconductor among the present invention is only used above-mentioned two kinds of drive signals, is exactly high-frequency driving signal and civil power synchronized signal, when using later on no longer repeat specification.
Figure 100 6 is simulation waveforms of Fig. 6 and the common high-frequency driving signal that produces of Fig. 8; Be successively from top to bottom: the positive and negative symmetrical square wave voltage Gc of 555 generations; The positive and negative symmetrical square wave signal Va that produces on the resistance R 12 with respect to middle heart; The positive and negative symmetrical square wave signal Vb that produces on the resistance R 11 with respect to middle heart, the positive and negative symmetrical square wave signal Ga that produces on the resistance R 14, the positive and negative symmetrical square wave signal Gb that produces on the resistance R 13 with respect to middle heart with respect to middle heart.
Figure 100 7 is simulation waveforms of Fig. 7 and the common synchronized signal that produces of Fig. 8, and waveform title and meaning are the same.
Fig. 9 is A type active rectification circuit RectA, the symmetrical primitive SBP that FET Q17, Q18 form, and it leaks level and is connected to transformer; Be Type B basic circuit SBP-B, input sine wave voltage V13 does not pass through rectifying and wave-filtering, when grid meets symmetrical square wave drive signal V9; The limit of paying at transformer TX2 produces the double-side band square-wave voltage Vs that envelope is a sine wave, and Vs can be divided into four different parts, promptly preceding 10 milliseconds upper and lower part and back 10 milliseconds upper and lower part; V14-V17 is to be the civil power synchronizing signal of 20ms in the cycle, V15, the V16 10ms that delays time wherein, V14, the V17 0ms that delays time; Direction according to diode D11-D14 can know that the upper part voltage of 10ms before D11, Q13 branch road are selected is so obtain having only the steamed bun wave voltage Va+ of positive half wave on source resistance R6; D13, Q15 branch road are selected the following part voltage of back 10ms, so on source resistance R7, obtain having only the steamed bun wave voltage Va-of negative half period, and the following part voltage of 10ms before D14, Q16 branch road are selected; So on source resistance R9, obtain having only the steamed bun wave voltage Vb-of negative half period; D12, Q14 branch road are selected the upper part voltage of back 10ms, then on source resistance R8, obtain having only the steamed bun wave voltage Vb+ of positive half cycle, when output voltage is obtained from the source electrode of Q13, Q15; Then output voltage is the whole steamed bun wave voltage Va2x of all-wave; When output voltage is obtained from the source electrode of Q15, Q17, then output voltage is the steamed bun wave voltage Vb2x of full-wave rectification, and the waveform of Va2x and Vb2a is identical.
Figure 100 9 is simulation waveforms of output voltage, is successively from top to bottom: input current voltage Vi, transformation is paid polygonal voltage Vs, and rectification steamed bun wave voltage Va+, Va-, Va2x, Vb+, Vb-, Vb2x.Can see from the simulation waveform of Figure 100 9; Although TX2 pays polygonal voltage waveform Vs about X axle and asymmetric, after over commutation and little capacitor C 6, C7, C8, C9 filtering, voltage waveform Va+ and Va-; Vb+ and Vb-are symmetry about the X axle; The amplitude of Va2x and the every 10ms of Vb2x also equates, fully proves aforementioned judgement of paying limit double-side band voltage about transformer: look that the positive-negative half-cycle amplitude differs bigger, but the big pulse of amplitude is narrow; The pulse that amplitude is little is wide, and its area or mean value equate.
Figure 10 is Type B active rectification circuit RectB, the symmetrical primitive SBP that FET Q9, Q10 form, and it leaks level and is connected to transformer; Be Type B basic circuit SBP-B; Input sine wave voltage V3 does not pass through rectifying and wave-filtering, and under the driving of high-frequency square-wave signal V9, transformer TX1 pays the limit and produces the double-side band square-wave voltage Vs of envelope for sine wave; Identical with above-mentioned situation; But because the source electrode of Q5, Q7 is linked together, the source electrode of Q6, Q8 is linked together, obtains positive and negative sine voltage Vsinx and V respectively (sinx) in that common source resistance R2, R3 are last.
Figure 101 0 is the output voltage simulation waveform of Type B active rectification circuit, is successively from top to bottom: input voltage Vi, paying the limit envelope is sinusoidal wave double-side band voltage Vs, (sinx), the voltage Vsinx of output on the resistance R 2 of the output voltage V on the resistance R 3.
Figure 11 (A) is C type active rectification circuit RectC; The symmetrical primitive SBP that FET Q19, Q20 form; It leaks level and meets transformer TX2, is Type B basic circuit SBP-B, and input sine wave voltage Vi does not pass through rectifying and wave-filtering; Grid adds positive and negative symmetrical square wave drive signal V11, produces the double-side band square-wave voltage Vs that envelope is a sine wave on the limit of paying of TX2.
Q5, Q11 and Q6 among Figure 11 (A), Q12 form Type B symmetry primitive SBPB1 and SBPB2 respectively, and drive signal V5, V9 are synchronous square wave driving signals, cycle 10ms; Positive and negative symmetry, both phase places are opposite, and positive direction drives Q5, Q6; Negative direction drives Q11, Q12, can know that according to the principle of Type B symmetry primitive SBPB what SBPB1 obtained is the voltage on preceding 10ms top; Negative just down on the voltage on the capacitor C 2, waveform with Vs before the envelope of 10ms upper part waveform, SBPB2 obtains is back 10ms partly voltage down; On the voltage on the capacitor C 3 negative down just, waveform with Vs after the 10ms envelope of waveform partly down, from the voltage of Q11, Q12 source electrode output V2sinx; Amplitude is 2 times of Vs, with input voltage V4 frequency homophase together.Can see that not taking-up of 10ms upper part voltage behind part voltage and the Vs is equivalent to halfwave rectifier voltage under the preceding 10ms of Vs.
Figure 11 (B) is D type active rectification circuit RectD, Q3, Q9, Q4, Q10; Q15, Q21, Q16, Q22 form Type B symmetry primitive SBPB1, SBPB2, SBPB3, SBPB4 respectively, and drive signal V6, V7, V12, V13 are the positive and negative symmetrical square waves of cycle 20ms; Anti-phase can be known according to the principle of Type B symmetry primitive SBPB, when the negative half period of preceding 10ms drive signal arrives; Q9, Q10, Q21, Q22 conducting; Diode has been formed a positive rectifier bridge in Q3, Q4, Q15, the Q16 body, the result of rectification, the waveform of 10ms double-side band square-wave voltage Vs below time shaft before making; Translate into the top of time shaft and come the positive steamed bun wave voltage of 10ms before on load resistance R3, obtaining; When the positive half cycle of back 10ms drive signal arrives; Q3, Q4, Q15, Q16 conducting; Diode has been formed a negative rectifier bridge in Q9, Q10, Q21, the Q22 body, the result of rectification, the waveform of double-side band square-wave voltage Vs above time shaft of 10ms after making; Translate into the below of time shaft and come, on load resistance R3, obtain the negative steamed bun wave voltage of back 10ms.Positive and negative two steamed bun wave voltages have formed the voltage waveform of a sinusoidal wave complete cycle on the resistance R 3; Its amplitude is identical with the amplitude that transformer is paid polygonal voltage Vs, with input voltage frequency, homophase together, 10ms before and after the Vs; Time shaft waveform up and down all arrives load, is equivalent to full-wave rectifying circuit.
Figure 101 1 is the simulation waveform of C type and D type active rectification circuit output voltage; Be successively from top to bottom: input voltage V4; Transformer is paid polygonal voltage Vs; The dynamically whole circuit output voltage V2sinx of C type, the dynamically whole circuit output voltage Vsinx of D type, the amplitude that can see V2sinx is 2 times of Vsinx.
Figure 12 is the schematic circuit of panel height modulation AHM; Q3, Q6 form A type symmetry primitive SBPA, and source electrode is connected to resistance R 6, is typical A type basic circuit SBP-A; Voltage on the load resistance is with combining grid voltage Vf; Vf is provided by the reference voltage Vc that produces in the machine, and Vc is a little more than civil power Vi, to prevent the grid Control Failure.When 1) load R5 changes, 2) city's electro-mechanical wave, 3) temperature changes; Fluctuation can appear in grid voltage Vf, and output voltage V o also can fluctuate thereupon, in order to compensate this fluctuation; Keep output voltage V o constant; Adjustment grid voltage Vf keeps grid voltage constant, to compensate above-mentioned three kinds of fluctuations that reason causes in good time.
Keeps direct voltage constant, a lot of alternative circuit are arranged, but the grid reference voltage Vf of this place is a sine wave AC voltage that the opinion with available circuit has no a kind of circuit can stablize alternating voltage; Really, pulse-width modulation PWM technology can stable DC and alternating voltage; But its operation principle is (the addressing before its drawback) that is the basis with the pulsewidth of regulating high-frequency impulse; Main power component of the present invention does not carry out the conventional power conversion, and no pulsewidth is adjustable, therefore; Keep grid voltage Vf constant, have only timely adjustment gate bias resistor R1 or R5.
Panel height modulation AHM technology just automatically, the resistance of timely adjustment biasing resistor R1 or R5, the amplitude of indirect regulation sine wave AC reference voltage Vf makes its maintenance constant, its operation principle is following:
When input voltage Vi rises or descends, or load resistance R6 increases or when reducing, the amplitude of source electrode output voltage V o rises or descends, in the time of still between DC reference voltage V1 and V2, and shown in the middle waveform of Figure 101 2, the AHM attonity;
When input voltage Vi rising, when perhaps load resistance R6 increased, the amplitude of source electrode output voltage V o rose to greater than DC reference voltage V1; Shown in the superiors' waveform of Figure 101 2, keep stable in order to make Vo, the grid potential of Q3, Q6 is descended; The upper resistance R 1 of biasing is increased, and R1 constantly increases, and Vo will constantly descend; After the amplitude of Vo dropped to less than DC reference voltage V1, R1 just no longer increased, and Vo also just no longer descends; Like the middle waveform of Figure 101 2, the amplitude that keeps output voltage V o is less than V1;
When input voltage Vi decline, when perhaps load resistance R6 reduced, the amplitude of source electrode output voltage V o dropped to less than DC reference voltage V2; Like the orlop waveform of Figure 101 2, keep stable in order to make Vo, the grid potential of Q3, Q6 is risen; Upper offset resistance R 1 is reduced, and R1 constantly reduces, and Vo will constantly rise; After the amplitude of Vo rose to greater than DC reference voltage V2, like the middle waveform of Figure 101 2, R1 just no longer reduced; Vo also just no longer rises, and the amplitude that keeps output voltage V o is greater than V2.
The result of above-mentioned dynamic adjustment, just the amplitude of output voltage V o only changes between DC reference voltage V1, V2, and V1, V2 can artificially set in advance, that is the amplitude of output voltage V o and the precision of voltage regulation can artificially be set in advance.Here the variation of R1 is not continuous, but quantification or digitized, its method is to be divided into the N equal portions to the adjustable part of resistance R 1; Each equal portions resistance is parallelly connected with a digital switch, and switch breaks off, and representes that this equal portions resistance inserts or increase; Switch closure is represented this equal portions resistive short or minimizing, the disconnection of switch and closure; Automatically controlled by digital circuit, speed is exceedingly fast.
Panel height modulation AHM technology is with little change increment of Digital Circuit Control resistance R 1 adjustable part; Be to have controlled power device Q3, the sinusoidal wave dynamically amplitude of reference voltage Vf of Q6 grid in essence; So claim the panel height modulation; The ingenious part of this law is that reference voltage is a DC low-voltage, and the object of control but is an ac high voltage.In practical application, N can get 8 or 16, and the circuit of realization is fairly simple, if the N value is excessive, and the circuit more complicated that can become.Panel height modulation AHM and pulse-width modulation PWM have play the same tune on different musical instruments wonderful, can integrated various chips, N can get bigger value, the adjusting of voltage more accurately, more level and smooth, should use more convenient.
Panel height modulation AHM technology is according to the amplitude of alternating voltage Vo, and automatically, the resistance of timely adjustment biasing resistor R1 or R2, its external circuit is very simple; One is controlling object: ac output voltage Vo, and one is destination object: resistance R 1 or R2, in side circuit; Can use the resistance of a mark controlling object Vo, come whole circuit of equivalent panel height modulation AHM, the mask method of equivalent resistance is following: AHMn (Vo) No; AHM representes panel height modulation AHM; N representes the adjustable Standard resistance range of destination object, (Vo) expression controlling object, and No representes the sequence number of element.
Figure 13 is the side circuit of panel height modulation AHM, and the course of work is following: U3, U4 form synchronous generator, produces and civil power clock signal synchronous Clk; It is voltage high detection circuit that U12, U13 form; When output voltage set during greater than V1, U19, U20 form the low testing circuit of voltage, when output voltage resets during less than V2; U27, U28 form start reseting signal generating circuit, output Clr and RST signal.
16 switch in parallel such as 16 resistance such as R6, R7, R13, R14, R18, R19, R24, R25, R29, R30, R36, R37, R41, R42, R51, R52 and S1-S16; Disconnection and the closure of U1, U7, U10, U14, U17, U21, U23, U25, U2, U8, U11, U15, U18, U22, U24,16 D flip-flops (74LS74) control switch S1-S16 such as 26; Promptly control the disconnection and the access of 16 resistance such as R1, U6 is four BCD forward-backward counters, and initialize data end position D0-D2 connects high level through resistance R 47; D3 ground connection; Initialize data is the data input pin A0-A3 that 0111, four terminal count output Q0-Q3 connects U16 four bit decoders, and U16 is translated into 16 control signal Q0-Q15 to four binary-coded decimals that U6 counts to get; One of corresponding 16 D flip-flops such as U1 of each control signal; The control of each D flip-flop is with the disconnection and the access of 16 resistance such as R6, the adjustable part of the resistance R 1 that these 16 resistance are exactly Figure 12, and the resistance R 58 of connecting with 16 resistance such as R6 is the resistance R 2 of Figure 16; V5 is the control voltage Vc among Figure 12, and direct current reference circuit V1, V2 are respectively 3.0V and 2.9V.
U3 is comparator LM339, and the anti-phase termination is slightly larger than zero low level V0, the steamed bun wave voltage Vd after the homophase termination output voltage V o rectification; When this voltage during greater than V0; U3 exports high level, when this voltage is lower than V0, and the U3 output low level; Then the output at U3 obtains the square-wave voltage synchronous with civil power, and this voltage is received the input B of U4; U4 is a monostable trigger, and its input B is that high level triggers, and C1, R1 have determined that the pulse of its output is 5ms, and then obtaining the cycle at the output QP of U4 is 10ms, and pulsewidth is 5ms clock signal C lk, please refer to the simulation waveform of Clk among Figure 101 3.
U12 is comparator LM339, anti-phase termination reference voltage V1=3V, the steamed bun wave voltage Vd after the homophase termination output voltage V o rectification; When the steamed bun wave voltage after the output voltage V o rectification during greater than V1; U12 exports high level, when this voltage is lower than V1, and the U12 output low level; Then the output at U12 obtains and synchronous square-wave voltage of civil power half period, and this voltage is received the input B of U13; U13 is a monostable trigger; Its input B is that high level triggers; C2, R17 have determined the pulse cycle of its output to be slightly larger than 5ms, and then the output QP at U13 obtains DC level rather than square-wave voltage, but that is monostable trigger U13 become a repeated trigger monostable trigger.
U19 is comparator LM339, anti-phase termination reference voltage V2=2.9V, the steamed bun wave voltage Vd after the homophase termination output voltage V o rectification; When this voltage during greater than V2; U19 exports high level, when this voltage is lower than V2, and the U19 output low level; Then the output at U19 obtains and synchronous square-wave voltage of civil power half period, and this voltage is received the input B of U20; U20 is a monostable trigger; Its input B is that high level triggers; C3, R31 have determined the pulse cycle of its output to be slightly larger than 5ms, and then the output QP at U20 obtains DC level rather than square-wave voltage, but that is monostable trigger U19 become a repeated trigger monostable trigger.
U27 is comparator LM339, half of anti-phase termination V3 voltage, and voltage that in-phase end connects is slightly larger than end of oppisite phase voltage; Be connected to capacitor C 5 simultaneously, when start powers up, because capacitor C 5 voltage can not be suddenlyd change; In-phase end institute making alive is 0V, and the U27 output low level is when the C5 voltage rises to greater than end of oppisite phase voltage; U27 exports high level, and then at the output of U27 obtain starting shooting power-on reset and clear signal Clr, this voltage is received the input B of U28; U28 is a monostable trigger, and its input B is that high level triggers, and C5, R46 have determined that the pulse cycle of its output is 1ms, then at the output QP of U28 obtain starting shooting power-on reset and clear signal Clr, please refer to the simulation waveform of Clr among Figure 23.
The count results Q0-Q3 of four binary-coded decimal forward-backward counter U6 (74LS193) directly gets into the A0-A3 of 4-16 decoder (74LS156) U16; Each 4 binary-coded decimal confirming is through behind the decoder; Corresponding with one that confirms among the output Q0-Q15; The input end of clock of 16 D flip-flops such as U1 is received in the output of decoder, with 4 corresponding those D flip-flops actions of binary-coded decimal.
During start, the negative pulse of the QN of U28 output 1ms resets U6; After the reset pulse, QP chooses U16, and 16 D flip-flops such as U1 are resetted; 16 switches such as S1 break off, 16 resistance access circuits such as R6, and the amplitude of reference voltage Vf is minimum.The bridge that output AC voltage Vo is made up of D1-D4 is rectified into the steamed bun wave voltage, and this voltage and direct voltage V1, V2 compare, and has three kinds of situation to take place:
1, when this voltage magnitude during less than direct voltage V1, greater than direct voltage V2, the QP of U13 and the QN of U20 be output low level, clock signal C lk can not through with door U5, U9, the Up of U6, Down pulse-free signal, the U6 counting stops.No matter data terminal, which kind of level of clock termination of 16 D flip-flops of U1 beginning, switch S 1-S16 is failure to actuate, and reference voltage Vf is constant, and then the amplitude of output voltage V o remains within the allowed band, and simulation waveform please refer to Figure 101 3A.
2, when this voltage magnitude during greater than direct voltage V1, also greater than direct voltage V2; The QP output high level of U13, the QN output low level of U20, clock signal can not can be passed through U9 through U5; Get into the input Down of U6; So U6 begins to subtract a counting, during less than V1, U6 stops counting up to the amplitude of output voltage V o.Because the QP of U20 exports high level,, be low level so the data terminal D of 16 D flip-flops of U1 beginning connects by triode Q1 anti-phase; If the clock end of certain D flip-flop has pulse to arrive; Then its output Q is a low level, and this low level makes the switch that is attached thereto break off, with the resistance access circuit of switch in parallel; Then reference voltage Vf reduces, and output voltage V o also descends thereupon.As long as the amplitude of the steamed bun wave voltage Vd of output voltage V o is greater than direct voltage V1 (3.0V), U6 just constantly subtracts 1 counting, and count results is deciphered through LS154; Always corresponding at last with a D flip-flop; Make and want that with it the switch of getting in touch breaks off, corresponding resistance access circuit, consequently reference voltage Vf constantly descends; Output voltage V o also constantly descends thereupon, and simulation waveform please refer to Figure 101 3B.
3, when this voltage magnitude during less than direct voltage V1, also less than direct voltage V2; The QP output low level of U13, the QN output high level of U20, clock signal can not can be passed through U5 through U9; Get into the input Up of U6; So U6 begins to increase a counting, during greater than V2, U6 stops counting up to the amplitude of output voltage V o.Because the QP output low level of U20,, be high level so the data terminal D of 16 D flip-flops of U1 beginning connects by triode Q1 anti-phase; If the clock end of certain D flip-flop has pulse to arrive; Then its output Q is a high level, and the feasible switch closure that is attached thereto of this high level is with the resistive short of switch in parallel; Then reference voltage Vf raises, and output voltage V o also rises thereupon.As long as the amplitude of the steamed bun wave voltage Vd of output voltage V o is less than direct voltage V2, U6 just constantly adds 1 counting, and count results is deciphered through LS154; Always corresponding at last with a D flip-flop; Make switch closure associated therewith, resistive short, consequently reference voltage Vf constantly rises; Output voltage V o also constantly rises thereupon, and simulation waveform please refer to Figure 101 3C.
Boost capacitor network UPnet is made up of N rank capacitance network, among Figure 14, is the firstorder circuit figure of network from Begin to End, and two arms about every rank all have, circuit are symmetry fully; Decompression capacitor network DNnet is made up of N rank capacitance network, among Figure 15, is the firstorder circuit figure of network from Begin to End, and two arms about every rank all have, circuit are symmetry fully.
Embodiment
Embodiment 1: ac inverter.
Figure 16 is an ac inverter, and metal-oxide-semiconductor Q25, Q27 etc. form A type symmetry primitive SBPA, meet transformer TX2 in its common drain; Constitute Type B basic circuit SBP-B; Transformer is paid the D type active rectification circuit RectD that the limit is Q17, Q18, Q19, Q20, Q23, Q24, Q28, Q29 composition, and C2 has been the electric capacity of smoothing effect, and V17 is a civil power; V18, V19, V25, V26 are the VDvrs type synchronized signals of positive and negative symmetry, and V22, V24 are VDvrh type high-frequency driving signals.If the amplitude of input voltage V17 is 280V, the no-load voltage ratio of transformer TX1 is 1: 0.3, and load resistance R7 is 50 Europe, and then output amplitude is the alternating voltage Vo of 80V on the resistance R 7.In the simulation waveform of Figure 101 6; Be that input voltage Vi, transformer are paid the limit envelope for sinusoidal wave double-side band square-wave voltage Vs, output voltage V o successively, can see that output voltage and input voltage are with frequency, homophase; It is the envelope that transformer is paid limit double-side band voltage waveform; Change the pulsewidth of drive signal V22, V24, promptly duty ratio can be adjusted output AC voltage Vo automatically.
Embodiment 2: dc inverter.
Figure 17 is a dc inverter, and metal-oxide-semiconductor Q33, Q34, Q37, Q38 form main circuit, because input voltage is a direct current, the metal-oxide-semiconductor polarity of forming symmetrical primitive is identical, exempts the diode that joins with it simultaneously.Applied voltage V16 is the direct voltage of 311V, and drive signal V24, V25 are the square-wave signals of 50Hz, V25 hysteresis 10ms; Drive signal G1, G3 are that the envelope that is produced by Q29, Q30 is the high-frequency square-wave signal of sinusoidal steamed bun ripple, and G3 hysteresis 10ms is during the preceding 10ms; Winding, Q33, R12, Q38 form the loop through the former limit of TX3 for Q33, Q38 conducting, direct voltage, on R12, produce the sinusoidal forward steamed bun wave height identical with G1 envelope square-wave voltage frequently; The limit of paying at TX3 produces the sinusoidal steamed bun wave height of double-side band square-wave voltage frequently; During the back 10ms, Q34, Q37 conducting, winding, Q34, R12, Q37 form the loop to direct voltage through the former limit of TX3; On R12, produce the sinusoidal negative direction steamed bun wave height identical square-wave voltage frequently with the G3 envelope; The limit of paying at TX3 produces the sinusoidal steamed bun wave height of back 10ms double-side band square-wave voltage frequently, and through 20ms, on resistance R 12, forming complete envelope is sinusoidal wave high frequency square wave voltage Voa; Pay the limit at TX3 and form the sinusoidal wave high frequency square wave voltage Vs of complete double-side band; Voltage Vs produces sinewave output voltage Vob behind the D type active rectification circuit that Q25, Q26, Q31, Q32, Q35, Q36, Q39, Q40 form, the pulsewidth may command of the no-load voltage ratio of TX3 and G1, G3 and the amplitude of regulating Vob.
The source electrode of the generation of G1, G3: Q27, Q28 is connecting resistance R10, R11 respectively; The grid source electrode meets high frequency square wave drive signal V17, V18; Drain electrode meets cycle 20ms, the square-wave signal V19 of duty ratio 50%, V20 respectively; V20 hysteresis 10ms, so be that 20ms, duty ratio are 50% high-frequency square-wave signal Vr3, Vr4 in resistance R 10, R11 last acquisition envelope cycle, wherein Vr4 is than the Vr3 10ms that lags behind.Behind the 50Hz that produces in the machine, the full-bridge of the sine wave signal of amplitude 322V through the D1-D4 composition; Produce steamed bun ripple signal; Be added in the drain electrode of Q29, Q30; Through resistance R 13, R14 ground connection, the grid source electrode meets R10, last drive signal Vr3, the Vr4 of R11 respectively to their source electrode respectively, then upward respectively obtains amplitude 320V at source resistance R13, R14, envelope is sinusoidal wave half steamed bun ripple signal G1, G3.
Figure 101 7 is simulation waveforms of each point voltage, is successively from top to bottom: drive signal Vr3, Vr4, drive signal G1, G3, TX3 pay limit double-side band voltage Vs, the sine voltage Voa of R12 output, the sine voltage Vob that active rectification DR is produced.
If the sine wave that cuts down is ASinx; Then cutting back residue expression formula partly is S=A-ASinx, and S is the result of SIN function ASinx counter-rotating back translation, still is SIN function; So pay the double-side band square-wave voltage that the limit obtains at transformer TX3, its envelope still is sinusoidal wave.
Q33, Q34 constitute main clipper circuit, the switching-over of Q37, Q38 guide current, and when its effect is equivalent to exchange input, the diode that joins with metal-oxide-semiconductor.The last output voltage V oa of R12 is immediately following grid voltage G1, G3, and its amplitude hang down a Vgs, pass through capacitor C 10 filtering after, its waveform no longer is a square-wave voltage, but with signal G1, sine voltage that the G3 envelope is identical.
The clipper circuit that Q33, Q34 form downcuts sine voltage Voa to the direct voltage that is added in drain electrode; Area is 64% of an input voltage; Residue after the cutting partly accounts for 36% of input voltage area, and this partly voltage process conventional power conversion in TX3 produces sine voltage Vob.Voa is the source voltage that cuts down, and its conversion efficiency is 100%, and Vob carries out the output voltage after the conventional power conversion through TX3; Its conversion efficiency is 85%; If this power loss partly is P1, P1=36%* (1-85%)=5.4%, then useful work is that gross efficiency is 94.56%.
Embodiment 3: alternating current steady voltage plug.
Figure 18 is the schematic circuit of alternating current steady voltage plug; Power device Q1, Q3 form A type symmetry primitive SBPA; Be connected to resistance R 7 at common source; Constitute A type basic circuit SBP-A, panel height modulation equivalent resistance AHM20k (Vo) 1 is biasing circuits of Q1, Q3 grid with resistance R 6, and input voltage Vi is that amplitude is the sine wave of 360V.Output voltage V o follows the tracks of the grid voltage of Q1, Q3, when upper offset resistance when 10k changes between 100k, output voltage V o changes between the 170V at 300V, promptly ac output voltage is adjustable, Figure 101 8 is simulation waveforms of output voltage; When load resistance R7, input voltage Vi or temperature T changed, respective change can take place in output voltage V o, and panel height modulation this moment AHM starts, and the result of closed-loop control makes output voltage keep constant.The mark meaning of panel height modulation equivalent resistance AHM20k (Vo) 1 is: the adjustable Standard resistance range of upper offset resistance AHM1 is 20k, and controlling object is output voltage V o.
If input voltage 250V, source electrode output voltage 220V, output current 20A then has the drain-source utmost point of the AC voltage drop of 30V at Q1, Q3, and power loss is 600W, and overall efficiency is 88%.In order to make Q1, the unlikely heating waste of Q3 drain-source 30V alternating voltage, the drain electrode of the symmetrical primitive SBPA that Q1, Q3 form meets transformer TX1, carries out the conventional power conversion to this a part of power (12%), and is with output voltage V o and line output, shown in figure 19.
Among Figure 19; The common drain of the A type symmetry primitive SBPA that Q13, Q14 form meets transformer TX1; Be evolved into C type basic circuit SBP-C, add VDvrh type high-frequency driving signal V8, V10 at the grid of two power device Q13, Q14, applied voltage V1 is 250V; Source electrode output voltage V oa is 220V, and then transformer former limit winding and Q13, Q14 drain-source pressure drop sum are 30V.Because Q13, Q14 are operated near the saturation region; Its drain-source pressure drop is very little; 30V voltage all is added in the former limit of transformer basically, and the no-load voltage ratio of TX1 is 11, and then the limit generation amplitude of paying at TX1 is the double-side band square-wave voltage of sine wave near 311V, envelope; Behind this voltage process D type active rectification RectD, obtain sine voltage Vob.Figure 101 9 is simulation waveforms of output voltage; Be successively from top to bottom: input voltage Vi, transformer are paid limit double-side band square-wave voltage Vs, source electrode output voltage V oa, transformer and are paid limit output voltage V ob; Can see that from simulation waveform output voltage V oa, Vob and input voltage Vi are with the frequency homophase.
Because output voltage and input voltage series connection, input current is identical with output current, and during computational efficiency, the power voltage available replaces; Input voltage 250V, wherein 220V is exported by source electrode, and surplus 30V is through the conventional power conversion; Its conversion efficiency is 85%, and this part output voltage is 30*85%=25.5V, therefore the actual 220+25.5=245.5V that is output as; Efficient equals power output divided by input power, and therefore, the overall efficiency of Figure 19 AC voltage regulator is 245.5/250=98.2%.The exhausted major part (88%) of input power is exported by source electrode; Through output needn't pass through core transformers, and the conversion efficiency of this part power is 100%; Have only very small portion power (12%) will carry out the conventional power conversion, and through the core transformers transmitted power.In the circuit of Figure 19, the C type basic circuit SBP-C that Q13, Q14 form cuts into two to input sine wave voltage Vi partly as a cutter; Some is output AC voltage Voa; Another partly is transformer original edge voltage Vp, and therefore, the circuit of Figure 19 is the voltage cutting circuit.
Should guarantee that output voltage V oa is constant sine voltage; Guarantee the operating frequency of transformer TX1 again; The gate drive signal that is added in Q1, Q2 must be that envelope is sinusoidal wave square-wave voltage, and its amplitude should be slightly high with output voltage, and its frequency should be suitable with the operating frequency of transformer; In addition, when input voltage is lower than 220V, must carry out voltage compensation, to reach the rated output voltage value.
Figure 20 is the main circuit of AC voltage regulator, by the Type B basic circuit SBP-B that Q57, Q58 form, adds pair limit circuit of transformer, is an ac inverter, and is identical with the circuit of Figure 16.The output voltage of inverter is connected with input voltage Vi; The alternating voltage Vr16 that is output on the resistance R 16 connects with input ac voltage Vi; The live wire of the following termination input voltage Vi of R16, another termination exit point Vc of R2, the pulsewidth of change drive signal V38; Be duty ratio, can adjust automatically output voltage V c.
The A type basic circuit SBP-A that forms by Q49, Q50; Add VDvrh type drive signal at its grid; When adding AC power V35; The output envelope is sinusoidal wave square-wave signal on source resistance R18, and the amplitude of its envelope is than the low Vgs of grid voltage, and its frequency is identical with the frequency that grid adds VDvrh type drive signal.C type basic circuit SBP-C that forms by Q51, Q54 and transformer thereof pay the limit circuit; Form an AC voltage regulator; Identical with the circuit of Figure 19, when resistance R 18 square-wave signals that export, that envelope is sine wave were added to the grid of Q51, Q54, the output voltage V oa that can guarantee its source electrode was the sine voltage of specified amplitude; Also can guarantee the operating frequency of transformer TX4, transformer TX4 pays the output voltage V ob on limit in end points Va and the parallelly connected output of source electrode output voltage V oa.Panel height modulation equivalent resistance AHM30k (Voa) 1 connects with resistance R 18, and when AHM30k (Voa) 1 became big, the envelope of the last output of R18 diminished for sinusoidal wave square-wave signal amplitude, and vice versa, controlled the amplitude of output voltage V oa indirectly.
The alternating current steady voltage plug course of work of Figure 20 is following: as input voltage Vi during in normal range (NR), compensating circuit and clipper circuit do not start, and output voltage is exactly input voltage Vi; When input voltage was too high, clipper circuit started, and compensating circuit does not start, and output voltage is Va; Cross when low when input voltage, clipper circuit does not start, and compensating circuit starts, and output voltage is Vc; The access of voltage Vi, Va, Vc and disconnection have special switch to control (please refer to uninterrupted power supply UPS).
Embodiment 4: D.C. regulated power supply.
Figure 21 is the schematic circuit of D.C. regulated power supply, and input voltage V2 produces steamed bun wave voltage Vd through the rectifier bridge that D3, D4, D13, D14 form; This voltage is added in the drain electrode of metal-oxide-semiconductor Q2 through resistance R 1, and the source electrode of Q2 is through resistance R 9 ground connection, and its grid meets square wave driving signal V3; It is the square-wave signal Vc of steamed bun ripple that source electrode produces envelope; Vc becomes flat-top steamed bun ripple cutoff signal through the voltage-stabiliser tube heap slicing that D11, D12, D15 form, and is added in the grid of metal-oxide-semiconductor Q4.The circuit that Q4 and transformer TX1, resistance R 8 are formed is that C type basic circuit is the half the of clipper circuit; On the source resistance R8 of Q4, obtain the flat-top steamed bun wave voltage identical with cutoff signal; The double-side band square-wave voltage of paying limit circuit generation of TX1 is through after the full-bridge rectification; Obtain direct voltage Vob, the amplitude of Voa, Vob is identical, two-way direct voltage and line output.
Panel height modulation equivalent resistance AHM50k (Voa) 1, adjustable resistance is 50k, and controlled plant is output AC voltage Voa, and the adjustment of output voltage V ob has two approach, and the one, the no-load voltage ratio of TX1 is coarse adjustment, the 2nd, the pulsewidth of cutting square wave is fine tuning.
Figure 102 1C is the simulation waveform of each point voltage; Be successively from top to bottom: steamed bun wave voltage Vd, killer voltage Vc, Q2 source electrode output voltage V oa, the TX1 of input voltage after rectification pays the output voltage V ob that limit double-side band voltage Vs, bridge rectifier obtain; Here Voa, Vob do not strengthen capacitor filtering, are unidirectional pulsating voltages.
Adopting the benefit of flat-topped wave cutting is further to improve overall efficiency; Figure 102 1A is the comparison demonstration graph of cutting mode, export the 250V direct voltage, can use the sine wave signal cutting input voltage of amplitude as 250V; But the residue after the cutting partly; Obviously greater than the residue part with 250V direct current signal cutting input voltage, the residue of cutting is partly few more, and the power that need carry out the conventional power conversion is few more; Efficient is also just high more, and the complete cutoff signal that this D.C. regulated power supply adopts is shown in Figure 102 1B.If input ac voltage is 220V, output dc voltage 250V, then the input voltage area is P1=220*1.414*2=622 (V), and the head area of slicing is P2=51.45, and overall efficiency can be calculated as follows:
The flat-top steamed bun wave voltage area of output is P1-P2=(622-51.45)=570.55 on the resistance R 8; This conversion efficiency partly is 100%, and head area 51.45 need carry out the conventional power conversion, and efficient is 85%; Then this available power partly is 51.45*85%=43.73; Overall efficiency is: (570.55+43.75)/622=98.75%, when output voltage was higher, overall efficiency was also higher.
Embodiment 5: ac uninterrupted power supply UPS.
On the circuit of alternating current steady voltage plug, additional direct voltage place in circuit and output voltage controlling circuit just become uninterrupted power supply UPS, physical circuit such as Figure 22.
Power device Q4, Q10, Q5, Q11, Q6, Q12 form three A type basic circuit SBP-A, and as the switch work of alternating voltage, the three is referred to as output voltage controlling circuit, and this circuit is the some (please refer to alternating current steady voltage plug) of alternating current steady voltage plug.When input voltage during in normal range (NR), the SBP-A that joins with port Vi starts, and input voltage forms pressure drop on source resistance R2, become output voltage V o; When input voltage was too high, the SBP-A that joins with port Va started, and the voltage Va that clipper circuit produces forms pressure drop on resistance R 2, become output voltage V o; Cross when low when input voltage, the SBP-A that joins with port Vc starts, and the voltage Vc that compensating circuit produces forms pressure drop on resistance R 2, become output voltage V o.
The A type basic circuit SBP-A that power device Q9, Q3 form is a charge-discharge circuit; The A type basic circuit SBP-A that power device Q2, Q8 form is the polarity of voltage change-over circuit; The A type basic circuit SBP-A that power device Q1, Q7 form is a square wave conversion circuit, and the three is referred to as the direct voltage place in circuit.When battery tension was lower than rated value, Q3 started, and to storage battery V13 charging, when battery tension was higher than rated value, Q3 broke off input ac voltage Vi, stopped charging through D3, Q3.
During mains failure, input voltage Vi is zero, and Q9 starts, battery tension through Q9, D9 output cycle 20ms, pulsewidth 10ms, with the synchronous positive square-wave voltage of civil power; Before during the 10ms, this voltage divides two-way, leads up to D1, Q1, on resistance R, forms the positive half cycle of square-wave voltage Vp, another road voltage through D2, Q2 and D14 to capacitor C 1 charging, negative just down capacitance voltage Vc5 in the formation; During the back 10ms; The storage battery no-output; The positive pole of voltage Vc5 on the capacitor C 5 is through Q8, D8 ground connection, and its negative pole forms the negative half period of square-wave voltage Vp through D7, Q7 on resistance R 1, and the 50Hz square-wave voltage Vp of formation directly gets into the input voltage bus on the resistance R 1.
After square-wave voltage Vp gets into the input voltage bus; According to being higher than, being lower than two kinds of situation of rated voltage, just the same during with alternating voltage, carry out identical processing and control; Cut during promptly greater than rated value; Compensate during less than rated value, the result of cutting and compensation, output voltage V o is sine voltage (please refer to dc inverter).
Embodiment 9: exchange constant-current supply.
Figure 27 exchanges constant-current supply, and the A type basic circuit SBP-A by Q47, Q48 form meets output resistance R17 in its common drain; At source resistance R10, the last parallel voltage-stabilizing diode respectively of R11 D39, D38, can know that by the power MOS pipe characteristic drain-source current is only relevant with grid voltage; When grid voltage is constant (by voltage stabilizing didoe D39, D38 voltage stabilizing), its drain-source current is also constant, when load changes; Or input voltage is when changing, and output current is constant.Figure 102 7A is the simulation waveform of output current, and when load resistance R17 changed to 50 Europe from 10 Europe, it is constant that output current keeps; Figure 102 7B is the simulation waveform of output voltage, and when load resistance R17 changed to 50 Europe from 10 Europe, the last output voltage of R17 changed to 280V from 60V, explained that also load current is constant.
Embodiment 10: direct current constant voltage supply.
Figure 28 is the direct current constant voltage supply, and the full-bridge that the input civil power is formed through D15, D16, D25, D26 is put in order the steamed bun wave voltage behind the circuit, is added in the drain electrode of metal-oxide-semiconductor Q29; Be added in simultaneously on the voltage-stabiliser tube heap by resistance R 1 and voltage-stabiliser tube D21, D23, D24, D27 series connection; Each voltage-stabiliser tube is 75V, and the gate clamped of Q1 is at the 300V level, and its source electrode is through resistance R 8 ground connection; Then on R8, produce the flat-top steamed bun wave voltage of 300V slicing; This voltage is added in the source electrode of metal-oxide-semiconductor Q30 through resistance R 7, and its drain electrode is through resistance R 9 ground connection, and the grid source electrode meets voltage stabilizing didoe D17.According to the characteristic of metal-oxide-semiconductor, drain-source current is only relevant with grid voltage, and grid voltage is constant, and drain-source current is also constant, and now at certain level, so its drain-source current is constant, the output continuous current by voltage stabilizing didoe D3 clamper for the grid voltage of Q30; When the resistance of load resistance R5 increased to that voltage surpasses permissible value on it, Q29 export constant voltage, has limited the R5 output voltage and has continued to increase, maintenance constant voltage function.
Figure 102 8A is the simulation waveform of output current, and load resistance R4 changes to 30 Europe from 8 Europe, and the electric current that flows through load resistance R18 is constant basically; Figure 102 8B is the simulation waveform of output voltage, and load resistance R18 changes to 30 Europe from 8 Europe, and voltage changes to 200V from 50V on it, explains that the electric current that wherein passes through keeps constant.
Embodiment 11: accessory power supply.
Figure 29 is an accessory power supply, and metal-oxide-semiconductor Q15, Q17 in the circuit, Q16, Q18 form two A type symmetry primitive SBPA; Their common source is connecting resistance R4, R5 respectively, constitutes A type basic circuit SBP-A, and external power supply V20 is an amplitude 311V civil power; Drive signal V14, V18, V15, V19 are the square waves of cycle 20ms, pulsewidth 1ms, and time-delay is successively: 0ms, 10ms, 9ms, 19ms, get the interval voltage of sinusoidal wave zero passage front and back 1ms respectively; Like Figure 102 9A is the simulation waveform of each point voltage, is successively from top to bottom: input ac voltage Vi, gate drive voltage V1, V2, V3, V4; Output voltage V p on the resistance R 4, the output voltage V n on the resistance R 5.V1-V4 is the interval selection pulse, can see, strobe pulse and output voltage tip interval are corresponding one by one.Figure 102 9B is the positive and negative symmetrical direct voltage behind excessive capacitor filtering, and amplitude if select distinct pulse widths, can obtain the output dc voltage of different amplitudes near 80V.
Electric network pollution; Power factor is low; Main cause is that too many capacitive load is arranged, and the characteristics of capacitive load are only to utilize near the interval little part voltage sinusoidal wave peak value, if utilize sine voltage from the interval that zero passage begins; Not only develop a big treasure-house of the energy, and can improve the pollution level of electrical network greatly.
This accessory power supply has utilized the interval sine voltage of zero cross near just, suitably selects the pulsewidth of metal-oxide-semiconductor drive signal, wants how low boost voltage, how lowly just can have.When selecting drive signal pulsewidth 0.5ms, the output symmetrical voltage is about 30V, and this voltage also can obtain direct-flow positive voltage after the rectification.
Embodiment 12: polarity inversion power supply.
Figure 30 is the polarity inversion power supply, and function is the polarity negate voltage.The series arm of the common source connecting resistance R5 of metal-oxide-semiconductor Q1, Q12 and C7, D20, the minus earth of D20, input voltage V12 is a positive voltage, drive signal V9, V10 are the square waves of 50Hz.During the preceding 10ms, the Q11 conducting, V12 forms the square-wave voltage of 10ms on resistance R 5, charge to capacitor C 7 through D20 simultaneously, and is negative just down on the polarity; When second 10ms arrived, Q11 ended, the Q12 conducting, and the positive voltage terminal ground connection of C7, diode D17 is the output negative voltage, so on resistance R 6, obtain the losing side wave voltage of 10ms.The simulation waveform of Figure 103 0 is a positive negative pulse stuffing voltage, obtain symmetrical direct current output, can strengthen filter capacitor, and in fact, the circuit on Figure 49 left side also is a square wave inverting power source.The polarity inversion power supply is often used in follow-up embodiment.
Embodiment 13: AC to AC N rank booster power.
Figure 31 is AC to AC N rank booster powers, and the right and left circuit is symmetry fully, and existing is example with N=4.Metal-oxide-semiconductor Q11, Q4 form A type symmetry primitive, and source electrode meets N rank boost capacitor network UPnet, the symmetrical primitive that Q1, Q8 form, and 1, two symmetrical primitive of its common source connecting resistance R1 and capacitor C all is connected into A type basic circuit SBP-A.For boost capacitor network first rank; Between positive half period, Q11 is logical, and V34 charges to capacitor C 2 through diode D7, D11, D17 and Q23; Between negative half-cycle; The Q4 conducting, to capacitor C 3 chargings, other three rank charging modes of boost capacitor network are identical through diode D9, D12, D18 and Q38 for V34.Charging and discharge are carried out simultaneously, between positive half period, and Q4, Q15, Q21, Q27, Q8 conducting; On resistance R 1, form the negative sense pressure drop behind the last voltage superposition of capacitor C 3, C10, C17, C23; Between negative half-cycle, Q11, Q18, Q24, Q30, Q1 conducting form forward voltage drop behind the last voltage superposition of capacitor C 2, C9, C16, C22 on resistance R 1; Charging and discharge hocket, and output voltage V o is than input voltage V11 hysteresis half period.Figure 103 1 is the simulation waveform of output voltage, and intermediate sinusoids is the 311V mains waveform, and skin is the square-wave output voltage that has boosted near 1200V.
The efficient of this power supply can be estimated as follows:
Load resistance R1 is 1k, output voltage 1200V, and output current 1.2A then, positive half cycle is that superposition is exported with voltage on the negative half period network capacitance, charging current can think identical with discharging current.The diode forward saturation voltage drop is 1.2V, and metal-oxide-semiconductor saturation conduction resistance is 0.75 Europe, and each charge tunnel has three diodes, a metal-oxide-semiconductor, and its voltage loss is:
U1＝1.2*3+0.75*1.2＝4.5V
Because the circuit of electric capacity charging is connected, electric current is identical, and the computational efficiency voltage available replaces, and the voltage loss of four charge tunnels simultaneously is identical, and the efficiency eta 1 when then charging is:
η1＝(311-4.5)/311＝98.56％
Discharge channel has four metal-oxide-semiconductors, a diode, and voltage loss is:
U2＝0.75*4*1.2+1.2＝4.8V
As a same reason, discharging efficiency η 2 is:
η2＝(1200-4.8)/1200＝99.6％
So, gross efficiency η=η 1* η 2=98.56%*99.6%=98.17%
Embodiment 21: AC to AC N rank voltage dropping power supply.
Figure 39 is AC to AC N rank voltage dropping power supplies, and the right and left circuit is symmetry fully, and existing is example with N=4.Metal-oxide-semiconductor Q4, Q1 form A type symmetry primitive, and its common source meets N rank decompression capacitor network DNnet, meets output resistance R1 in its drain electrode.For left side circuit, between positive half period, V7 charges to capacitor C 1, C7, C13, C19 through diode D1, D13, D31, D49; Q2 conducting simultaneously, capacitor C 2, C8, C14, C20 parallel discharge produce negative voltage on resistance R 1; Between negative half-cycle, V7 charges to capacitor C 2, C8, C14, C20 through diode D4, D16, D34, D52, Q4 conducting simultaneously; Capacitor C 1, C7, C13, C19 parallel discharge produce forward voltage on resistance R 1.Between charge period, four capacitances in series, interdischarge interval, four electric capacity parallel connections, therefore, the voltage Vo on the resistance R 1 is 1/4th of input voltage V7.Figure 103 9 is simulation waveforms of output voltage, and sine wave is the 311V mains waveform, and the centre is the square-wave output voltage that has been depressured to 77V.
The efficient of this power supply can be estimated as follows:
Load resistance R1 is 77 Europe, output voltage 77V, and output current 1A then, the diode forward saturation voltage drop is 1.2V, and metal-oxide-semiconductor saturation conduction resistance is 0.75 Europe, and each charge tunnel has four diodes, and its voltage loss is:
U1＝1.2*4＝4.8V
Because the circuit to the electric capacity charging is connected, electric current is identical, and the computational efficiency voltage available replaces, and the efficiency eta 1 during charging is:
η1＝(Vi-U1)/Vi＝(311-4.8)/311＝98.46％
Discharge channel has 1 metal-oxide-semiconductor, 2 diodes, and voltage loss is:
U2＝0.75*1+1.2*2＝1.95V
Voltage is during discharge:
U3＝(311-4.8)/4＝76.55
As a same reason, discharging efficiency η 2 is:
η2＝(U3-U2)/U3＝(76.55-1.95)/76.55＝97.45％
So, gross efficiency η=η 1* η 2=98.46%*97.45%=95.94%
Embodiment 25: the full insulating power supply of AC to AC N rank step-down.
Figure 43 is the full insulating power supply of AC to AC N rank step-down; Compare with AC to AC N rank voltage dropping power supply, charging and discharge separate fully, and left side circuit has increased metal-oxide-semiconductor Q13, Q32; The right circuit has increased Q16, Q38, the metal-oxide-semiconductor conducting of increase and by synchronous with civil power.Figure 104 3 is simulation waveforms of output voltage, is the waveform of input voltage Vi above, is the output waveform of output voltage V o below.
Embodiment 26: AC to AC N rank lowering and stabilizing blood pressure power supply.
Figure 44 is AC to AC N rank lowering and stabilizing blood pressure power supplys, compares with the AC to AC N rank stabilized voltage power supply of boosting, and only with the decompression capacitor network boost capacitor network that replaced, the operation principle and the course of work are identical.Figure 104 4 is simulation waveforms of output voltage, is that input voltage Vi, killer voltage Vc, output voltage V o, TX1 pay polygonal voltage Vs, output voltage V ob from top to bottom successively.
Embodiment 27: DC-to-DC N rank ultralow pressure high-current supply.
Figure 45 is DC-to-DC N rank ultralow pressure high-current supplies, and the right and left circuit is identical, is phase lag 10ms, during the charging of left side electric capacity, and the right capacitor discharge, vice versa.Compare with AC to AC N rank voltage dropping power supply; The D1 of power input, D2 have changed metal-oxide-semiconductor Q1, Q2 into; This is because direct current input time, break-make that must the control voltage 20ms cycle, and Q1, Q2 that output links to each other with resistance R 1 are constant; All the other all diodes all change metal-oxide-semiconductor into, and the polarity of decision metal-oxide-semiconductor and the principle of direction are: make that the direction of the interior diode of metal-oxide-semiconductor body is identical with the direction of original diode.In the time of not conducting of metal-oxide-semiconductor, entire circuit also can be worked, and only the saturation voltage drop of diode is 1.2V in the metal-oxide-semiconductor body, and is relatively too big, when the in good time conducting of metal-oxide-semiconductor, is equivalent to the saturation voltage drop short circuit diode, improved overall efficiency greatly.IRF4004 operating current 350A, the forward saturation resistance has only 0.00135 Europe, through the 100A electric current, its saturation voltage drop 0.135V.Figure 79 is the simulation waveform of DC-to-DC N rank ultralow pressure high-current supply output voltage, and the upper strata curve is the voltage on the capacitor C 3, and lower floor is that curve is output voltage V o; Can find out input direct voltage V15=4V, four times of step-down chargings from simulation waveform; The voltage that electric capacity obtains explains that near 1V the charging loss is minimum, and output voltage is 0.97V; Explain in the discharge process that about 4 times of voltage discharge total losses 1.2V, establishing input current is Ii; Output current is 4Ii, and then overall efficiency can be estimated as follows:
η＝Wo/Wi＝(Vo*Io)/(Vi*Ii)＝0.97*4*Ii/4*Ii＝0.97*4/4＝97％
Embodiment 28: computer power.
Figure 46 is a computer power, and two partly about circuit divided, and left part part is an alternating current 220V to 50V circuit and 50V to the 12V circuit, and right part part is 12V to 5V and 12V to the 3.3V circuit.Input voltage V27 is the 288V direct voltage that Figure 21 D.C. regulated power supply produces, and is added on the positive half cycle circuit of AC to AC 6 rank voltage dropping power supplies, and its output voltage is V48; Voltage V48 is added in the input of DC-to-DC 4 rank ultralow pressure power supplys, obtains voltage V12 at its output, can make the adjustment object of AHM equivalent resistance into V12, and then V12 is exactly stable 12V direct voltage.
The input voltage of the right circuit is V12; Upper part is the voltage cutting circuit; Because input voltage is a direct current, killer voltage produces circuit and voltage cutting circuit itself all only needs positive half cycle circuit partly, and metal-oxide-semiconductor Q19 has formed the cutting drive signal generation circuit; The constant amplitude square signal of the high Vgs of generation amplitude specific output voltage V10; The amplitude of this signal is by panel height modulation equivalent resistance AHM200 (V10) 1 control, and its mark meaning is: panel height modulation equivalent resistance adjustable extent is 200 Europe, and detected object is voltage V10.Q21 and TX1 form the voltage cutting circuit; Its source resistance R4 goes up the voltage V10 of output 10V; When output voltage V 10 changes because of input voltage V12, or when changing because of load R4, output voltage V 10 also can change; The amplitude that panel height modulation AHM regulates the gate drive signal of Q21 automatically is to keep the V10 amplitude constant.Change the no-load voltage ratio of TX1, amplitude that can coarse adjustment secondary output voltage Vob, the duty ratio of regulating constant amplitude cutting square-wave signal, amplitude that can fine tuning output voltage V ob, the amplitude of Vob equates with V10, and line output.Figure 47 lower right is two independently DC-to-DC N rank ultralow pressure power supplys, and left side circuit N=2 becomes 5V to voltage V10 step-down, and the right circuit N=3 becomes 3.3V to voltage V10 step-down.
Figure 104 6A is the simulation waveform of output voltage; Be respectively from top to bottom: the voltage V48 about the 50V that produces by the 220V civil power, the stable+12V voltage V12 that produces by V48, the stable+5V voltage V05 that produces by 12V voltage, the stable+3.3V voltage V33 that produces by V12; Figure 104 6B simulation waveform shows that with identical space details is seen clearlyer to every kind of voltage.
Embodiment 29: communication power supply.
Figure 47 is a communication power supply, and its circuit divides three partly, and the left side first partly is complete AC-to DC 4 rank voltage dropping power supplies, and input voltage is civil power Vi, and output voltage V o is the direct voltage about 70V, is the charge in batteries voltage summary height of 48V than nominal voltage.
Second partly forms complete UPS without power consumption by metal-oxide-semiconductor Q10, Q11; Its charging, discharge control; Voltage detecting and storage battery testing circuit are all identical, and here, input voltage is not the steamed bun wave voltage after the rectification; But the direct voltage Vo of AC-to DC 4 rank voltage dropping power supplies output, the detection signal of LM339 is not AC signal but direct current signal.
The 3rd partly is the direct current clipper circuit, identical with the direct current clipper circuit of computer power.
The input civil power is through first partly after the AC-to DC 4 rank voltage dropping power supplies; Direct voltage Vo about output 70V, this voltage are added in the input of the uninterrupted voltage of no power consumption of Q10, Q11 composition, when battery tension is lower than rated value; Storage battery testing circuit output high level; Switch S 1 closure, drive signal V7 makes the Q10 conducting, and Vo passes through diode D20 to charge in batteries; When battery tension is higher than rated value, storage battery testing circuit output low level, switch S 1 is broken off, and Q10 ends, and storage battery stops charging.Meanwhile; Voltage Vo is added on the direct current clipper circuit of Q12, Q13 composition; The stable 48V direct voltage Va of output on its source resistance; Residual voltage after Vo is cut is added in transformer TX2 and carries out the conventional power conversion, and the direct voltage Vb that transformer is paid limit circuit output is identical with the amplitude of voltage Va, parallel connection output.When mains failure or when being lower than rated value; LM339 output high level in the voltage detecting circuit; Switch S 2 closures; Drive signal V10 makes the Q11 conducting, and battery tension is added to through diode D26 on the direct current clipper circuit of being made up of Q12, Q13, and the following course of work is identical when not having a power failure with civil power; When the city power recovery just often, produce voltage Vo, the course of work with have a power failure before not the same, the LM339 output low level in the voltage detecting circuit at this moment, switch S 1 disconnection, Q10 ends, the battery tension disconnection.
Figure 104 7A is the simulation waveform of AC-to DC 4 rank voltage dropping power supply output voltages and electric current; The about 40A of output current Io; About output voltage 70V, Figure 104 7B is the output voltage V a of direct current clipper circuit generation and the simulation waveform that transformer is paid limit output voltage V b, and Va, Vb are equal basically.
Embodiment 31: power factor corrector PFC;
Figure 49 is a power factor corrector, is actually an AC to AC 5 rank booster powers, and difference is all to change charging diode into metal-oxide-semiconductor, with the charging opportunity of electric capacity in the control boost network.
When input current and input voltage fully synchronously the time, the definition power factor is 1, and asynchronous more, power factor is low more.The capacitive load of rectifying and wave-filtering, its power factor is very low, and reason is that the steamed bun wave voltage after the rectification charges to electric capacity; Direct voltage on the electric capacity; The capital is charged to the amplitude near the steamed bun ripple, and exhausted most amplitude is less than those moment of direct voltage on the capacitor, and input voltage has no chance electric capacity is charged; At these constantly, input current is zero; Have only amplitude those moment, just have an opportunity to the capacitor charging, in this very short time greater than direct voltage on the capacitor; Holocyclic average current is provided; So the peak value of input current is quite big, this has just caused input current and input voltage very asynchronous, and power factor is very low.
In order to improve power factor, must make input current and input voltage synchronous, at each constantly promptly, no matter amplitude is big or small, and input voltage is all had an opportunity to the electric capacity charging, and charging could produce input current.
The method that employing AC to AC 5 rank booster powers carry out power factor correction is following: all be divided into five five equilibriums to positive-negative half-cycle, between the civil power positive half period, to capacitor C 1 charging 2ms, Q11 fills 2ms through D11 to capacitor C 4 to Q2 through D7, or the like; Between the civil power negative half-cycle, to capacitor C 3 charging 2ms, Q14 passes through D12 to capacitor C 5 charging 2ms to Q8 through D6, or the like.So, in the whole cycle, no matter amplitude is big or small, and input voltage all has an opportunity electric capacity is charged.Positive half cycle charging is accomplished, and the voltage on the capacitor is in negative half period stack output, and the negative half period charging is accomplished; Voltage on the capacitor is in positive half cycle stack output; Voltage on each electric capacity of capacitance network is unequal, and the input voltage amplitude is relevant constantly with this electric capacity charging end of a period, and Figure 104 9A is the simulation waveform of output voltage; Input ac voltage 220V, output dc voltage is near 1000V.
Make input current and input voltage more synchronous, can increase exponent number, exponent number is big more; Input current is more synchronous with input voltage; Figure 104 9B is N=0, input current waveform when promptly not adding power factor correction, input current waveform when Figure 104 9C is N=5; Input current waveform when Figure 104 9D is N=10, input current waveform when Figure 104 9E is N=20.
Embodiment 32: high-frequency and high-voltage high power factor direct current power supply.
Figure 50 is the high-frequency and high-voltage high power factor direct current power supply, on the basis of 5 rank power factor correctors, has increased the cutoff signal of being made up of metal-oxide-semiconductor Q21, Q22 and has produced circuit, and the cutoff signal of generation is Vg.V12 is the square wave of 50Hz; Time-delay 10ms; The drive signal of Q21, Q22 is V9, V10, all is the square-wave signal of 18V, 1kHz (frequency is low be for emulation time observe easily), therefore;, the waveform of the cutoff signal Vg that Q21, Q22 produced is that envelope is the square wave of 50Hz, the square-wave signal of modulating frequency 1kHz.
The output stage of 5 rank power factor correctors is made up of Q1, Q4; Its drive signal was the square wave of time-delay 10ms, 50Hz originally; The output voltage V o that on common source resistance R1, obtains is the square-wave voltage of amplitude 1000V, 50Hz; What be added in Q11, Q12 grid now is that envelope is the square-wave signal Vg of 50Hz square wave, modulating frequency 1kHz, and then on common source resistance R1, having obtained output voltage amplitude 1000V, envelope is the square-wave voltage Vo of 50Hz square wave, modulating frequency 1kHz.Figure 105 0A is the output voltage simulation waveform, and waveform is stabilized in about 1000V from low to high, and the frequency of envelope square wave is 50Hz, comprises ten modulated square waves in each square wave, and the waveform of output voltage V o and drive signal Vg are identical.Figure 105 0B is the waveform of the output voltage V o that amplified, and details can see clearlyer.Figure 105 0C is the simulation waveform of input voltage and input current, and what input voltage showed here is-Sinx,, can be found out by analogous diagram that input current and input voltage are synchronous fully so that observe better and more synchronous degree, and power factor can reach more than 99%.
Embodiment 34: three-phase ac regulated power supply.
Figure 55 is a three-phase ac regulated power supply, metal-oxide-semiconductor Q1, Q7, Q2, Q8; Q3, Q9 form three A type basic circuit SBP-A, and input three-phase voltage Via, Vib, Vic receive their input respectively, and the grid working point is respectively by resistance R 1, R7; R2, R9; R3, R11 decision, at stable three-phase alternating current output voltage V a, Vb, the Vc of the last acquisition of their source resistance R8, R10, R12, the principle of stabilized voltage of every circuitry phase is in aforementioned.Figure 105 5 is simulation waveforms of three-phase ac regulated power supply output voltage, and skin is an input voltage waveform, and nexine is an output voltage waveforms, and adjusting resistance R 1, R2, R3 can regulate output voltage amplitude.
When the precision of voltage regulation is high, replace R1, R2, R3, can directly adjust automatically output voltage with panel height modulation equivalent resistance; When the difference Vm of input voltage and output voltage was excessive, available C type basic circuit SPB-C replaced A type basic circuit SBP-A, and pressure reduction Vm is carried out the conventional power conversion, feedback to input or directly output.
Embodiment 35: three phase alternating inverse power supply.
Figure 56 is a three phase alternating inverse power supply; The circuit of each phase is all identical with Figure 31 ac inverter; Because input is a three-phase voltage; Gate drive signal in every phase active rectification is identical with the phase place of this phase input voltage, the output voltage V ca of every phase D type active rectification, Vcb, Vcc all with this mains input voltage Via, Vib, Vic series connection mutually, the voltage after the overlapped in series is output voltage Ac, Bc, the Cc of ac inverter.Figure 105 6 is simulation waveforms of output voltage; 3 sets of curves are arranged among the figure; 1 group 3 of innermost layers are compensation voltage plot Vca, Vcb, Vcc; 1 group of 3 curve of outermost layer are output voltage Ac, Bc, the Cc after input voltage and the bucking voltage stack, and middle 1 group of 3 curve is input voltage Via, Vib, Vic.
The input phase voltage of three phase alternating inverse power supply low excessively (amplitude 280V); The specified phase voltage (amplitude 311V) of its output has been passed through the ac converter compensation; This embodiment is also claimed the three-phase alternating current offset supply; Bucking voltage Vca, Vcb, Vcc can independently export, and other circuit are carried out the three-phase alternating current compensation.
Practical implementation ten thousand formulas 36: three-phase dc inverter.
Figure 57 is the three-phase dc inverter; Metal-oxide-semiconductor Q4, Q10, Q5, Q11, Q6, Q12 form three A type basic circuit SBP-A; Direct current input positive voltage V+ gets into Q4, Q5, Q6 through D4, D5, D6 respectively; Direct current input negative voltage V-gets into Q10, Q11, Q12 through D12, D13, D14 respectively, and the grid of three basic circuits meets the sine wave drive signal of 120 degree that lag behind successively, the high Vgs of the amplitude specific output voltage of signal respectively; According to the voltage cutting principle, at three-phase sine wave voltage Va, Vb, the Vc of last 120 degree that obtain to lag behind successively of source resistance R4, R5, the R6 of three basic circuits.Figure 105 7 is simulation waveforms of three-phase dc inverter output voltage; The amplitude of three-phase sine wave voltage is near input direct voltage; DC input voitage is reverse into three-phase alternating voltage, has only passed through link, i.e. a voltage cutting; This inverter circuit efficient height and loss is little, this embodiment is also claimed the direct current cutting power supply.In order further to raise the efficiency, available C type basic circuit SPB-C replaces A type basic circuit SBP-A, and the residual voltage after the cutting is carried out the conventional power conversion, feedbacks to input or directly output.
Embodiment 37: three-phase alternating current cutting power supply.
Figure 58 is the three-phase alternating current cutting power supply, and all to exchange clipper circuit identical with Figure 35 for the circuit of each phase, because input is a three-phase voltage, the gate drive signal in every phase D type active rectification is identical with the phase place of this phase input voltage.Figure 105 8 is simulation waveforms of output voltage; 3 sets of curves are arranged among the figure; 1 group 3 of outermost layers are input voltage curve Via, Vib, Vic; Nexine has 2 groups of 6 curves to be respectively cutting sine voltage Voa, Vob, Voc and to carry out output voltage V a, Vb, Vc behind conventional power conversion and the active rectification through transformer TX1, and to pay the limit output voltage amplitude very approaching owing to cut sine voltage and transformer; Two sets of curves overlap basically, and it is much thicker than the curve of input three-phase voltage that curve seems.
Embodiment 38: three-phase alternating current uninterrupted power supply UPS.
Figure 59 is three-phase uninterrupted power supply UPS, and circuit divides 3 partly among the figure, and each partly is a phase; Three-phase circuit is identical; 4 kinds of input voltages are arranged: mains input voltage Vai, Vbi, Vci, voltage Va, Vb, Vc that dc inversion becomes to exchange, voltage Voa, Vob, Voc when input voltage is too high after the process cutting; Input voltage is crossed when hanging down through voltage Ac, Bc, Cc behind the voltage compensation, a kind of output voltage: VA, VB, VC.The function of the A type basic circuit that metal-oxide-semiconductor Q13, Q16 form is the A phase voltage of incoming transport civil power, and the function of the A type basic circuit that Q19, Q23 form is the master switch as three-phase uninterrupted power supply A phase.The positive half cycle of 4 kinds of voltages is received the drain electrode of metal-oxide-semiconductor Q19 through diode D31-D34; Negative half period is received the drain electrode of metal-oxide-semiconductor Q23 through diode D43-D46; Because positive-negative half-cycle is separated; The voltage of positive half cycle can not interfere with each other in the drain electrode of Q19, and the voltage of negative half period can not interfere with each other in the drain electrode of Q23.When civil power just often, Q13, Q16 conducting, civil power is exported A phase voltage VA through D31, D43 on resistance R 16; Cross when low when civil power, voltage Ac export A phase voltage VA through D34, D46 on resistance R 16, and the while is shut output channel diode D31, the D43 of civil power; When civil power was too high, Q13, Q16 ended, and voltage Voa exports A phase voltage VA through D33, D45 on resistance R 16; When the city had a power failure, dc inversion voltage Va exported A phase voltage VA through D32, D44 on resistance R 16.Metal-oxide-semiconductor Q10, Q13 open in the overall process of uninterrupted power supply operation, only when three-phase uninterrupted power supply UPS withdraws from use or extraneous load short circuits fully, just end.
B is mutually identical with A with the course of work of C circuitry phase mutually.
Figure 59 is the complete circuit of three-phase alternating current uninterrupted power supply; Comprise that it is the three-phase alternating current offset supply that line voltage is crossed low generation bucking voltage; Comprise that the too high generation killer voltage of line voltage is the three-phase cutting power supply, produce dc inversion voltage three-phase dc inverter when comprising mains failure.If produce dc inversion voltage and diode that all join with it when Figure 59 circuit does not comprise mains failure, then three-phase alternating current uninterrupted power supply UPS just becomes complete three-phase ac regulated power supply; If Figure 59 circuit includes only a circuitry phase, then three-phase alternating current uninterrupted power supply UPS just becomes single phase alternating current (A.C.) uninterrupted power supply UPS.
Explain: all circuit diagrams all come from the SIMetrix/SIMPLIS of power electronics simulation software 5.60 in the Figure of description, can not add to revise direct emulation, obtain identical output waveform.

Claims (5)

1. a power inverter comprises element circuit, it is characterized in that:
The FET Q1 of element circuit is the N raceway groove, and FET Q2 is the P raceway groove; The positive pole of diode D1 links to each other with the negative pole of diode D2, constitutes terminal A, and the drain electrode of FET Q1 links to each other with the negative pole of diode D1; Its source electrode connects terminal B, and the drain electrode of FET Q2 links to each other with the positive pole of diode D2, and its source electrode connects terminal B; The grid of FET Q1 connects the positive pole of drive signal V1; The negative pole of drive signal V1 connects terminal B, and the grid of FET Q2 connects the negative pole of drive signal V2, and the positive pole of drive signal V2 connects terminal B.
2. a kind of power inverter as claimed in claim 1 comprises basic circuit,
Basic circuit is made up of said element circuit and resistance R 1, and the terminal A of element circuit connects the live wire of input voltage vin, and resistance R 1 is connected between the terminal B of zero line and element circuit of input voltage vin, and the terminal B of element circuit is exactly the output of basic circuit; Between the terminal B of element circuit and ground, can also connect boost capacitor network (UPnet) and decompression capacitor network (DNnet), replace resistance R 1.
3. a kind of power inverter as claimed in claim 1 comprises the active rectification circuit,
The active rectification circuit is made up of described element circuit and two resistance R 1, R2; Two FET Q1 of element circuit, the source electrode of Q2 are separately; The end of the source electrode connecting resistance R1 of FET Q1 constitutes exit point P+, the end of the source electrode connecting resistance R2 of FET Q2; Constitute another termination exit point N of exit point N-, resistance R 1, R2, the terminal A of element circuit constitutes input endpoint L.
4. a kind of power inverter as claimed in claim 1 is characterized in that:
Drive signal V1, V2 are produced by high-frequency driving signal generator (VDrvh) and synchronized signal generator (VDrvs):
1) high-frequency driving signal generator (VDrvh) is made up of integrated circuit NE555 and signal conversion circuit (SPrs), DC power supply V3, V4 series connection, middle ground; The negative pole of direct voltage V3 connects pin GND, the capacitor C 1 of NE555, the end of C2; The positive pole of direct voltage V4 meets pin Vcc, the Reset of NE555, an end of resistance R 7, the pin Thresh of another termination NE555 of capacitor C 1, the pin Cntrl of another termination NE555 of capacitor C 2; The pin Dis of another termination NE555 of resistance; The positive pole of diode D1 meets the pin Dis of NE555, and its negative pole meets the pin Trig of NE555, diode D2 and resistance R 6 series connection; The positive pole of diode D2 meets the pin Thresh of NE555; The pin Dis of another termination NE555 of diode D6, the pin Out of NE555 meets the end points IN of signal conversion circuit SPrs, the end points GND ground connection of signal conversion circuit SPrs through resistance R 3;
2) synchronized signal generator (VDrvs) is made up of integrated circuit LM339 and signal conversion circuit (SPrs); DC power supply V4, V5 series connection, middle ground, the negative pole of direct voltage V4 connect the supply pin of LM339-; The positive pole of direct voltage V5 connect the supply pin of LM339+with an end of resistance R 8; The exit point Gc of another termination LM339 of resistance R 8, an end ground connection of the negative pole of power supply V3 and resistance R 6, the homophase input pin of another termination LM339 of resistance R 6+; The positive pole of power supply V3 through resistance R 7 connect the homophase input pin of LM339+; Anti-phase input pin-ground connection of LM339, the exit point Gc of LM339 meets the end points IN of signal conversion circuit SPrs, the end points GND ground connection of signal conversion circuit (SPrs) through resistance R 3;
3) signal conversion circuit (SPrs) is made up of optocoupler U1, U2, and the diode of optocoupler U1 negative electrode partly meets input endpoint IN, and its anode meets end points GND; The triode of optocoupler U1 emitter partly connects the negative pole of power supply V2 through resistance; Connect the collector electrode of triode Q2 simultaneously, the triode of optocoupler U1 collector electrode partly connects the positive pole of power supply V1, connects the collector electrode of triode Q1 simultaneously;, triode Q1, Q2 emitter be connected together and constitute exit point Gb, meet end points GND through resistance R 2 simultaneously; The diode of optocoupler U2 anode partly meets input endpoint IN; Its negative electrode meets end points GND, and the triode of optocoupler U2 emitter partly connects the negative pole of power supply V2 through resistance, connects the collector electrode of triode Q4 simultaneously; The triode of optocoupler U2 collector electrode partly connects the positive pole of power supply V1; Connect the collector electrode of triode Q3 simultaneously,, the emitter of triode Q3, Q4 is connected together and constitutes exit point Ga, meets end points GND through resistance R 5 simultaneously.
5. a kind of power inverter as claimed in claim 2 is characterized in that:
Boost capacitor network (UPnet) and decompression capacitor network (DNnet) are made up of N rank capacitance network, two arms about every rank all have:
1) left arm of boost capacitor network (UPNet): the negative electrode of diode D1 connects an end of capacitor C 1; Form the starting point Begin1 on these rank, the anode of another terminating diode D3 of capacitor C 1 and the drain electrode of FET Q2, the source electrode of FET forms the terminal point End1 on these rank; The anode of diode connects the input positive source; The negative electrode of diode connects the input power cathode, the right arm of boost capacitor network (UPNet): the anode of diode D2 connects an end of capacitor C 2, forms the starting point Begin2 on these rank; The negative electrode of another terminating diode D4 of capacitor C 2 and the drain electrode of FET Q1; The source electrode of FET Q1 is formed the terminal point End2 on these rank, and the negative electrode of diode connects the input power cathode, and the anode of diode connects the input positive source;
2) left arm of decompression capacitor network (DNnet): the anode of diode D1 connects an end of capacitor C 1, forms the terminal B egin1 on these rank, the negative electrode of another terminating diode D3 of capacitor C 1; Form the end points End1 on these rank, the negative electrode of diode connects the positive pole of output voltage, and the anode of diode connects the negative pole of output voltage; The right arm of decompression capacitor network (DNnet): the negative electrode of diode D2 connects an end of capacitor C 2; Form the terminal B egin2 on these rank, the negative electrode of another terminating diode D4 of capacitor C 2 forms the end points End2 on these rank; The anode of diode connects the negative pole of output voltage, and the negative electrode of diode D4 connects the positive pole of output voltage; The end points End of last single order meets down the terminal B egin of single order, forms multistage boost capacitor network and multistage decompression capacitor network; Envelope is sinusoidal wave square wave driving signal (VEnvl).
CN2010201450421U 2010-03-29 2010-03-29 Green power inverter Expired - Fee Related CN202127352U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110168928A (en) * 2016-12-09 2019-08-23 先进能源工业公司 Gate driving circuit and its control method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110168928A (en) * 2016-12-09 2019-08-23 先进能源工业公司 Gate driving circuit and its control method
CN110168928B (en) * 2016-12-09 2023-04-25 先进能源工业公司 Gate driving circuit and control method thereof

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