CN202121517U - Dead-zone time regulating circuit for phase shift control circuit - Google Patents
Dead-zone time regulating circuit for phase shift control circuit Download PDFInfo
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- CN202121517U CN202121517U CN2011202066560U CN201120206656U CN202121517U CN 202121517 U CN202121517 U CN 202121517U CN 2011202066560 U CN2011202066560 U CN 2011202066560U CN 201120206656 U CN201120206656 U CN 201120206656U CN 202121517 U CN202121517 U CN 202121517U
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- dead time
- time regulating
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Abstract
The utility model provides a dead-zone time regulating circuit for a phase shift control circuit, which relates to the electronic circuit technology. The dead-zone time regulating circuit for the phase shift control circuit comprises an original dead-zone time detecting loop and a dead-zone time regulating loop, wherein the original dead-zone time detecting loop is connected with the phase shift control circuit and is used for carrying out logical OR operation on output signals of the shift phase control circuit; the dead-zone time regulating loop is connected with the original dead-zone time detecting circuit; and the dead-zone time regulating loop comprises a monostabillity trigger as well as an adjustable resistor and an adjustable capacitor that are connected with the monostabillity trigger and are used for adjusting dead-zone time. With the adoption of the dead-zone time regulating circuit for the phase shift control circuit, the dead-zone time of the phase shift control circuit is adjusted, and the requirements of different circuits can be met. The dead-zone time regulating circuit is simple and practical and has high reliability.
Description
Technical field
The utility model relates to electronic circuit technology, particularly relates to a kind of Dead Time regulating circuit that is used for phase-shift control circuit.
Background technology
Along with the continuous maturation of insulated gate bipolar transistor (IGBT) inversion transformation technique, the major loop topological structure of the soft switch of full-bridge phase-shifting resonance obtains increasing application.Existing phase shifting control chip commonly used is such as UC3875; UC3879, UC3895, they have a common feature; Be exactly self Dead Time maximum limited (such as self Dead Time of UC3875 less than 2.5uS), the not enough especially 1uS of self Dead Time of UC3879 and UC3895.And in many inverters,, need bigger Dead Time for realizing soft preferably switch effect, prevent that IGBT is straight-through, improving reliability.
The utility model content
The purpose of the utility model is to propose a kind of Dead Time regulating circuit that is used for phase-shift control circuit, makes the Dead Time of phase-shift control circuit can access adjustment.
For realizing above-mentioned purpose, the utility model provides a kind of Dead Time regulating circuit that is used for phase-shift control circuit, comprising: original Dead Time detecting circuit, be connected with phase-shift control circuit, and the output signal of phase-shift control circuit is carried out the computing of logic OR; The Dead Time regulating loop is connected with original Dead Time detecting circuit, and the Dead Time regulating loop comprises monostable flipflop, and the adjustable resistance and the tunable capacitor that are connected with monostable flipflop, be used to regulate Dead Time.
In one embodiment, the Dead Time regulating circuit also comprises: control voltage source, be connected with the Dead Time regulating loop, and be used to the Dead Time regulating loop control voltage reference is provided.
In one embodiment, control voltage source comprises the adjustable voltage stabilizing a reference source of three ends.
In one embodiment, the Dead Time regulating circuit also comprises: PWM stack and letter sorting loop, be connected with the Dead Time regulating loop, and the output signal of Dead Time regulating loop is superposeed and sorts.
In one embodiment, the non-computing of logic OR is done to the output signal of Dead Time regulating loop and the output signal of PWM start and stop control loop in PWM stack loop.
In one embodiment, the monostable flipflop of Dead Time regulating loop comprises 555 chips.
In one embodiment, the discharge pin of 555 chips is connected with adjustable resistance, and the threshold voltage pin of 555 chips is connected with tunable capacitor.
Based on technique scheme, according to the one side of the utility model,, can regulate the Dead Time of phase-shift control circuit through original Dead Time detecting circuit and Dead Time regulating loop, satisfy the demand of different circuit.Its circuit is simple and practical, reliability is high.
Description of drawings
Accompanying drawing described herein is used to provide the further explanation to the utility model, constitutes the part of the utility model.Illustrative examples of the utility model and explanation thereof only are used to explain the utility model, but do not constitute the improper qualification to the utility model.In the accompanying drawings:
Fig. 1 is the sketch map according to the Dead Time regulating circuit that is used for phase-shift control circuit of the utility model embodiment.
Fig. 2 is the sketch map according to the Dead Time regulating circuit that is used for phase-shift control circuit of another embodiment of the utility model.
Fig. 3 is the Dead Time regulating circuit figure that is used for phase-shift control circuit according to the another embodiment of the utility model.
Fig. 4 is that the circuit logic according to the utility model embodiment concerns key diagram.
Embodiment
With reference to the accompanying drawings the utility model is described in more detail, the exemplary embodiment of the utility model wherein is described.In the accompanying drawings, identical label is represented identical or similar assembly or element.
Fig. 1 is the signal Figure 100 according to the Dead Time regulating circuit that is used for phase-shift control circuit of the utility model embodiment.Signal Figure 100 of Dead Time regulating circuit comprises phase-shift control circuit 102, original Dead Time detecting circuit 104 and Dead Time regulating loop 106.
Original Dead Time detecting circuit 104 is connected with phase-shift control circuit 102, the output signal of phase-shift control circuit 102 is carried out the computing of logic OR.
Dead Time regulating loop 106 is connected with original Dead Time detecting circuit 104.Dead Time regulating loop 106 comprises monostable flipflop, and the adjustable resistance and the tunable capacitor that are connected with monostable flipflop, be used to regulate Dead Time.
According to the one side of the utility model, through original Dead Time detecting circuit and Dead Time regulating loop, can regulate the Dead Time of phase-shift control circuit, satisfy the demand of different circuit.Its circuit is simple and practical, reliability is high.
Fig. 2 is the signal Figure 200 according to the Dead Time regulating circuit that is used for phase-shift control circuit of another embodiment of the utility model.Signal Figure 200 of Dead Time regulating circuit comprises phase-shift control circuit 202, original Dead Time detecting circuit 204, Dead Time regulating loop 206, control voltage source 208, PWM stack loop 210 and PWM start and stop control loop 212.
Original Dead Time detecting circuit 204 is connected with phase-shift control circuit 202, the output signal of phase-shift control circuit 202 is carried out the computing of logic OR.In one embodiment, original Dead Time detecting circuit 204 can be realized by two CMOS NOR gates, also can use other logic gates that can reach identical function to realize.
Dead Time regulating loop 206 is connected with original Dead Time detecting circuit 204.Dead Time regulating loop 206 comprises monostable flipflop, and the adjustable resistance and the tunable capacitor that are connected with monostable flipflop, be used to regulate Dead Time.In one embodiment, the monostable flipflop of Dead Time regulating loop 206 can be 555 chips.Wherein, the discharge pin of 555 chips can be connected with adjustable resistance, and the threshold voltage pin of 555 chips can be connected with tunable capacitor.Size through adjustment adjustable resistance and electric capacity can change Dead Time, satisfies different circuit requirements.
PWM stack and letter sorting loop 210 are connected with Dead Time regulating loop 206, and the output signal of Dead Time regulating loop 206 is superposeed and sorts.Wherein, the non-computing of logic OR can be done to the output signal of Dead Time regulating loop 206 and the output signal of PWM start and stop control loop 212 in PWM stack letter sorting loop.Wherein, when PWM start and stop control loop 212 output high potentials, PWM will be blocked; During PWM start and stop control loop 212 output electronegative potentials, PWM opens.PWM start and stop change-over time short, speed is fast.PWM stack loop 210 can be realized by a NOR gate, also can use other logic gates that can reach identical function to realize.
Fig. 3 is the Dead Time regulating circuit Figure 30 0 that is used for phase-shift control circuit according to the another embodiment of the utility model.Dead Time regulating circuit Figure 30 0 comprises: comprise phase-shift control circuit 302, original Dead Time detecting circuit 304, Dead Time regulating loop 306, control voltage source 308, PWM stack loop 310, PWM letter sorting loop 311 and PWM start and stop control loop 312.
Original Dead Time detecting circuit 304 can comprise CMOS type NOR gate IC3D, IC3C.Wherein, IC3C is connected into the form of logic inverter.This part loop also can use other logic gates that reaches identical function to realize.
Dead Time regulating loop 306 can comprise IC4, capacitor C 1, C3, C4 and resistance R 4.Wherein, IC4 can be for being connected into CMOS type 555 chips of monostable flipflop.Can change the Dead Time of phase-shift control circuit 302 through adjustment resistance R 4, capacitor C 3 sizes, satisfy different circuit requirements.
PWM letter sorting loop 311 can comprise CMOS type and door IC2A, IC2B.
Fig. 4 is that the circuit logic according to the utility model embodiment concerns key diagram.Circuit logic relation shown in Figure 4 is the waveform sketch map of the key point among Fig. 3 embodiment.Wherein, OUTA, the corresponding original PWM waveform of OUTB, PWMA, the corresponding adjustment of PWMB back PWM waveform.Visible by scheming, the Dead Time Δ t1 before the Dead Time Δ t2 of adjustment back PWM adjusts increases to some extent, and added value is by resistance R 4, capacitor C 3 sizes and the control of control magnitude of voltage in the Dead Time regulating loop 306 among Fig. 3.
One side according to the utility model; Original Dead Time detecting circuit can comprise CMOS type logic gates; The Dead Time regulating loop can comprise CMOS type 555 chips; The control voltage reference of Dead Time regulating loop can comprise TL431, and the PWM stack can comprise CMOS type logic gates with the letter sorting loop, guarantees high speed property, the accuracy of circuit with this.Under the situation that does not increase other components and parts, but the start and stop of quick control PWM.Entire circuit can only be made up of 2 kinds of gate chips, a kind of 555 sequence circuit, and is simple and practical, reliability is high.
The description of the utility model provides for example with for the purpose of describing, and is not exhaustively perhaps the utility model to be limited to disclosed form.A lot of modifications and variation are obvious for those of ordinary skill in the art.Selecting and describing embodiment is principle and practical application for better explanation the utility model, thereby and makes those of ordinary skill in the art can understand the various embodiment that have various modifications that the utility model design is suitable for special-purpose.
Claims (7)
1. a Dead Time regulating circuit that is used for phase-shift control circuit is characterized in that, comprising:
Original Dead Time detecting circuit is connected with said phase-shift control circuit, the output signal of said phase-shift control circuit is carried out the computing of logic OR;
The Dead Time regulating loop is connected with said original Dead Time detecting circuit, and said Dead Time regulating loop comprises monostable flipflop, and the adjustable resistance and the tunable capacitor that are connected with said monostable flipflop, be used to regulate Dead Time.
2. Dead Time regulating circuit according to claim 1 is characterized in that, also comprises:
Control voltage source is connected with said Dead Time regulating loop, is used to said Dead Time regulating loop the control voltage reference is provided.
3. Dead Time regulating circuit according to claim 2, wherein, said control voltage source comprises the adjustable voltage stabilizing a reference source of three ends.
4. Dead Time regulating circuit according to claim 1 and 2 is characterized in that, also comprises:
PWM stack and letter sorting loop are connected with said Dead Time regulating loop, and the output signal of said Dead Time regulating loop is superposeed and sorts.
5. Dead Time regulating circuit according to claim 4, wherein, the non-computing of logic OR is done to the output signal of said Dead Time regulating loop and the output signal of PWM start and stop control loop in PWM stack loop.
6. Dead Time regulating circuit according to claim 1, wherein, the monostable flipflop of said Dead Time regulating loop comprises 555 chips.
7. Dead Time regulating circuit according to claim 6, wherein, the discharge pin of said 555 chips is connected with adjustable resistance, and the threshold voltage pin of said 555 chips is connected with tunable capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202066560U CN202121517U (en) | 2011-06-20 | 2011-06-20 | Dead-zone time regulating circuit for phase shift control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202066560U CN202121517U (en) | 2011-06-20 | 2011-06-20 | Dead-zone time regulating circuit for phase shift control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202121517U true CN202121517U (en) | 2012-01-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011202066560U Expired - Lifetime CN202121517U (en) | 2011-06-20 | 2011-06-20 | Dead-zone time regulating circuit for phase shift control circuit |
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| Country | Link |
|---|---|
| CN (1) | CN202121517U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103516354A (en) * | 2013-10-23 | 2014-01-15 | 江南大学 | Electromagnetism resonance type wireless electric energy transmission lock phase frequency tracking circuit |
| CN112532121A (en) * | 2020-12-03 | 2021-03-19 | 中国电子科技集团公司第二十四研究所 | Three-phase brushless motor driving circuit, three-phase brushless motor driver and compensation method |
-
2011
- 2011-06-20 CN CN2011202066560U patent/CN202121517U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103516354A (en) * | 2013-10-23 | 2014-01-15 | 江南大学 | Electromagnetism resonance type wireless electric energy transmission lock phase frequency tracking circuit |
| CN103516354B (en) * | 2013-10-23 | 2016-02-10 | 江南大学 | Electromagentic resonance formula wireless power transmission frequency of phase locking tracking circuit |
| CN112532121A (en) * | 2020-12-03 | 2021-03-19 | 中国电子科技集团公司第二十四研究所 | Three-phase brushless motor driving circuit, three-phase brushless motor driver and compensation method |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120118 |
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| CX01 | Expiry of patent term |