CN202120898U - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
- Publication number
- CN202120898U CN202120898U CN2011201943885U CN201120194388U CN202120898U CN 202120898 U CN202120898 U CN 202120898U CN 2011201943885 U CN2011201943885 U CN 2011201943885U CN 201120194388 U CN201120194388 U CN 201120194388U CN 202120898 U CN202120898 U CN 202120898U
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- CN
- China
- Prior art keywords
- semiconductor package
- sticking brilliant
- crystal grain
- raceway groove
- sticking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a semiconductor packaging structure comprising a grain, a lead frame and a grain-bonding glue line. A grain-bonding part, a middle part and a pin part are sequentially arranged in the lead frame from inside to outside, wherein the grain-bonding part is concavely provided with a plurality of channels right below the grain; and the grain-bonding glue line is filled in a plurality of channels and is bonded with grains. Therefore, more space is provided between the border of grains and the pin when delamination of the grain-bonding glue line is restrained.
Description
Technical field
The utility model is about a kind of semiconductor package, refers to that especially a kind of square plane that is applicable to do not have pin package (Quad Flat Non-leaded; QFN), can reduce the semiconductor package of delamination problems.
Background technology
Existing semiconductor grain is to seal with the adhesive body of an insulate heat thermosetting resin (Encapsulated body); Avoid the infringement of external environment in order to the protection chip; And with the electric connection of lead frame as the chip and the printed circuit board (PCB) of semiconductor packages, for example outer pin does not have pin package (QFN) on the square plane of packaging body surrounding.
With reference to figure 1, be a kind of existing semiconductor package phantom.The existing encapsulating structure of icon be earlier lead frame 1 in order to the plane of carrying crystal grain 3 on direct coating one sticking brilliant glue-line 4, again crystal grain 3 is placed on the sticking brilliant glue-line 4, reach the fixedly purpose of crystal grain 3 of adhesion.Usually can stipulate enough that for guaranteeing adherence sticking brilliant glue material need overflow crystal grain 3 edges one specific range D.The sticking brilliant glue material that the shortcoming of the existing encapsulating structure of this kind is to overflow crystal grain 3 edges has the possibility of the pin portion 2 of being infected with lead frame 1.
With reference to figure 2, be the existing semiconductor package phantom of another kind.The existing encapsulating structure of icon is that the position on lead frame 5, beyond crystal grain 8 edges is arranged with a raceway groove 7; Make the sticking brilliant glue-line 9 of coating in lead frame 5 and after putting crystal grain 8; But sticking brilliant glue material overflow reduces sticking brilliant glue material thus and is infected with the situation of lead frame pin portion 6 to raceway groove 7.Yet the existing encapsulating structure of this kind has reduced the free space of routing (wire bonding) because of 7 of raceway grooves occupy.
The utility model content
The main purpose of the utility model is that a kind of semiconductor package is being provided, and can under the prerequisite that reduces delamination problems, promote the free space of playing ground wire.
Reach above-mentioned purpose, the semiconductor package of the utility model comprises a crystal grain, a lead frame and a sticking brilliant glue-line.
Above-mentioned lead frame defines sticking brilliant portion, a pars intermedia and a pin portion from inside to outside in regular turn, and wherein sticking brilliant portion is concaved with a plurality of raceway grooves, and raceway groove is to be arranged under the crystal grain especially.Above-mentioned sticking brilliant glue-line is to be filled in a plurality of raceway grooves on the one hand, is adhering to crystal grain on the one hand, makes the crystal grain relative fixed on lead frame.
Above-mentioned a plurality of raceway groove can be the U-shaped raceway groove, and the plane of sticking brilliant portion can be low than pars intermedia, further promotes sticking brilliant glue-line degree of adhesion thus.Above-mentioned a plurality of raceway groove also can be other shape, for example is a plurality of straight inclined-planes raceway grooves, and likewise, the plane of sticking brilliant portion can be low than pars intermedia.
Above-mentioned a plurality of raceway groove can be designed to all kinds how much, is arranged with the surface that is arranged in sticking brilliant portion.For example, be a multi-level degree of lip-rounding arrangement, be X-shaped to look squarely observation, or an X-shaped raceway groove, an outside degree of lip-rounding raceway groove that centers on the X-shaped raceway groove and the combination that crisscrosses an inboard degree of lip-rounding raceway groove of X-shaped raceway groove.
The lead frame material can be alloy.Crystal grain can be to see through a lead-in wire to be connected in pin portion.
The beneficial effect of the utility model:
Through said structure design, sticking brilliant glue-line is because of a plurality of raceway grooves promote bond strength, suppressed the delamination situation between itself and lead frame.In addition, because moving, the raceway groove of former crystal grain edge to pin portion is located at sticking brilliant portion, so the space between crystal grain edge and the pin portion can more flexibly use; For example, the distance that lead-in wire connects between crystal grain edge and the pin portion can shorten, and increases the lead-in wire bonding strength; In addition, the cost of lead-in wire also can be saved.
Description of drawings
Fig. 1 is existing semiconductor package phantom.
Fig. 2 is another kind of existing semiconductor package phantom.
Fig. 3 is the preceding semiconductor package vertical view of the sticking crystalline substance of the utility model first preferred embodiment.
Fig. 4 is the sticking brilliant back semiconductor package vertical view of the utility model first preferred embodiment.
Fig. 5 is the semiconductor package phantom of the utility model first preferred embodiment.
Fig. 6 is the semiconductor package phantom of the utility model second preferred embodiment.
Fig. 7 is the semiconductor package phantom of the utility model the 3rd preferred embodiment.
Fig. 8 is the semiconductor package phantom of the utility model the 4th preferred embodiment.
Fig. 9 is the preceding semiconductor package vertical view of the sticking crystalline substance of the utility model the 5th preferred embodiment.
Figure 10 is the preceding semiconductor package vertical view of the sticking crystalline substance of the utility model the 6th preferred embodiment.
The main element symbol description
Pars intermedia 12,31,37,42 pin portions 13
Sticking brilliant glue- line 21,34,40,45 lead-in wires 22
Capping layer 23 X-shaped raceway grooves 51,53
Long and narrow raceway groove 51a, 51b degree of lip-rounding raceway groove 54,55
Embodiment
With reference to figure 3～Fig. 5, be respectively the forward and backward semiconductor package vertical view of sticking crystalline substance and the phantom of first preferred embodiment.Semiconductor package shown in the figure mainly comprises a lead frame 10, a crystal grain 20, one a sticking brilliant glue-line 21 and a capping layer 23.From inside to outside, lead frame 10 comprises sticking brilliant portion 11 (zone that dotted line is represented), a pars intermedia 12 and a pin portion 13 successively.
Aforementioned sticking brilliant portion 11 is concaved with a plurality of raceway grooves 14.In the present embodiment, a plurality of raceway grooves 14 are viewed as a plurality of degree of lip-rounding raceway grooves to look squarely, and are multi-level arrangement, and each raceway groove 14 is for having the U-shaped raceway groove of U-shaped wall profile.
When gluing crystalline substance, will glue brilliant glue material earlier and be coated on formation one sticking brilliant glue-line 21 in the predetermined sticking brilliant portion 11, be placed on crystal grain 20 on the sticking brilliant glue-line 21 more at last.Behind the sticking crystalline substance, a plurality of raceway grooves 14 are positioned at (also being positioned at sticking brilliant portion 11 scopes) under the crystal grain 20, and sticking brilliant glue-line 21 is filled in a plurality of raceway grooves 14 on the one hand, also crystal grain 20 is adhered to firmly on the one hand.
Just get a lead-in wire 22 after the sticking brilliant step, two ends are welded in crystal grain 20 and pin portion 13 respectively.And then carry out the forming step of capping layer, the two is all prior art, repeats no more in this.
In this example, lead frame 10 is an alloy material, and sticking brilliant glue material is that epoxy resin (expoxy) capping layer 23 is with moulded section, covers crystal grain 20 and lead-in wire 22.
Owing to offer a plurality of raceway grooves 14 in sticking brilliant portion 11, therefore sticking brilliant glue-line 21 more closely is bonded in lead frame 10, suppresses the generation of delamination.In addition, this encapsulating structure must not be subject to the rule of the excessive glue in four sides yet, but has therefore enlarged usage space between crystal grain edge to the pin portion.
With reference to figure 6, be the semiconductor package phantom of second preferred embodiment.The present embodiment and first example are similar, under sticking brilliant portion 30, crystal grain 33, are concaved with a plurality of raceway grooves 32 equally, and a sticking brilliant glue-line 34 is filled in a plurality of raceway grooves 32 on the one hand, also crystal grain 33 adhesions are lived on the one hand.Specifically, in this example, the plane of sticking brilliant portion 30 is low than pars intermedia 31, but not flushes with pars intermedia 12 like the sticking brilliant portion 11 of Fig. 5.Such structure has better tackability compared to first example, more suppresses delamination problems.
With reference to figure 7, be the semiconductor package phantom of the 3rd preferred embodiment.The present embodiment and first example are similar, under sticking brilliant portion 36, crystal grain 39, are concaved with a plurality of raceway grooves 38 equally, and a sticking brilliant glue-line 40 is filled in a plurality of raceway grooves 38 on the one hand, also crystal grain 39 adhesions are lived on the one hand.Specifically, in this example, each raceway groove 38 is a straight inclined-plane raceway groove.Such structure has sticking brilliant glue-line equally and more closely is bonded in lead frame, suppresses the advantage of the generation of delamination, must not be subject to the rule of the excessive glue in four sides too, is pars intermedia 37 usage spaces but therefore enlarged between crystal grain edge to the pin portion.
With reference to figure 8, be the semiconductor package phantom of the 4th preferred embodiment.Present embodiment and the 3rd example are similar, under sticking brilliant portion 41, crystal grain 44, are concaved with a plurality of straight inclined-planes raceway groove 43 equally, and a sticking brilliant glue-line 45 is filled in a plurality of raceway grooves 43 on the one hand, also crystal grain 44 adhesions are lived on the one hand.Specifically, in this example, the position, plane of sticking brilliant portion 41 is accurate to be low than pars intermedia 42, but not flushes with pars intermedia 37 like the sticking brilliant portion 36 of Fig. 7.Such structure has better tackability compared to the 3rd example, more suppresses delamination problems.
With reference to figure 9, be the preceding semiconductor package vertical view of sticking crystalline substance of the 5th preferred embodiment.Present embodiment stresses that mainly a plurality of raceway grooves are meant two staggered long and narrow raceway groove 51a, and 51b constitutes an X-shaped raceway groove 51 to look squarely to observe, and is arranged with the surface that is arranged in sticking brilliant portion 52.
With reference to Figure 10, be the preceding semiconductor package vertical view of sticking crystalline substance of the 6th preferred embodiment.Present embodiment mainly stress a plurality of raceway grooves be meant an X-shaped raceway groove 53, around an outside degree of lip-rounding raceway groove 55 of X-shaped raceway groove 53 and the combination that crisscrosses an inboard degree of lip-rounding raceway groove 54 of X-shaped raceway groove 53, be arranged with the surface that is arranged in sticking brilliant portion 56.
The foregoing description only is to explain for ease and give an example, and the interest field that the utility model is advocated is from should being as the criterion so that claim is said, but not only limits to the foregoing description.
Claims (10)
1. a semiconductor package is characterized in that, comprising:
One crystal grain;
One lead frame defines sticking brilliant portion, a pars intermedia and a pin portion from inside to outside in regular turn, and wherein should sticking brilliant portion being concaved with a plurality of raceway grooves is to be positioned under this crystal grain; And
One sticking brilliant glue-line is filled in these a plurality of raceway grooves and adheres to this crystal grain.
2. semiconductor package as claimed in claim 1 is characterized in that, these a plurality of raceway grooves are the U-shaped raceway groove.
3. semiconductor package as claimed in claim 2 is characterized in that, the plane of this sticking brilliant portion is low than this pars intermedia.
4. semiconductor package as claimed in claim 1 is characterized in that, these a plurality of raceway grooves are a plurality of straight inclined-planes raceway grooves.
5. semiconductor package as claimed in claim 4 is characterized in that, the plane of this sticking brilliant portion is low than this pars intermedia.
6. semiconductor package as claimed in claim 1 is characterized in that, these a plurality of raceway grooves are a multi-level degree of lip-rounding and are arranged with and are arranged in the surface that this glues brilliant portion to look squarely to observe.
7. semiconductor package as claimed in claim 1 is characterized in that, these a plurality of raceway grooves are X-shaped and are arranged with the surface that is arranged in this sticking brilliant portion.
8. semiconductor package as claimed in claim 1; It is characterized in that; These a plurality of raceway grooves are an X-shaped raceway groove, an outside degree of lip-rounding raceway groove that centers on this X-shaped raceway groove and the combination that crisscrosses an inboard degree of lip-rounding raceway groove of this X-shaped raceway groove, are arranged with the surface that is arranged in this sticking brilliant portion.
9. semiconductor package as claimed in claim 1 is characterized in that, this lead frame is an alloy material.
10. semiconductor package as claimed in claim 1 is characterized in that, this crystal grain sees through a lead-in wire and is connected in this pin portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201943885U CN202120898U (en) | 2011-06-10 | 2011-06-10 | Semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201943885U CN202120898U (en) | 2011-06-10 | 2011-06-10 | Semiconductor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202120898U true CN202120898U (en) | 2012-01-18 |
Family
ID=45461939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011201943885U Expired - Fee Related CN202120898U (en) | 2011-06-10 | 2011-06-10 | Semiconductor packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202120898U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022188071A1 (en) * | 2021-03-10 | 2022-09-15 | Innoscience (suzhou) Semiconductor Co., Ltd. | Iii-nitride-based semiconductor packaged structure and method for manufacturing thereof |
-
2011
- 2011-06-10 CN CN2011201943885U patent/CN202120898U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022188071A1 (en) * | 2021-03-10 | 2022-09-15 | Innoscience (suzhou) Semiconductor Co., Ltd. | Iii-nitride-based semiconductor packaged structure and method for manufacturing thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120118 Termination date: 20160610 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |