CN202110902U

CN202110902U - Novel chip of pressure sensitive resistor

Info

Publication number: CN202110902U
Application number: CN2011202428345U
Authority: CN
Inventors: 张俊峰; 夏波
Original assignee: SHAANXI HUAXING ELECTRONIC GROUP CO Ltd
Current assignee: SHAANXI HUAXING ELECTRONIC GROUP CO Ltd
Priority date: 2011-07-02
Filing date: 2011-07-02
Publication date: 2012-01-11
Anticipated expiration: 2021-07-02

Abstract

The utility model discloses a novel chip of a pressure sensitive resistor, which comprises a chip body and a composite electrode layer coated on the surface of the chip body. The novel chip of the pressure sensitive resistor is not only good in conductive performance but also low in manufacture cost.

Description

Novel varistor chip

Technical field

The utility model relates to electronic devices and components, relates in particular to a kind of novel varistor chip.

Background technology

Existing varistor chip is made up of chip body and the silver electrode layer that adheres to chip body surface, though silver has good electrical conductivity and welding performance; Because the price comparison of silver is high; Thereby make that the said silver electrode layer cost of manufacturing is higher, so the silver electrode layer is all made thinlyyer in traditional typography; The silver-colored situation of erosion appears easily, thus the performance of influence conduction.

The utility model content

The utility model purpose has been to provide a kind of not only have excellent conductive performance and the lower novel varistor chip of manufacturing cost.

A kind of novel varistor chip that the utility model provides, it comprises: chip body and the combination electrode layer that is coated on the surface of said chip body.

Preferably, said combination electrode layer comprises the silver electrode layer on the surface that is coated on said chip body and the copper electrode layer that is coated on said silver electrode laminar surface.

The utility model varistor chip is provided with the combination electrode layer, and said combination electrode layer not only has excellent conducting performance and manufacturing cost is lower.

Description of drawings

Accompanying drawing described herein is used to provide the further understanding to the utility model, constitutes the application's a part, does not constitute the improper qualification to the utility model, in the accompanying drawings:

Fig. 1 is the structural representation of the utility model varistor chip;

Fig. 2 is another visual angle figure of Fig. 1;

Fig. 3 is another visual angle figure of Fig. 1.

Embodiment

To combine accompanying drawing and specific embodiment to specify the utility model below, be used for explaining the utility model in the illustrative examples and the explanation of this utility model, but not as the qualification to the utility model.

Please referring to figs. 1 through Fig. 3, the utility model provides a kind of novel varistor chip, and it comprises: chip body 1 and the combination electrode layer 2 that is coated on the surface of said chip body 1.The copper electrode layer 22 that said combination electrode layer 2 comprises the silver electrode layer 21 on the surface that is coated on said chip body 1 and is coated on said silver electrode layer 21 surface; Said copper electrode layer 22 can form excellent electrical property with silver electrode layer 21 and contact, and silver electrode layer 21 can form excellent electrical property with ceramic surface and contact.

When making said novel varistor chip, at first, at the silver electrode layer 21 of the surface-coated white of chip body 1; Then, at the aeneous copper electrode layer 22 of surface-coated one deck of said silver electrode layer 21, constitute said combination electrode layer 2.

Compared with prior art, the benefit of the utility model is:

(1), said combination electrode layer is made up of silver electrode layer and said copper electrode layer, ag material and copper product all have excellent conducting performance, thereby make that stating the combination electrode layer has excellent conducting performance;

(2), because the silver electrode laminar surface is coated with the copper electrode layer; It can avoid the silver electrode layer situation of erosion silver to occur; Guarantee that said novel varistor chip has excellent conducting performance, simultaneously, the copper product price is lower; Thereby make that the manufacturing cost of said novel varistor chip is lower, help enhancing competitiveness.

More than technical scheme that the utility model embodiment is provided carried out detailed introduction; Used concrete example among this paper principle and the execution mode of the utility model embodiment are set forth, the explanation of above embodiment only is applicable to the principle that helps to understand the utility model embodiment; Simultaneously, for one of ordinary skill in the art, according to the utility model embodiment, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as the restriction to the utility model.

Claims

1. a novel varistor chip is characterized in that, comprising: chip body and the combination electrode layer that is coated on the surface of said chip body.

2. novel according to claim 1 varistor chip is characterized in that: said combination electrode layer comprises the silver electrode layer on the surface that is coated on said chip body and the copper electrode layer that is coated on said silver electrode laminar surface.