CN202083778U

CN202083778U - Integrated circuit

Info

Publication number: CN202083778U
Application number: CN201120132827XU
Authority: CN
Inventors: 李大伟; 朱建彰; 王强; 王潘丰; 邹丽娜
Original assignee: Capital Microelectronics Beijing Technology Co Ltd
Current assignee: Capital Microelectronics Beijing Technology Co Ltd
Priority date: 2011-04-29
Filing date: 2011-04-29
Publication date: 2011-12-21
Anticipated expiration: 2021-04-29

Abstract

Provided is an integrated circuit, comprising a first and second JTAG control circuits cascaded via a JTAG interface. The integrated circuit comprises a virtual JTAG control circuit and a selective circuit. WWhen the selective signal is effective, the selective circuit selects the virtual JTAG and cascades the virtual JTAG with the first JTAG control circuit while the second JTAG control circuit is bypassed; and when the selective signals is ineffective, the first JTAG control circuit and the second JTAG control circuit are cascaded. In this way, the confidential work toward the second JTAG control circuit is finished, and the cascaded JTAG module is guaranteed to be unchanged.

Description

A kind of integrated circuit

Technical field

The utility model relates to integrated circuit, relates in particular to jtag interface.

Background technology

JTAG (JointTestActionGroup; Combined testing action group) interface is that current most chip all supports this agreement to be used for the test of chip, comprises the visit to chip memory, to functions such as configurable circuit are configured by the defined group interface of ieee standard.The ultimate principle of JTAG is at TAP (Test Access Port of device inside definition; The test access mouth) tests carrying out internal node by the jtag test instrument of special use.Now, jtag interface also is usually used in realizing ISP (In-System Programmable; Online programming), devices such as flash memory FLASH are programmed.

In actual applications, jtag controller is followed certain criteria, as long as understand the operation that inner used register and employed order just can be finished entire chip, this has very big threat for chip secret.

Jtag test allows a plurality of devices to be cascaded by jtag interface, forms a JTAG chain, can realize each device is tested respectively.

Yet, when a plurality of JTAG modules of chip internal realization are passed through the jtag interface cascade, if simple masks some modules by secret indicator signal, other module that cascade then can occur can't be visited by jtag interface again, if some modules are got around (bypass) by secret indicator signal, then can cause the JTAG number of modules change of cascade, this checking and peripheral control unit design to chip has all increased very big difficulty.

The utility model content

The purpose of this utility model provides the integrated circuit that can overcome above shortcoming.

According to first aspect of the present utility model, provide a kind of integrated circuit.This integrated circuit comprises the first and second JTAG control circuits by the jtag interface cascade, also comprise virtual JTAG control circuit, the first selection module and the second selection module, wherein the TD0 output signal of a JTAG control circuit is imported the TDI input end of virtual JTAG control circuit and the first input end of the first selection module; Second input end of module is selected in the constant signal input first of numerical value; The output signal of the first selection module is imported the TDI input end of the 2nd JTAG control circuit; The TD0 output signal of the TD0 output signal of virtual JTAG control circuit and the 2nd JTAG control circuit is imported second input end and the first input end of the second selection module respectively, and second selects the output signal of module as common TD0 output signal; Wherein, first selects module and second to select the signal of module its first input end separately of difference gating under the effect of effective choice signal, the signal of its second input end separately of difference gating under the effect of invalid selection signal.

According on the other hand of the present utility model, provide a kind of integrated circuit.This integrated circuit comprises the first and second JTAG control circuits by the jtag interface cascade, described integrated circuit comprises virtual JTAG control circuit and selects circuit, wherein when selecting signal effective, select circuit to select virtual JTAG, with itself and a JTAG control circuit cascade, the 2nd JTAG control circuit is got around; When selecting invalidating signal, a JTAG control circuit and the 2nd JTAG control circuit cascade.

Description of drawings

Below with reference to accompanying drawings the utility model is described in detail, wherein:

Fig. 1 is the synoptic diagram according to the integrated circuit that comprises the JTAG chain of the utility model embodiment.

Embodiment

Fig. 1 is the synoptic diagram according to the integrated circuit that comprises the JTAG chain of the utility model embodiment.As shown in Figure 1, integrated circuit comprises two real JTAG control circuits, JTAG module D1 and D2.Four signals that signal wire is a JTAG agreement defined in left side are respectively clock input signal TCK, mode select signal TMS, test data input TDI and test data output TD0.JTAG module D1 and D2 connect by jtag interface.Specifically, the input end separately of importing JTAG module D1 and D2 respectively from the clock input signal TCK and the mode select signal TMS of outside, i.e. TCK and TMS input end.From the TDI input end of the data input signal TDI of outside input JTAG module D1, the output terminal of JTAG module D1 then is coupled to the input end TDI of JTAG module D2.

According to the utility model, integrated circuit also comprises a virtual JTAG module V.Module V utilizes the JTAG agreement to carry out a virtual simplification JTAG control circuit, can utilize hardware to realize.Module V can finish the most basic JTAG function, and shared area is very little, can not influence the allocation plan of entire chip.

In the coupling of the input end TDI of the TD0 output terminal of JTAG module D1 and JTAG module D2, introduced a MUX 10.One of input end of MUX 10 is connected to the TD0 output terminal of JTAG module D1, and its another input end is then imported fixed signal.In an example, this fixed signal is binary and value 1.The output terminal of MUX 10 is connected to the TDI input end of JTAG module D2.The control bit prot_flagn of MUX 10 is secret indicating bits, can come from internal non-volatile memory, can be the input of chip, also can be that other inner secret control circuits produce.

The TD0 output terminal of JTAG module D1 also is coupled to the TDI input end of virtual JTAG module V.

In addition, between the TD0 output terminal of JTAG module D2 and last output signal TD0, introduced a MUX 20.One of input end of MUX 20 is connected to the TD0 output terminal of JTAG module D2, and its another input end then is connected to the TD0 output terminal of JTAG module V.The output terminal of MUX 20 is connected to last output signal TD0.

The control bit prot_flagn of MUX 20 is consistent with MUX 10.When prot_flagn is effective, MUX 10 gatings are from the output signal TD0 of JTAG module D1, MUX 20 gatings are from the output signal TD0 of JTAG module D2 simultaneously, module D1 and D2 be by the jtag interface cascade, and the outside can conduct interviews to module D2 and tests by jtag interface.

When prot_flagn was invalid, MUX 10 not gating and replaced constant high level signal from the output signal TD0 of JTAG module D1, and JTAG module D2 is in idle condition under the effect of this high level signal; MUX 20 gatings come the output signal TD0 of self-virtualizing JTAG module V simultaneously.That is to say that module D1 and V carry out cascade by jtag interface, module D2 is got around, so by jtag interface all operations of module D2 is all transferred to module V, has so just reached the protection to module D2

So promptly finished security work, guaranteed that also the JTAG number of modules of cascade can not change simultaneously D2.

Obviously, the utility model described here can have many variations, and this variation can not be thought and departs from spirit and scope of the present utility model.Therefore, the change that all it will be apparent to those skilled in the art all is included within the covering scope of these claims.

Claims

1. integrated circuit, it is characterized in that comprising the first and second JTAG control circuits by the jtag interface cascade of combined testing action group, also comprise virtual JTAG control circuit, the first selection module and the second selection module, wherein the test data of JTAG control circuit output TD0 output signal is imported the test data input TDI input end of virtual JTAG control circuit and the first input end of the first selection module; Second input end of module is selected in the constant signal input first of numerical value; The output signal of the first selection module is imported the TDI input end of the 2nd JTAG control circuit; The TD0 output signal of the TD0 output signal of virtual JTAG control circuit and the 2nd JTAG control circuit is imported second input end and the first input end of the second selection module respectively, and second selects the output signal of module as common TD0 output signal; Wherein, first selects module and second to select the signal of module its first input end separately of difference gating under the effect of effective choice signal, the signal of its second input end separately of difference gating under the effect of invalid selection signal.

2. integrated circuit, it is characterized in that comprising the first and second JTAG control circuits by the jtag interface cascade, described integrated circuit comprises virtual JTAG control circuit and selects circuit, wherein when selecting signal effective, select circuit to select virtual JTAG, with itself and a JTAG control circuit cascade, the 2nd JTAG control circuit is got around; When selecting invalidating signal, a JTAG control circuit and the 2nd JTAG control circuit cascade.