CN202049996U - 增强单电极led芯片封装导电性的支架结构 - Google Patents

增强单电极led芯片封装导电性的支架结构 Download PDF

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CN202049996U
CN202049996U CN2011201265853U CN201120126585U CN202049996U CN 202049996 U CN202049996 U CN 202049996U CN 2011201265853 U CN2011201265853 U CN 2011201265853U CN 201120126585 U CN201120126585 U CN 201120126585U CN 202049996 U CN202049996 U CN 202049996U
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led
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刘振亮
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Shenzhen city Getelong Au Optronics Co
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

本实用新型公开了一种增强单电极LED芯片封装导电性的支架结构，包括LED发光管支架以及与其连接的芯片，其特征在于，所述的LED发光管支架包括一个杯形芯片放置部，所述的杯形芯片放置部其底部设置有一个凹槽，所述凹槽内填充有银胶贮胶层，所述的芯片其底部电极与银胶贮胶层相连接，所述芯片的另一电极经焊线后通过引线焊接于所述LED发光管支架的另一个引出线上，本实用新型在LED发光管支架芯片放置部增加了能够加大加厚银胶层的凹槽，且这种结构是随同LED发光管支架一起完成的，本实用新型有益效果是增强了LED芯片封装导电性及粘接力。

Description

增强单电极LED芯片封装导电性的支架结构
【技术领域】
本实用新型涉及一种增强单电极LED芯片封装导电性的支架结构。
【背景技术】
目前市面上以红色LED芯片为代表的单电极芯片在固晶时均采用在芯片底部电极加涂有含银的导电胶进行粘接及导电，由于支架底部平整度及工装设备的公差，在实际生产中会形成芯片电极底部的胶层厚薄不均匀，导致导电能力及粘接力存在差别，导电性差的芯片会逐步“瞎灯”，从产品应用层面看，同工艺的红色LED灯“瞎点”率大于蓝、绿LED灯，而它们最大区别在于红色LED芯片靠芯片底部粘着同时又靠银胶层导电，而蓝、绿LED芯片仅靠芯片底部胶层实现粘着。在单电极LED芯片封装过程中，为保证芯片发光的稳定可靠，需要对LED芯片导电胶层及粘接力进行提升。
【实用新型内容】
为解决现有技术生产的单电极LED芯片封装产品的缺点和不足，本实用新型提供一种增强单电极LED芯片封装导电性的支架结构，本实用新型在LED发光管支架底部底部增加可以加大加厚的银胶层凹槽结构，且这种结构是随同LED发光管支架生产一起完成，本实用新型能够增强LED芯片导电性及粘接力。
本实用新型采用的技术方案是，一种增强单电极LED芯片封装导电性的支架结构，包括LED发光管支架以及与其连接的芯片，其特征在于，所述的LED发光管支架包括一个杯形芯片放置部，所述的杯形芯片放置部其底部设置有一个凹槽，所述凹槽内填充有银胶贮胶层，所述的芯片其底部电极与银胶贮胶层相连接，所述芯片的另一电极经焊线后通过引线焊接于所述LED发光管支架的另一个引出线上。
根据上述特征的本实用新型，其特征还在于，所述的杯形芯片放置部其底部的凹槽断面为方形、圆形或者三角形。
本实用新型实现单电极LED芯片点亮工艺过程为：在LED发光管支架内点入导电银胶后放入芯片，经高温烧结后芯片被胶层粘接于支架上，同时底部电极被导电银胶接通，由焊线机将芯片顶部另一电极焊上引线并焊于LED发光管支架另一引出电极，封透明胶后即成为可发光的LED管。
根据上述结构的本实用新型，其有益效果在于，本实用新型在LED发光管支架芯片放置部增加了可加大加厚的银胶层的支架凹槽结构，增强了芯片封装后的导电性及粘着力，保证了芯片封装后其发光稳定可靠。
【附图说明】
下面结合附图及实施方式对本实用新型详细加以说明。
附图1为本实用新型的剖面示意图。
在图中，1、芯片；2、电极；3、底部电极；4、引线；5、LED发光管支架；6、银胶贮胶层；7、引出线；8、凹槽；11、杯形芯片放置部。
【具体实施方式】
如图1所示，本实用新型的增强单电极LED芯片封装导电性的支架结构，包括LED发光管支架5以及与其连接的芯片1，其特征在于，所述的LED发光管支架5包括一个杯形芯片放置部11，所述的杯形芯片放置部11其底部设置有一个凹槽8，所述凹槽8内填充有银胶贮胶层6，所述的芯片1其底部电极3与银胶贮胶层6相连接，所述芯片1的另一电极2经焊线后通过引线4焊接于所述LED发光管支架5的另一个引出线7上。
根据上述特征的本实用新型，其特征还在于，所述的杯形芯片放置部11其底部的凹槽8断面可以优选为方形、圆形或者三角形，本实施例为方形。

Claims (2)

1.一种增强单电极LED芯片封装导电性的支架结构，包括LED发光管支架以及与其连接的芯片，其特征在于，所述的LED发光管支架包括一个杯形芯片放置部，所述的杯形芯片放置部其底部设置有一个凹槽，所述凹槽内填充有银胶贮胶层，所述的芯片其底部电极与银胶贮胶层相连接，所述芯片的另一电极经焊线后通过引线焊接于所述LED发光管支架的另一个引出线上。
2.根据权利要求1所述的增强单电极LED 芯片封装导电性的支架结构，其特征还在于，所述的杯形芯片放置部其底部的凹槽断面为方形、圆形或者三角形。
CN2011201265853U 2011-04-25 2011-04-25 增强单电极led芯片封装导电性的支架结构 Expired - Lifetime CN202049996U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI609510B (zh) * 2014-02-04 2017-12-21 豪雅冠得光電股份有限公司 發光裝置及其製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI609510B (zh) * 2014-02-04 2017-12-21 豪雅冠得光電股份有限公司 發光裝置及其製造方法

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Effective date of registration: 20161115

Address after: 518000 Guangdong city of Shenzhen province Baoan District Fuyong Street Peace community liyuanlu Kaihui Mao Industrial Park C building third floor

Patentee after: Shenzhen city Getelong photoelectric Co Ltd

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Patentee before: Liu Zhenliang

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Address after: 518000, Guangdong, Baoan District Fuyong Street Fenghuang community fourth industrial zone, plant 2, a layer of 101, two, 201, Shenzhen

Patentee after: Shenzhen city Getelong Au Optronics Co

Address before: 518000 Guangdong city of Shenzhen province Baoan District Fuyong Street Peace community liyuanlu Kaihui Mao Industrial Park C building third floor

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