CN202025733U - Semiconductor-packaging structure - Google Patents

Semiconductor-packaging structure Download PDF

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Publication number
CN202025733U
CN202025733U CN201120102151XU CN201120102151U CN202025733U CN 202025733 U CN202025733 U CN 202025733U CN 201120102151X U CN201120102151X U CN 201120102151XU CN 201120102151 U CN201120102151 U CN 201120102151U CN 202025733 U CN202025733 U CN 202025733U
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CN
China
Prior art keywords
chip
substrate
golden finger
bonding area
glutinous brilliant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201120102151XU
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Chinese (zh)
Inventor
陈有增
蔡和洁
张郁雯
蔡嘉真
刘智铭
段吉运
张家荣
刘耿宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunyuan Technology Co Ltd
Original Assignee
Kunyuan Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunyuan Technology Co Ltd filed Critical Kunyuan Technology Co Ltd
Priority to CN201120102151XU priority Critical patent/CN202025733U/en
Application granted granted Critical
Publication of CN202025733U publication Critical patent/CN202025733U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model discloses a semiconductor-packaging structure, which comprises a substrate, an insulating varnish layer, chip-bonding adhesive and a chip. At least one golden finger area and a chip-bonding area which are spaced from each other are defined on the top surface of the substrate, and the insulating varnish layer is formed on the other area of the top surface of the substrate, except the golden finger areas and the chip-bonding area. The chip-bonding adhesive is applied in the chip-bonding area, and the chip is bonded on the chip-bonding adhesive. Consequently, when the chip is placed on the chip-bonding adhesive, the chip-bonding adhesive cannot be easily spilled out to stain golden fingers, and thereby discarded products are reduced.

Description

Semiconductor package
Technical field
The utility model relates to semiconductor package, refers to a kind of semiconductor package of avoiding the glutinous brilliant glue problem of overflowing especially.
Background technology
In the semiconductor element packaging technology, when chip is cut to, an inferior step is that it is adhered on the substrate, that is the glutinous crystalline substance that is commonly called as.The glutinous brilliant material that uses is the stickiness glued membrane for example, but the element cost is too high and adhesive tape waste material amount is big, uses the glutinous brilliant glue of pasty state instead so also have at present, but uses the glutinous brilliant glue excessive glue situation is easily arranged, and will cause encapsulating the fraction defective increase.
With reference to figure 1,2A, 2B, be respectively existing and be coated with the substrate front view of glutinous brilliant glue, finish glutinous brilliant substrate front view and cutaway view.A substrate 91 shown in the figure defines a plurality of golden fingers (finger) zone 911~913 in end face, and the substrate top surface other parts beyond the golden finger zone 911~913 then are formed with an insulation enamelled coating 92.Expose the golden finger that is useful on electrical welding in the above-mentioned golden finger zone 911~913.Golden finger zone 911~913 is centered around near the chip 94 predetermined zones of placing basically.
When sticking brilliant step, the glutinous brilliant glue 93 with appropriate amount is uniformly coated on chip 94 predetermined zones of placing earlier, chip is placed on the glutinous brilliant glue 93 again.Be generally expected that glutinous brilliant glue 93 can be covered with 94 ends of chip, and for guaranteeing above-mentioned purpose, can stipulate that usually one differentiates the door of glutinous brilliant failure, if for example being specified in chip 94 each side overflows sizing material length overall D2 less than 70% of the long D1 of this side, then judges failure.
In Fig. 2 A, promptly demonstrate glutinous brilliant glue amount and control improper and the glue that causes overflowing, and then pollute the situation of golden finger 914, so will scrap whole material, reduce and produce yield.
The utility model content
Main purpose of the present utility model provides a kind of semiconductor package, so as to solve existing when brilliant step institute the glue problem of overflowing takes place.
For reaching above-mentioned purpose, semiconductor package of the present utility model comprises a substrate, an insulation enamelled coating, a glutinous brilliant glue and a chip.The end face of aforesaid substrate defines an at least one golden finger zone and a crystal bonding area territory that separates, and the insulation enamelled coating then is formed at other zone of the substrate top surface beyond golden finger zone and the crystal bonding area territory.Glutinous brilliant glue is to coat within the crystal bonding area territory, and chip then is attached on the brilliant glue.
By the design of above-mentioned semiconductor package, because of insulation enamelled coating itself has certain thickness, constitute a groove structure around the crystal bonding area territory, glutinous brilliant glue can be limited in the groove structure during last chip, and it is regional and pollute golden finger near golden finger to be not easy to overflow.The utility model reduces the situation of product rejection in the packaging technology, promotes the technology yield.
Above-mentioned golden finger zone can be positioned at chip periphery.Aforesaid substrate can be the printed circuit board (PCB) that the crystal bonding area territory has exposed circuit pattern or do not have exposed circuit pattern for the crystal bonding area territory.Glutinous brilliant glue can be insulating cement or nonisulated glue.
The utility model reduces compared to the existing semiconductor package enamelled coating consumption that not only insulate, and has also avoided so can reduce the ratio that goods are scrapped, great advantage being arranged aspect manufacturing cost because of excessive glue pollutes golden finger.
Description of drawings
Fig. 1 is the existing substrate front view that is coated with glutinous brilliant glue;
Fig. 2 A is for finishing glutinous brilliant substrate front view;
Fig. 2 B is the A-A line cutaway view along Fig. 2 A;
Fig. 3 A is the substrate front view of the uncoated glutinous brilliant glue still of the utility model one preferred embodiment;
Fig. 3 B is the B-B line cutaway view along Fig. 3 A;
Fig. 4 is the substrate front view that is coated with glutinous brilliant glue of the utility model one preferred embodiment;
Fig. 5 A is the glutinous brilliant substrate front view of finishing of the utility model one preferred embodiment;
Fig. 5 B is the C-C line cutaway view along Fig. 5 A.
[main element symbol description]
Substrate 91 golden finger zones 911,912,913
Golden finger 914 insulation enamelled coatings 92
Glutinous brilliant glue 93 chips 94
Substrate 11 golden finger zones 111,112,113
Golden finger 111a, 112a, 113a crystal bonding area territory 114
Circuit pattern 115 insulation enamelled coatings 12
Glutinous brilliant glue 13 chips 14
The long D1 of side overflows sizing material length overall D2
Embodiment
With reference to figure 3A and Fig. 3 B.The formation of semiconductor package of the present utility model is described below successively.At first, get a substrate of making 11, its end face defines an a plurality of golden fingers zone 111~113 and a crystal bonding area territory 114, and crystal bonding area territory 114 is meant predetermined zone of placing chip (being plotted in Fig. 5 A), and it is slightly larger than the area of chip own.Include at least one golden finger 111a in each golden finger zone 111,112,113,112a, 113a, and crystal bonding area territory 114 also includes an exposed circuit pattern 115.In the present embodiment, golden finger zone 111,112,113 is distributed in periphery, crystal bonding area territory 114 (and chip).
Then form an insulation enamelled coating 12 in the mode of avoiding a plurality of golden fingers zone 111~113 and crystal bonding area territory 114 at substrate 11 end faces, just substrate 11 end faces are external naked states except a plurality of golden fingers zone 111~113 and crystal bonding area territory 114, and remainder is insulated enamelled coating 12 and covers.
Then a glutinous brilliant glue 13 is uniformly coated in the exposed crystal bonding area territory 114, as shown in Figure 4.The special insulating cement that uses of this example is as glutinous brilliant glue 13.Again chip 14 is positioned at last on the glutinous brilliant glue 13 and makes chip 14 suitably be cemented at substrate 11, shown in Fig. 5 A and 5B.
Because the insulation enamelled coating 12 arround crystal bonding area territory 114 has a thickness, itself and crystal bonding area territory 114 are configured to the aspect of a groove jointly.When chip 14 is placed, even glutinous brilliant glue 13 can be to outdiffusion, also because of being limited to not to be diffused into contiguous golden finger zone 111~113 in the above-mentioned groove.So such semiconductor package does not have golden finger 111a, 112a, 113a overflow because of glutinous brilliant glue 13 situation of pollution take place.
Also, circuit pattern 115 and 14 direct short-circuits of chip exposed in the crystal bonding area territory 114 have been avoided because used glutinous brilliant glue 13 between chip 14 and substrate 91.But in other embodiments, used substrate can be printed circuit board (PCB) (Printed circuit board; PCB), ceramic wiring board, circuit film etc. as chip carrier and with electrically conduct jointly, it can be single or multiple lift, and there is no exposed circuit pattern in its crystal bonding area territory, therefore glutinous brilliant glue is not limited to use insulating cement.Glutinous brilliant glue material for example is that glue etc. is solidified on epoxy glue, B rank.
The foregoing description is only given an example for convenience of description, and the interest field that the utility model is advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.

Claims (4)

1. semiconductor package is characterized in that comprising:
One substrate, its end face define an at least one golden finger zone and a crystal bonding area territory that separates;
One insulation enamelled coating is formed at other zone of this substrate top surface beyond this at least one golden finger zone and this crystal bonding area territory;
One glutinous brilliant glue is coated within this crystal bonding area territory; And
One chip is attached on this glutinous brilliant glue.
2. semiconductor package as claimed in claim 1 is characterized in that, this at least one golden finger zone is positioned at this chip periphery.
3. semiconductor package as claimed in claim 1 is characterized in that, this substrate is a printed circuit board (PCB).
4. semiconductor package as claimed in claim 1 is characterized in that, this glutinous brilliant glue is an insulating cement.
CN201120102151XU 2011-04-08 2011-04-08 Semiconductor-packaging structure Expired - Fee Related CN202025733U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201120102151XU CN202025733U (en) 2011-04-08 2011-04-08 Semiconductor-packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201120102151XU CN202025733U (en) 2011-04-08 2011-04-08 Semiconductor-packaging structure

Publications (1)

Publication Number Publication Date
CN202025733U true CN202025733U (en) 2011-11-02

Family

ID=44850675

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201120102151XU Expired - Fee Related CN202025733U (en) 2011-04-08 2011-04-08 Semiconductor-packaging structure

Country Status (1)

Country Link
CN (1) CN202025733U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681499A (en) * 2013-11-29 2015-06-03 矽品精密工业股份有限公司 Package stack structure and method for fabricating the same
CN111769082A (en) * 2020-07-06 2020-10-13 瑞声声学科技(深圳)有限公司 ASIC chip and manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104681499A (en) * 2013-11-29 2015-06-03 矽品精密工业股份有限公司 Package stack structure and method for fabricating the same
CN111769082A (en) * 2020-07-06 2020-10-13 瑞声声学科技(深圳)有限公司 ASIC chip and manufacturing method
CN111769082B (en) * 2020-07-06 2022-07-01 瑞声声学科技(深圳)有限公司 ASIC chip and manufacturing method

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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20111102

Termination date: 20160408

CF01 Termination of patent right due to non-payment of annual fee