CN201966206U

CN201966206U - Twenty-row lead frame

Info

Publication number: CN201966206U
Application number: CN2011201013602U
Authority: CN
Inventors: 罗天秀
Original assignee: Chengdu Advanced Power Semiconductor Co Ltd
Current assignee: Chengdu Advanced Power Semiconductor Co Ltd
Priority date: 2011-04-08
Filing date: 2011-04-08
Publication date: 2011-09-07
Anticipated expiration: 2021-04-08

Abstract

The utility model discloses a twenty-row lead frame and is characterized in that twenty rows of transistors are arranged on the lead frame from top down at intervals, and each row comprises 56 transistors which are located in the same horizontal line of the lead frame at intervals. The lead frame increases frame density, improves equipment efficiency by 58% and molding efficiency by 5 times, reduces frame cost by 40% and compound cost by 30%, increases frame utilization rate by 41.05% and reduces compound quantity by 32.4%.

Description

20 row lead frame framves

Technical field

The utility model relates to a kind of lead frame, particularly relates to a kind of 20 row lead frame framves.

Background technology

Present lead frame product, / 216 each bars are arranged on the market 6 as shown in Figure 1, and this lead frame has 6 rows, and 36 transistors are arranged on every row, this lead frame length is 179.6mm, width is 31.5mm, and this product density is low, causes production efficiency low, the production cost height, in addition, the product of present poor efficiency, the wasting of resources that it consumed is big.Growth along with the market consumption, the present equipment and the design productivity of product can not satisfy market demand, need to improve the effective rate of utilization of product, along with the raising of production cost and labour costs, be faced with price pressure, need reduce production costs by technique improvement.

The utility model content

Goal of the invention of the present utility model is: at the problem of above-mentioned existence, provide the 20 row lead frame framves that a kind of density is big, cost is low.

In order to achieve the above object, the utility model adopts following technical scheme: a kind of 20 row lead frame framves, described framework has been spaced 20 row's transistors from top to bottom, the every row of described 20 row's transistors has 56 transistors, and 56 transistors on described every row are located at interval on the same horizontal line of framework.

Described lengths of frame is 252 ± 0.1mm, and width is 73 ± 0.04mm.

Lead frame in the utility model is not changing under the prerequisite of conventional lead frame length and width basically, bring up to 20 rows/1120 each bar by traditional/216 each bars of 6 rows, like this, increased the density of product, and then enhance productivity, reduced cost;

In sum, owing to adopted technique scheme, the beneficial effects of the utility model are:

1, increases framework density, improve device efficiency, reduce cost;

2, enhance productivity, the device efficiency .Molding of leading portion raising 58% improves 4 times efficient;

3, cost reduces, and the framework cost reduces by 40%, and the Compound cost reduces by 30%;

4, improve resource utilization, the framework utilance improves 41.05%, and the Compound consumption reduces by 32.4%.

Description of drawings

Fig. 1 is 6 traditional row lead frame framves;

Fig. 2 is a structural representation of the present utility model.

Embodiment

Below in conjunction with accompanying drawing, the utility model is done detailed explanation.

In order to make the purpose of this utility model, technical scheme and advantage clearer,, the utility model is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.

As shown in Figure 2, a kind of 20 row lead frame framves, described framework have been spaced 20 row's transistors from top to bottom, and the every row of described 20 row's transistors has 56 transistors, and 56 transistors on described every row are located at interval on the same horizontal line of framework.Described lengths of frame is 252 ± 0.1mm, and width is 73 ± 0.04mm.

When the utility model density improved, leading portion need prevent the framework oxidation and guarantee soldering reliability, and remove unnecessary waste material on request in the operation of back.

The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.

Claims

1. row lead frame frame is characterized in that: described framework has been spaced 20 row's transistors from top to bottom, and the every row of described 20 row's transistors has 56 transistors, and 56 transistors on described every row are located at interval on the same horizontal line of framework.

2. 20 row lead frame framves according to claim 1 is characterized in that: described lengths of frame is 252 ± 0.1mm, and width is 73 ± 0.04mm.