CN201937744U - Signal decoder and television - Google Patents

Signal decoder and television Download PDF

Info

Publication number
CN201937744U
CN201937744U CN2011200158407U CN201120015840U CN201937744U CN 201937744 U CN201937744 U CN 201937744U CN 2011200158407 U CN2011200158407 U CN 2011200158407U CN 201120015840 U CN201120015840 U CN 201120015840U CN 201937744 U CN201937744 U CN 201937744U
Authority
CN
China
Prior art keywords
signal
digital image
image decoding
tuner
decoding apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2011200158407U
Other languages
Chinese (zh)
Inventor
唐顺忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qingdao Hisense Electronics Co Ltd
Original Assignee
Qingdao Hisense Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qingdao Hisense Electronics Co Ltd filed Critical Qingdao Hisense Electronics Co Ltd
Priority to CN2011200158407U priority Critical patent/CN201937744U/en
Application granted granted Critical
Publication of CN201937744U publication Critical patent/CN201937744U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Circuits Of Receivers In General (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)

Abstract

The utility model provides a signal decoder and a television, wherein the signal decoder comprises a high-frequency head and a digital image decoding chip, wherein the high-frequency head comprises a radio frequency signal receiving module and is used for receiving radio frequency signals, and the digital image decoding chip is connected with the high frequency head and comprises a demodulation and decoding module, wherein the demodulation and decoding module is used for demodulating and decoding the radio frequency signals. Compared with the prior art, the signal decoder has the beneficial effects that the receiving, the demodulation and the decoding of analog signals and signals in various digital systems are supported through the single high-frequency head and the single chip.

Description

Signal decoding apparatus and television set
Technical field
The utility model relates to field of television, particularly, relates to a kind of signal decoding apparatus and television set.
Background technology
At present, along with the quickening of various countries' digital broadcast television program process, develop rapidly has been obtained in Digital Television market.Actual conditions for country variant consider that its digital television standard also is not quite similar.Main standards comprises DVB-T in the world, DVB-C, DVB-S and ATSC etc.For example European Region mainly adopts DVB-T, DVB-C.Therefore the multi-modulation scheme demand of Digital Television should be satisfied in Digital Television market, simultaneously, considers actual conditions, and analog signal is also being used in some areas, also should consider the problem that analog signal exists when satisfying Digital Television multi-modulation scheme demand.
In the prior art, do not occur as yet for the television set of supporting analog signal and multi-modulation scheme digital signal simultaneously.
The utility model content
Main purpose of the present utility model provides a kind of signal decoding apparatus and television set, can not support the problem of analog signal and multi-modulation scheme digital signal simultaneously in order to solve prior art.
In order to realize above-mentioned purpose of the present utility model, according to an aspect of the present utility model, provide a kind of signal decoding apparatus, by the following technical solutions:
A kind of signal decoding apparatus comprises: tuner, comprise the radiofrequency signal receiver module, and be used for received RF signal; And the digital image decoding chip, be connected with described tuner, comprise demodulation sign indicating number module, wherein, described demodulation sign indicating number module is used for described radiofrequency signal is carried out the demodulation sign indicating number.
Further, described radiofrequency signal receiver module is connected in described demodulation sign indicating number module.
Further, described tuner is for supporting the tuner of multiple standard.
Further, described multiple standard comprises DVB-T and DVB-C standard.
Further, described tuner comprises: the Wideband Intermediate Frequency output port, be connected in described digital image decoding chip, and be used for analog signal is transported to described digital image decoding chip.
Further, described tuner also comprises: the narrowband intermediate frequency output port, be connected in described digital image decoding chip, and be used for digital signal is transported to described digital image decoding chip.
Further, described signal decoding apparatus also comprises: the Flash memory, be connected with described digital image decoding chip, and be used to store the log-on data information of described digital image decoding chip.
Further, described signal decoding apparatus also comprises: power amplifier module, described power amplifier module is connected with described demodulation sign indicating number module.
According to another aspect of the present utility model, a kind of television set is provided, comprise foregoing signal decoding apparatus.
Compared with prior art, the beneficial effects of the utility model are: adopt the digital image decoding chip, join the system that tuner, power amplifier design form outward, realize DVB-T and DVB-C digital radio signal and analog radio-frequency signal receiving demodulation and decoding by this Circuits System.Realized that television set supports analog signal to receive by single tuner and single-chip and the problem of the digital signal reception of multiple standard simultaneously.
Description of drawings
The accompanying drawing that constitutes the application's a part is used to provide further understanding of the present utility model, and illustrative examples of the present utility model and explanation thereof are used to explain the utility model, do not constitute improper qualification of the present utility model.In the accompanying drawings:
Fig. 1 is the signal decoding apparatus primary structure figure according to the utility model embodiment;
Fig. 2 is the periphery design figure according to the signal decoding apparatus of the utility model embodiment.
In the drawings, tuner-102, digital image decoding chip-104, power amplifier module-106, FLASH memory-108, radiofrequency signal receiver module-1021, Wideband Intermediate Frequency output port-1023, narrowband intermediate frequency output port-1025.
Embodiment
Need to prove that under the situation of not conflicting, embodiment and the feature among the embodiment among the application can make up mutually.Describe the utility model below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
Fig. 1 is the signal decoding apparatus primary structure figure according to the utility model embodiment, referring to shown in Figure 1, signal decoding apparatus comprises: tuner 102 and digital image decoding chip 104, tuner 102 is connected with digital image decoding chip 104, wherein, tuner 102 comprises radiofrequency signal receiver module 1021, is used for received RF signal, and radiofrequency signal comprises digital radio signal and analog radio-frequency signal; Wherein, digital image decoding chip 104 comprises demodulation sign indicating number module 1041, and demodulation sign indicating number module 1041 is connected with the radiofrequency signal receiver module 1021 of tuner 102.
Preferably, the tuner 102 of this signal decoding apparatus is for supporting the tuner 102 of multiple standard, have Wideband Intermediate Frequency output port 1023 and narrowband intermediate frequency output port 1025, wherein Wideband Intermediate Frequency output port 1023 is connected in digital image decoding chip 104, the 1041 pairs of analog radio-frequency signals of demodulation sign indicating number module that are used for analog radio-frequency signal is transported to digital image decoding chip 104 carry out demodulation, narrowband intermediate frequency output port 1025 is connected in digital image decoding chip 104, and the 1041 pairs of digital radio signals of demodulation sign indicating number module that are used for digital radio signal is transported to digital image decoding chip 104 are decoded.
Preferably, the tuner 102 of this signal decoding apparatus is for supporting the tuner of multi-modulation scheme, and support comprises the digital signal of the multiple standard of DVB-T and DVB-C.
Preferably, signal decoding apparatus also comprises: Flash memory 108, be connected with digital image decoding chip 104, and be used to store the log-on data information of digital image decoding chip 104.Preferably, the Flash that Flash memory 108 adopts 64M and digital image decoding chip walk abreast addressing of address and data communication, solution OSD switching and switching channel and the slow problem of channel.Carry out the startup of Boot load bearing system and the storage of partial data information by Flash.Digital demodulator demodulator comes and the digital image decoding chip communication by the I2C bus, realizes reading and controlling of digital image decoding chip logarithm type matrix quasi-solution adjusting information.
Preferably, signal decoding apparatus also comprises: power amplifier module 106, power amplifier module 106 is connected with demodulation sign indicating number module 1041.The signal decoding apparatus of present embodiment specifically comprises tuner 102 and digital image decoding chip 104, tuner 102 is connected with digital image decoding chip 104, wherein, tuner 102 comprises radiofrequency signal receiver module 1021, be used for received RF signal, and radiofrequency signal comprises digital radio signal and analog radio-frequency signal; Wherein, digital image decoding chip 104 comprises demodulation sign indicating number module 1041, and demodulation sign indicating number module 1041 is connected with the radiofrequency signal receiver module 1021 of tuner 102.
Preferably, this signal decoding module is supported global Peripheral Interface, has very high versatility.
Preferably, the Peripheral Interface of this signal decoding module comprises: multimedia interface HDMI is used for external multimedia facility; USB interface can be used to connect peripheral hardware storage series; Aberration input interface SAW supports the aberration input; And signaling interface VGA, component signal interface COMP, video interface AV, Peripheral Interface SCART, general-purpose interface COMMON INTERFACE, earphone and output interface SPDIF.
Particularly, referring to shown in Figure 2, Fig. 2 is the periphery design figure according to the signal decoding apparatus of the utility model embodiment, this module is to be core with digital image decoding chip MSD308PX, join the system that tuner FH2610, D-class power amplifier TAS5707 design outward, realize DVB-T and DVB-C digital radio signal and analog radio-frequency signal receiving demodulation and decoding by this Circuits System design.
As shown in Figure 2, the outer periphery of this signal decoding apparatus is used for external multimedia facility in respect of multimedia interface HDMI; USB interface can be used to connect peripheral hardware storage series; Aberration input interface SAW supports the aberration input; And signaling interface VGA, component signal interface COMP, video interface AV, Peripheral Interface SCART, general-purpose interface COMMON INTERFACE, earphone and output interface SPDIF.
Preferably, the signal decoding apparatus periphery design also comprises internal memory DDR and dual access memory EEP, this digital image decoding chip adopts clock rate and the DDR of 800MHz to carry out the picture frame caching process, with problems such as technology solution flating such as the interleave algorithm of realizing H.264 decoding and 3D.In this embodiment, this digital image decoding chip has also designed the Flash of 64M and digital image decoding chip walk abreast addressing of address and data communication, solves OSD switching and switching channel and the slow problem of channel.Carry out the startup of Boot load bearing system and the storage of partial data information by Flash.
Signal flow mainly is: digital radio signal and analog radio-frequency signal, and after the reception of the tuner FH2610 on the mainboard, analog radio-frequency signal is shown to enter the demodulation sign indicating number that the digital image decoding chip carries out analog radio-frequency signal behind the trap through sound; Digital medium-frequency signal is exported to the digital image decoding chip and is decoded.The demodulation work of its DVB-T and DVB-C is also mainly carried out in digital image decoding chip the inside.Behind the tuner received television signal, analog signal is carried out analog if signal to the digital image decoding chip and is separated the decoding of mediation video signal by Broadband IF (Wideband Intermediate Frequency) output; Digital signal is carried out demodulation by Narrowband IF (narrowband intermediate frequency) output to the digital image decoding chip.
In addition, this digital image decoding chip is also supported component signal (Y PB PR), VGA signal, the input of aberration (S) signal.This digital image decoding chip adopts clock rate and the DDR of 800MHz to carry out the picture frame caching process, with problems such as technology solution flating such as the interleave algorithm of realizing H.264 decoding and 3D.Design the Flash of 64M and digital image decoding chip walk abreast addressing of address and data communication, solved OSD switching and switching channel and the slow problem of channel.Carry out the startup of Boot load bearing system and the storage of partial data information by Flash.Numeral demodulator comes and the digital image decoding chip communication by the I2C bus, realizes reading and controlling of digital image decoding chip logarithm type matrix quasi-solution adjusting information.
Preferably, this signal decoding apparatus has adopted the management of low power consumption standby power supply, and this design reduces the stand-by power consumption of module, realizes international low energy consumption standard-required.
This design mainly contains two parts and distinguishes with design in the past: a part is the brand-new single pcb board system design of MSD308PX scheme, and adopting horizontal terminal is ultra-thin LED machine specialized designs, supports global TV Peripheral Interface; Another part is that tuner FH2610 receives DVB-T and DVB-C digital signal, puts in digital medium-frequency signal and the digital image decoding chip MSD308PX inside and demodulator cooperates the demodulation of carrying out anolog TV signals.
In addition, this system design scheme is considered General design, supports ultra-thin LED more than 40 cun, by having considered compatibility on its size and the circuit design, reduces cost and improves processing technology by single board design.This can be described as a very big progress in the teaching machine design.Teaching machine system in the past, because the immature poor compatibility that causes is gone up in its complexity and design, performance and processing technology are poor, and the cost height, thereby influence popularizing of Digital Television.
Therefore, as can be seen, signal decoding apparatus that the utility model provides adopts the digital image decoding chip, joins the system that tuner, power amplifier design form outward, realizes DVB-T and DVB-C digital radio signal and analog radio-frequency signal receiving demodulation and decoding by this Circuits System.Realized that television set supports analog signal to receive by single tuner and single-chip and the problem of the digital signal reception of multiple standard simultaneously.
According to another one of the present utility model aspect, a kind of television set is provided, comprise aforesaid signal decoding apparatus, and signal decoding apparatus is as the core apparatus of television set.
Preferably, this television set is realized DVB-T and DVB-C digital radio signal and analog radio-frequency signal receiving demodulation and decoding by above-mentioned signal decoding apparatus.Concrete, this signal decoding module mainly comprises: tuner 102 and digital image decoding chip 104, tuner 102 is connected with digital image decoding chip 104, wherein, tuner 102 comprises radiofrequency signal receiver module 1021, be used for received RF signal, and radiofrequency signal comprises digital radio signal and analog radio-frequency signal; Wherein, digital image decoding chip 104 comprises demodulation sign indicating number module 1041, and demodulation sign indicating number module 1041 is connected with the radiofrequency signal receiver module 1021 of tuner 102.Preferably, the tuner 102 of this signal decoding apparatus is for supporting the tuner 102 of multiple standard, have Wideband Intermediate Frequency output port 1023 and narrowband intermediate frequency output port 1025, wherein Wideband Intermediate Frequency output port 1023 is connected in digital image decoding chip 104, the 1041 pairs of analog radio-frequency signals of demodulation sign indicating number module that are used for analog radio-frequency signal is transported to digital image decoding chip 104 carry out demodulation, narrowband intermediate frequency output port 1025 is connected in digital image decoding chip 104, and the 1041 pairs of digital radio signals of demodulation sign indicating number module that are used for digital radio signal is transported to digital image decoding chip 104 are decoded.Preferably, the tuner 102 of this signal decoding apparatus is for supporting the tuner of multi-modulation scheme, and support comprises the digital signal of the multiple standard of DVB-T and DVB-C.
Preferably, the tuner of the signal decoding apparatus of this television set adopts FH2610, digital radio signal and analog radio-frequency signal, after the reception of the tuner FH2610 on the mainboard, analog radio-frequency signal is shown to enter the demodulation sign indicating number that the digital image decoding chip carries out analog radio-frequency signal behind the trap through sound; Digital medium-frequency signal is exported to the digital image decoding chip and is decoded.The demodulation work of its DVB-T and DVB-C is also mainly carried out in digital image decoding chip the inside.Behind the tuner received television signal, analog signal is carried out analog if signal to the digital image decoding chip and is separated the decoding of mediation video signal by Broadband IF (Wideband Intermediate Frequency) output; Digital signal is carried out demodulation by Narrowband IF (narrowband intermediate frequency) output to the digital image decoding chip.
Preferably, it is ultra-thin LED machine specialized designs that this television set adopts horizontal terminal, supports global TV Peripheral Interface; Concrete comprises: multimedia interface HDMI, support external multimedia unit; USB interface can be used for external storage series; And aberration input interface SAW, signaling interface VGA, component signal interface COMP, video interface AV, Peripheral Interface SCART, general-purpose interface COMMON INTERFACE, earphone and output interface SPDIF.
Preferably, this television set also comprises internal memory DDR and dual access memory EEP, can adopt the clock rate of 800MHz and DDR to carry out the picture frame caching process, solves problems such as flating with technology such as the interleave algorithm of realizing H.264 decoding and 3D.In this embodiment, this television set has also designed the Flash of 64M and digital image decoding chip walk abreast addressing of address and data communication, solves OSD switching and switching channel and the slow problem of channel.Carry out the startup of Boot load bearing system and the storage of partial data information by Flash.
Preferably, this system design scheme of this television set is considered General design, supports ultra-thin LED more than 40 cun, by having considered compatibility on its size and the circuit design, reduces cost and improves processing technology by single board design.This can be described as a very big progress in the teaching machine design.Teaching machine system in the past, because the immature poor compatibility that causes is gone up in its complexity and design, performance and processing technology are poor, and the cost height, thereby influence popularizing of Digital Television.
Preferably, this television set has adopted the management of low power consumption standby power supply, and this design reduces the stand-by power consumption of module, realizes international low energy consumption standard-required.
Preferably, this television set adopts single pcb board system design, and adopting horizontal terminal is ultra-thin LED machine specialized designs, supports global TV Peripheral Interface; Well embodied the thinking of saving cost.
Therefore, as can be seen, the television set that the utility model provides, a part adopts brand-new MSD308PX master chip design, another part is that tuner FH2610 receives, and puts in digital medium-frequency signal and the digital image decoding chip MSD308PX inside and demodulator cooperates the demodulation of carrying out anolog TV signals.Not only support DVB-T and DVB-C digital signal, and support analog signal, and support global television interface, realized that television set supports analog signal to receive by single tuner and single-chip and the problem of the digital signal reception of multiple standard simultaneously.
Be preferred embodiment of the present utility model only below, be not limited to the utility model, for a person skilled in the art, the utility model can have various changes and variation.All within spirit of the present utility model and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.

Claims (9)

1. a signal decoding apparatus is characterized in that, comprising:
Tuner comprises the radiofrequency signal receiver module, is used for received RF signal; And
The digital image decoding chip is connected with described tuner, comprises demodulation sign indicating number module, and wherein, described demodulation sign indicating number module is used for described radiofrequency signal is carried out the demodulation sign indicating number.
2. signal decoding apparatus according to claim 1 is characterized in that, described radiofrequency signal receiver module is connected in described demodulation sign indicating number module.
3. signal decoding apparatus according to claim 1 is characterized in that, described tuner is for supporting the tuner of multiple standard.
4. signal decoding apparatus according to claim 3 is characterized in that, described multiple standard comprises DVB-T standard and DVB-C standard.
5. signal decoding apparatus according to claim 1 is characterized in that, described tuner comprises:
The Wideband Intermediate Frequency output port is connected in described digital image decoding chip, is used for analog signal is transported to described digital image decoding chip.
6. signal decoding apparatus according to claim 1 is characterized in that, described tuner also comprises:
The narrowband intermediate frequency output port is connected in described digital image decoding chip, is used for digital signal is transported to described digital image decoding chip.
7. signal decoding apparatus according to claim 1 is characterized in that, also comprises:
The Flash memory is connected with described digital image decoding chip, is used to store the log-on data information of described digital image decoding chip.
8. signal decoding apparatus according to claim 1 is characterized in that, also comprises:
Power amplifier module, described power amplifier module is connected with described demodulation sign indicating number module.
9. a television set is characterized in that, comprises each described signal decoding apparatus in the claim 1 to 8.
CN2011200158407U 2011-01-18 2011-01-18 Signal decoder and television Expired - Lifetime CN201937744U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011200158407U CN201937744U (en) 2011-01-18 2011-01-18 Signal decoder and television

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011200158407U CN201937744U (en) 2011-01-18 2011-01-18 Signal decoder and television

Publications (1)

Publication Number Publication Date
CN201937744U true CN201937744U (en) 2011-08-17

Family

ID=44449247

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011200158407U Expired - Lifetime CN201937744U (en) 2011-01-18 2011-01-18 Signal decoder and television

Country Status (1)

Country Link
CN (1) CN201937744U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017128622A1 (en) * 2016-01-30 2017-08-03 乐视控股(北京)有限公司 Digital television and signal processing apparatus thereof
CN108282628A (en) * 2018-02-09 2018-07-13 深圳创维-Rgb电子有限公司 TV motherboard, TV motherboard component and DTV

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017128622A1 (en) * 2016-01-30 2017-08-03 乐视控股(北京)有限公司 Digital television and signal processing apparatus thereof
CN108282628A (en) * 2018-02-09 2018-07-13 深圳创维-Rgb电子有限公司 TV motherboard, TV motherboard component and DTV

Similar Documents

Publication Publication Date Title
CN201674568U (en) Multifunctional set-top box
CN204206332U (en) A kind of device that car machine image is exported by Wi-Fi
CN201937744U (en) Signal decoder and television
CN103686011A (en) Television signal receiving module and method
CN204206374U (en) A kind of simple two-way signal receives descrambling kilocalorie receiver
CN204598192U (en) A kind of novel information secure digital telstar receiver
CN201854360U (en) Digital television receiving device
CN204258994U (en) A kind of four frequency Signal reception descrambling kilocalorie receivers
CN201450547U (en) Digital television receiving device
CN201541330U (en) 3D stereoscopic digital television
CN201957185U (en) Television integrated machine with Cable Modem function
CN203012241U (en) Video glasses provided with function of watching mobile digital TV
CN203057372U (en) Digital television receiving terminal
CN202738040U (en) Network television set-top box
CN201266976Y (en) Portable multimedia player with digital television function
CN205195888U (en) Miniaturized digital television receiving module that removes of high integrated
CN201444668U (en) Decoding circuit and television set with same
CN201156780Y (en) DVB-T digital television decoding module
CN204377023U (en) There is the ground of USB interface, cable digital TV tuner
CN104219554A (en) Digital TV receiver and digital TV playing method
CN204180213U (en) A kind of D-LED television set supporting DVB-T2
CN201754602U (en) Television module for computer
CN105812862A (en) Highly integrated miniaturized mobile digital television receiving module
CN206611533U (en) A kind of satellite set top box protected with antenna short circuit
CN202127420U (en) Double demodulation circuit and set-top box with same

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20110817