CN201156780Y - DVB-T digital television decoding module - Google Patents
DVB-T digital television decoding module Download PDFInfo
- Publication number
- CN201156780Y CN201156780Y CNU2007201582895U CN200720158289U CN201156780Y CN 201156780 Y CN201156780 Y CN 201156780Y CN U2007201582895 U CNU2007201582895 U CN U2007201582895U CN 200720158289 U CN200720158289 U CN 200720158289U CN 201156780 Y CN201156780 Y CN 201156780Y
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- signal demodulator
- decoding module
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Abstract
The utility model relates to a DVB-T digital television decoding module, which solves the problems of poor integration, performance, compatibility and processing techniques in the majority of the existing DVB-T digital television decoding module. The technical proposal comprises a digital image decoding chip, a high-frequency head, an analog signal demodulator and a digital signal demodulator; wherein, the high-frequency head is connected with the digital image decoding chip respectively through the analog signal demodulator and the digital signal demodulator. The design of the circuit system realizes the reception and demodulation of the DVB-T digital signals and the analog digital signals. The digital image decoding chip adopts a plurality of digital techniques to process the image signals and to decode the digital signals, and supports the HDMI decoding. The costs are reduced; and the processing technology is improved.
Description
Technical field
The utility model relates to TV technology, is specifically related to a kind of DVB-T digital television decoder module.
Background technology
Digital Television is with respect to traditional simulated television, it is good to have view reception effect, the image definition height, the audio quality height, antijamming capability is strong, the efficiency of transmission height, advantages such as compatible existing simulated television, therefore, countries in the world are all in the process of accelerating the digital broadcast television program, develop rapidly had been obtained in Digital Television market in recent years, support that the tv product of DVB-T is also more and more, yet present most of DVB-T digital television decoding module integrated level was poor, performance is bad, design is complicated and immature, and compatibility and processing technology are poor, thereby influences popularizing of teaching machine.
The utility model content
The utility model is poor at the integrated level that present DVB-T digital television decoding module exists, and the technical problem that performance is bad provides a kind of integrated level good, compatible high, low, the high performance DVB-T digital television of cost decoder module.
The utility model is to realize goal of the invention by following technological means:
A kind of DVB-T digital television decoding module, it is characterized in that: comprise digital image decoding chip, tuner, analog signal demodulator and digital signal demodulator, wherein, described tuner is connected with described digital image decoding chip by described analog signal demodulator, described digital signal demodulator respectively.
Preferably, the I2C bus of described tuner is connected with described digital image decoding chip by described digital signal demodulator, described analog signal demodulator.
Preferably, described analog signal demodulator is connected with described digital image decoding chip on same I2C bus with described digital signal demodulator.
Preferably, described picture decoding chip is the HiDTVPRO_FX/CX chip based on the MIPS framework.
Preferably, described picture decoding chip HiDTVPRO_FX/CX adopts 4 layers of single PCB board design.
Preferably, described digital image decoding chip is connected with MCU, DDR, Flash respectively.
Preferably, described tuner is digital-analog integrated tuner TD1318AF.
Preferably, described digital signal demodulator is digital demodulator CE6353.
Preferably, described analog signal demodulator is put TDA9886TS in being.
Preferably, described digital image decoding chip is connected AudioProcesser by the I2C bus with the I2S bus.
Compared with prior art, the utlity model has a lot of advantages,, realize that DVB-T digital signal and analog and digital signal receive demodulation process by the design of foregoing circuit system; Adopting multiple digital technology to carry out picture signal by the HiDTVPRO_FX/CX master chip handles and digital signal decoding, supports the HDMI decoding; Reduce stand-by power consumption by system MCU design; Improve the application of system by compatibility design; Reduce cost, improve processing technology by single board design.
Description of drawings
Fig. 1 is the digital image decoding chip HiDTVPRO_FX/CX and the peripheral circuit system framework schematic diagram thereof of preferred embodiment.
Fig. 2 is the signal flow graph of preferred embodiment.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is further described:
Figure 1 shows that based on MIPS framework digital image decoding chip HiDTVPRO_FX/CX, this chip is a master chip of the present utility model, the integrated MPEG-2 decoding of this chip monolithic, 3D COMB, the processing of 7 generation DCRE analog videos, analog video multiplex switch, PIP, POP, MIPS 250M CPU, Deinterlace and SCALER, 8/10bits LVDS output, HDMI2.0receiver, AC3/MPEG2/MP3/AAC decoder, OSD engine; Support ATSC/DVB/ISDB decoding and the decoding of full system type pictorial analog signal; Support 120Hz and 8bit-14bit LVDS output etc.Wherein, 7th DCRE possesses 1920 * 1080P De-interlacer; Technology such as the compensation of ME/MC moving image, digital flesh correction, SRC (Scan Rate Conversion) strengthen, the colored acutance reproduction of ACR, dynamic contrast further promote image quality greatly.In addition, this master chip is also supported component signal (Y PB PR), VGA signal, the input of aberration (S) signal.
Among the master chip HiDTVPRO_FX/CX and peripheral circuit thereof shown in Figure 1, the DDR of 300MHz 128MB is as the picture signal initial gain value, and the technology such as interleave algorithm and 3D that realize solve problems such as flating and oblique line sawtooth.This circuit design the Flash of 16M and master chip walk abreast addressing of address and data communication, solve OSD switching and switching channel and the slow problem of channel.Carry out Boot load by 4M Flash, carry the startup of this system and the storage of partial data information.MCU communicates by letter with master chip by the I2C bus, carries out the reception of standby start-up control, electrifying timing sequence control and remote keying signal, and this is designed to reduce the complete machine standby power, saves electric energy.The sound accompaniment part of this system also is in master chip by I2C bus slave, YPBPR, VGA, and after the audio signal CVBS of AV video channel is input to Audio Processer chip, carry out passage and switch, sound demodulation and audio are exported to audio power amplifier Audio AMP and earphone power amplifier Earphone AMP after handling.Switch switches to 1 road HDMI signal as 3 road HDMI signals to output to master chip and decode, and decoded I2S audio signal inputs to Audio Processer chip and handles.
Referring to Fig. 2, this digital image decoding module comprises master chip digital image decoding chip HiDTVPRO_FX/CX, tuner TD1318AF, in put TDA9886TS and digital demodulator CE6353, described tuner TD1318AF is respectively by described digital demodulator CE6353, putting TDA9886T in described is connected with described digital image decoding chip HiDTVPRO_FX/CX, wherein, described analog signal demodulator chip is not limited thereto, but in to put TDA9886TS be comparative maturity, its cost performance is fine, described tuner chip and described digital signal demodulator chip also are not limited thereto, but this two classes chip product is fewer at present.
The whole set of television circuit mainly adopts: the signal processing chip of the PBGA of Trident company encapsulation.Movement adopts 4 layers of PCB board design of row.Digital RF and analog radio-frequency signal mainly receive by the digital-analog integrated tuner TD1318AF on the mainboard, carry out the demodulation of analog intermediate frequency and digital medium-frequency signal respectively by TDA9886TS and CE6353.The signal processing chip of Trident company receives from the CVBS signal of TDA9886TS output, and handles from the laggard line number word image of MPEG-2 digital signal of CE6353 output.
Master chip HiDTVPRO_FX/CX realizes above-mentioned functions based on the Lunix system, and software designs from bottom to the user interface independent development.The flow process of each signal of the utility model mainly is: behind the digital-analog integrated tuner TD1318AF received television signal, analog signal by in put TDA9886TS RF_AGC control, analog signal is by Broadband IF (Wideband Intermediate Frequency) output, to in put TDA9886TS and be demodulated into the CVBS signal after, input master chip HiDTVPRO_FX/CX carries out video signal to be handled; Digital signal is controlled by the IF_AGC of digital demodulator CE6353, digital signal is by Narrowband IF (narrowband intermediate frequency) output, after carrying out demodulation to digital demodulator CE6353, output MPEG-2 digital signal is decoded to master chip HiDTVPRO_FX/CX.That is to say, this system adopt NXP company digital-analog integrated tuner TD1318AF and in put TDA9886TS and cooperate and carry out the demodulation of anolog TV signals.Digital demodulator CE6353 by digital-analog integrated tuner TD1318AF and intel company cooperates and separates the DVB-T digital signal.In addition, this system design scheme is considered General design, and LCD or PDP from 26 cun to 63 cun are by having considered compatibility on its size and the circuit design.
The utility model has realized that by adopting above-mentioned simple circuit design DVB-T digital signal and analog and digital signal receive demodulation process; Adopting multiple digital technology to carry out picture signal by the HiDTVPRO_FX/CX master chip handles and digital signal decoding, supports the HDMI decoding; Reduced stand-by power consumption, improved compatibility and processing technology, reduced cost, be easy to large-scale promotion and use.
Certainly; above-mentioned explanation is not to be to restriction of the present utility model; the utility model also not only is confined to above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art are made in essential scope of the present utility model also should belong to protection range of the present utility model.
Claims (10)
1. DVB-T digital television decoding module, it is characterized in that: comprise digital image decoding chip, tuner, analog signal demodulator and digital signal demodulator, wherein, described tuner is connected with described digital image decoding chip by described analog signal demodulator, described digital signal demodulator respectively.
2. DVB-T digital television decoding module according to claim 1 is characterized in that: the I2C bus of described tuner is connected with described digital image decoding chip by described digital signal demodulator, described analog signal demodulator.
3. DVB-T digital television decoding module according to claim 1 is characterized in that: described analog signal demodulator is connected with described digital image decoding chip on same I2C bus with described digital signal demodulator.
4. DVB-T digital television decoding module according to claim 1 is characterized in that: described picture decoding chip is the HiDTVPRO_FX/CX chip based on the MIPS framework.
5. DVB-T digital television decoding module according to claim 1 is characterized in that: described picture decoding chip HiDTVPRO_FX/CX adopts 4 layers of single PCB board design.
6. according to claim 1 or 4 or 5 described DVB-T digital television decoding module, it is characterized in that: described digital image decoding chip is connected with MCU, DDR, Flash respectively.
7. require 1 described DVB-T digital television decoding module according to getting profit, it is characterized in that: described tuner is digital-analog integrated tuner TD1318AF.
8. DVB-T digital television decoding module according to claim 1 is characterized in that: described digital signal demodulator is digital demodulator CE6353.
9. DVB-T digital television decoding module according to claim 1 is characterized in that: described analog signal demodulator is put TDA9886TS in being.
10. DVB-T digital television decoding module according to claim 1 is characterized in that: described digital image decoding chip is connected audio process by the I2C bus with the I2S bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201582895U CN201156780Y (en) | 2007-12-11 | 2007-12-11 | DVB-T digital television decoding module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007201582895U CN201156780Y (en) | 2007-12-11 | 2007-12-11 | DVB-T digital television decoding module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201156780Y true CN201156780Y (en) | 2008-11-26 |
Family
ID=40104556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2007201582895U Expired - Fee Related CN201156780Y (en) | 2007-12-11 | 2007-12-11 | DVB-T digital television decoding module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201156780Y (en) |
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2007
- 2007-12-11 CN CNU2007201582895U patent/CN201156780Y/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081126 Termination date: 20111211 |