CN201918086U - Teaching system - Google Patents

Teaching system Download PDF

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Publication number
CN201918086U
CN201918086U CN 201020611332 CN201020611332U CN201918086U CN 201918086 U CN201918086 U CN 201918086U CN 201020611332 CN201020611332 CN 201020611332 CN 201020611332 U CN201020611332 U CN 201020611332U CN 201918086 U CN201918086 U CN 201918086U
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China
Prior art keywords
fpga
tutoring system
plug socket
module
bus interface
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Expired - Fee Related
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CN 201020611332
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Chinese (zh)
Inventor
贺敬凯
王瑞春
王勇
湛邵斌
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Shenzhen Institute of Information Technology
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Shenzhen Institute of Information Technology
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Priority to CN 201020611332 priority Critical patent/CN201918086U/en
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Publication of CN201918086U publication Critical patent/CN201918086U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model relates to a teaching system which comprises a single chip microcomputer module, an FPGA (Field Programmable Gate Array) module, a bayonet socket used for plugging the single chip microcomputer module or the FPGA module, and an input device, an output device, an AD/DA conversion device and a bus interface that are connected with the bayonet socket. With application of the technical scheme, the teaching system can meet both the single chip microcomputer teaching need and FPGA teaching need. In addition, the teaching system is simple in hardware structure, low in price and easy to operate, can intuitively show the completed circuit design experiment program and facilitate the learning of beginners.

Description

A kind of tutoring system
Technical field
The utility model relates to control technology, more particularly, relates to a kind of tutoring system.
Background technology
FPGA (Field-Programmable Gate Array, field programmable gate array) is the product that further develops on the basis of programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome the limited shortcoming of original programming device gate circuit number again.In the FPGA tutoring system, the circuit design of being finished with hardware description language (Verilog or VHDL) through simple comprehensive and layout, is burned onto on the FPGA apace and tests usually.
Single-chip microcomputer is the specialized core course of electrical type specialty, and it is easy to learn relative FPGA.If can learn FPGA, then can further strengthen the heightened awareness of learner to single-chip microcomputer application and FPGA application by single-chip microcomputer.
But present tutoring system often has only a function, and the single chip computer teaching system can only satisfy the teaching needs of single-chip microcomputer, can not be used to learn FPGA.And traditional FPGA tutoring system can not satisfy the teaching needs of single-chip microcomputer usually, and the hardware configuration complexity, costs an arm and a leg.
The utility model content
The technical problems to be solved in the utility model is, the defective at the above-mentioned tutoring system function singleness of prior art provides a kind of tutoring system, and this tutoring system can satisfy the single chip computer teaching needs can satisfy FPGA teaching needs again.
The technical scheme that its technical matters that solves the utility model adopts is: construct a kind of tutoring system, comprise one-chip computer module, FPGA module, the plug socket of be used to peg graft one-chip computer module or FPGA module, the input equipment that is connected with described plug socket, output device, AD/DA conversion equipment and bus interface.
In tutoring system described in the utility model, described input equipment comprises matrix keyboard, the QWERTY keyboard interface that is connected with described plug socket respectively.
In tutoring system described in the utility model, described matrix keyboard is the 8*8 matrix keyboard.
In tutoring system described in the utility model, described output device comprises charactron, LED lamp, LCD interface, standard indicator interface, the loudspeaker that is connected with described plug socket respectively.
In tutoring system described in the utility model, described bus interface comprises network interface, serial port, the I that is connected with described plug socket respectively 2C bus interface, single bus interface, spi bus interface.
In tutoring system described in the utility model, described AD/DA conversion equipment comprises analog to digital conversion circuit and the D/A converting circuit that is connected with described plug socket respectively.
Implement the technical solution of the utility model, have following beneficial effect:
1. this tutoring system can satisfy the single chip computer teaching needs and can satisfy FPGA teaching needs again;
2. simple, the low price of hardware configuration, and operation easily can represent the circuit design experimental project of being finished intuitively, is convenient to beginner's study.
Description of drawings
The utility model is described in further detail below in conjunction with drawings and Examples, in the accompanying drawing:
Figure 1A is that the utility model tutoring system is as single chip computer teaching system embodiment one logical diagram;
Figure 1B is that the utility model tutoring system is as FPGA tutoring system embodiment one logical diagram;
Fig. 2 is the logical diagram of the utility model tutoring system embodiment two.
Embodiment
In conjunction with Figure 1A and Figure 1B, in the logical diagram of tutoring system embodiment one of the present utility model, this tutoring system comprises one-chip computer module 200, FPGA module 300, the plug socket 100 of be used to peg graft one-chip computer module 200 or FPGA module 300, the input equipment 400 that is connected with described plug socket, output device 500, bus interface 600 and AD/DA conversion equipment 700.In Figure 1A, one-chip computer module 200 connects input equipment 400, output device 500, bus interface 600 and AD/DA conversion equipment 700 by plug socket 100, and at this moment, this tutoring system is the single chip computer teaching system.In Figure 1B, FPGA module 300 connects input equipment 400, output device 500, bus interface 600 and AD/DA conversion equipment 700 by plug socket 100, and at this moment, this tutoring system is the FPGA tutoring system.
In the logical diagram of the tutoring system embodiment of the present utility model two shown in Fig. 2, this tutoring system comprises one-chip computer module (not shown), FPGA module (not shown), the plug socket 100 of be used to peg graft one-chip computer module or FPGA module, the input equipment 400 that is connected with described plug socket, output device 500, bus interface 600 and AD/DA conversion equipment 700.Wherein, input equipment 400 comprises matrix keyboard 401, the QWERTY keyboard interface 402 that is connected with plug socket 100 respectively, and preferably, matrix keyboard can be the 8*8 matrix keyboard.Output device 500 comprises charactron 501, LED lamp 502, LCD interface 503, standard indicator interface 504, the loudspeaker 505 that is connected with plug socket 100 respectively, for example, the quantity of charactron 501 can be 8, represents the result of experimental project with the demonstration of 8 charactrons.LED lamp 502 can be 8 LED running lamps, represents the result of experimental project with the light on and off of 8 LED running lamps.Bus interface 600 can comprise network interface 601, serial port 602, the I that is connected with plug socket 100 respectively 2C bus interface 603, single bus interface 604, spi bus interface 605.AD/DA conversion equipment 700 comprises analog to digital conversion circuit 701 and the D/A converting circuit 702 that is connected with plug socket 100 respectively.Should be noted that when this tutoring system is used as the single chip computer teaching system, one-chip computer module is inserted in the plug socket; When this tutoring system is used as the FPGA tutoring system, the FPGA module is inserted in the plug socket.
The experimental project that this tutoring system can be developed specifically comprises: running lamp project, charactron scan item, music playing project, digital stopwatch and digital clock project, coded lock project, data acquisition project, beverage Vending Machine project, I 2C device control project, SPI device control project, single wire bus device control project, serial port protocol project, network interface agreement project or the like.Based on the project of these peripheral hardwares, can in teaching, carry out the teaching of project formula; Simultaneously also high-caliber system design can be realized in one-chip computer module or in the FPGA module, as the platform of studying single-chip microcomputer or FPGA in depth.
The tutoring system that specifies this fusion single-chip microcomputer and FPGA with " running lamp project " and " music playing project " is how to realize teaching below, represents design concept with form more intuitively.
One, running lamp project:
Experiment purpose: by experiment, the experimenter is grasped use hardware description language or C voice to realize the technology and the method for simple I/O Application of Interface.
Performing step is divided into to be used chip microcontroller and uses FPGA to realize two kinds of methods.
Adopt the performing step of FPGA module:
(1) adopts hardware description language, the fixed system frequency in the hardware is carried out frequency division, obtain the frequency of 1Hz;
(2) adopt the behavior modeling, obtain the hardware logic that 1Hz changes a port high-low level state, the output of these hardware logics will be used to drive 8 LED running lamps, and this hardware logic will satisfy the specific requirement of running lamp project;
(3) with above-mentioned hardware logic, at specific FPGA and relevant hardware environment, carry out the pin locking, the hardware logic that so just will adopt hardware description language to write is changed the hardware for reality;
(4) because actual FPGA hardware pin is connected with 8 LED running lamps, turn round so promptly drive the mode that lamp sets according to logic after the FPGA work;
(5) in above-mentioned design, can also from multiple LED running lamp pattern, select by the 8*8 matrix keyboard.
Adopt the performing step of one-chip computer module:
(1) adopts the C language, adopt the method for software delay to carry out frequency division, obtain the frequency of 1Hz according to single-chip microcomputer work system frequency;
(2) use the single-chip microcomputer corresponding ports to drive 8 LED running lamps, use the C Programming with Pascal Language to realize, use the delay function of previous step in rapid simultaneously, make the driving LED running lamp satisfy the specific requirement of project;
(3) but above-mentioned software carried out compiling link generate the scale-of-two file in download;
(4) but above-mentioned scale-of-two file in download is written into single-chip microcomputer, then single-chip microcomputer turns round with regard to the mode of controlling lamp and setting according to logic;
(5) in above-mentioned design, can also from multiple LED running lamp pattern, select by the 8*8 matrix keyboard.
Experimental result: the experimenter can observe the light on and off of 8 LED running lamps intuitively with eyes.
Two, music playing project:
Experiment purpose: by experiment, the experimenter is grasped use hardware description language or C language to realize technology and method than complicated applications.
Performing step is divided into to be used chip microcontroller and uses FPGA to realize two kinds of methods.
Adopt the performing step of FPGA module:
(1) frequency of each tone at first definite music numerical notation;
(2) adopt hardware description language, the fixed system frequency in the hardware is carried out frequency division, obtain the frequency of each tone;
(3) adopt the behavior modeling, by the duration ratio of each tone of stipulating in the numbered musical notation, continue this frequency of output, this output will be used to drive loudspeaker;
(4) with above-mentioned hardware logic, at specific FPGA and relevant hardware environment, carry out the pin locking, the hardware logic that so just will adopt hardware description language to write is changed the hardware for reality;
(5) because actual FPGA hardware pin is connected with the loudspeaker lamp, play interesting to listen to music according to numbered musical notation so promptly drive loudspeaker behind the FPGA workpiece;
(6) in above-mentioned design, can also from multiple melody, select a head or many head to play by the 8*8 matrix keyboard.
Adopt the performing step of one-chip computer module:
(1) frequency of each tone at first definite music numerical notation;
(2) adopt the C language, use timer to carry out frequency division, obtain the frequency of each tone according to the system works frequency of single-chip microcomputer;
(3) adopt the C language to carry out program design, by the duration ratio of each tone of stipulating in the numbered musical notation, continue this frequency of output, this output will be used to drive loudspeaker;
(4) but above-mentioned c program compiling link is generated the scale-of-two file in download, be written into single-chip microcomputer then, single-chip microcomputer just drives loudspeaker according to the interesting to listen to music of numbered musical notation broadcast like this;
(5) in above-mentioned design, can also from multiple melody, select a head or many head to play by the 8*8 matrix keyboard.
Experimental result: the experimenter can enjoy the music of loudspeaker plays intuitively with ear.
The above is a preferred embodiment of the present utility model only, is not limited to the utility model, and for a person skilled in the art, the utility model can have various changes and variation.All within spirit of the present utility model and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present utility model.

Claims (6)

1. a tutoring system is characterized in that, comprises one-chip computer module, FPGA module, the plug socket of be used to peg graft one-chip computer module or FPGA module, the input equipment that is connected with described plug socket, output device, AD/DA conversion equipment and bus interface.
2. tutoring system according to claim 1 is characterized in that, described input equipment comprises matrix keyboard, the QWERTY keyboard interface that is connected with described plug socket respectively.
3. tutoring system according to claim 1 is characterized in that, described matrix keyboard is the 8*8 matrix keyboard.
4. tutoring system according to claim 1 is characterized in that, described output device comprises charactron, LED lamp, LCD interface, standard indicator interface, the loudspeaker that is connected with described plug socket respectively.
5. tutoring system according to claim 1 is characterized in that, described bus interface comprises network interface, serial port, the I that is connected with described plug socket respectively 2C bus interface, single bus interface, spi bus interface.
6. according to each described tutoring system of claim 1-5, it is characterized in that described AD/DA conversion equipment comprises analog to digital conversion circuit and the D/A converting circuit that is connected with described plug socket respectively.
CN 201020611332 2010-11-17 2010-11-17 Teaching system Expired - Fee Related CN201918086U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201020611332 CN201918086U (en) 2010-11-17 2010-11-17 Teaching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201020611332 CN201918086U (en) 2010-11-17 2010-11-17 Teaching system

Publications (1)

Publication Number Publication Date
CN201918086U true CN201918086U (en) 2011-08-03

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201020611332 Expired - Fee Related CN201918086U (en) 2010-11-17 2010-11-17 Teaching system

Country Status (1)

Country Link
CN (1) CN201918086U (en)

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C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110803

Termination date: 20111117