CN201904774U

CN201904774U - Single-ended high-voltage level conversion circuit for bridge-type drive circuit

Info

Publication number: CN201904774U
Application number: CN201020679042XU
Authority: CN
Inventors: 孙腾达
Original assignee: DAILY SILVER IMP MICROELECTRONICS Co Ltd
Current assignee: DAILY SILVER IMP MICROELECTRONICS Co Ltd
Priority date: 2010-12-24
Filing date: 2010-12-24
Publication date: 2011-07-20
Anticipated expiration: 2020-12-24

Abstract

The utility model discloses a single-ended high-voltage level conversion circuit for a bridge-type drive circuit, which comprises a first pulse generator, a DMOS (double diffusion metal-oxide-semiconductor) tube, a sampling resistor and a high-voltage decoding circuit, wherein the signal output end of the first pulse generator is connected with the grid electrode of the DMOS tube; the drain electrode of the DMOS tube is connected with the second end of the sampling resistor and the signal input end of the high-voltage decoding circuit; the first end of the sampling resistor and the power source end of the high-voltage decoding circuit are respectively connected with the power supply end of a high-voltage level; the grounded end of the high-voltage decoding circuit is connected with that of the high-voltage level; and the signal output end of the high-voltage decoding circuit serves as the output signal end of a high-voltage drive. The single-ended high-voltage level conversion circuit for the bridge-type drive circuit has the advantages that only one DMOS tube is used during the level conversion from a high-voltage level to a low-voltage level, so that more chip area can be saved and the chip cost is greatly reduced; and signals with the shortest pulse width are adopted to control the grid electrode of the DMOS tube, so that the high-voltage DMOS tube is conducted within the shortest time during the switch conversion, and the chip consumption is effectively reduced.

Description

A kind of single-ended high voltage level change-over circuit that is used for bridge drive circuit

Technical field

The utility model relates to the level shifting circuit in a kind of integrated circuit, especially relates to a kind of single-ended high voltage level change-over circuit that is used for bridge drive circuit.

Background technology

Control signal is when a certain operating voltage circuit part is transferred to another operating voltage circuit part, because therefore the difference of operating voltage need carry out level conversion to control signals transmitted in integrated circuit.When especially the operating voltage between two circuit differed greatly, the level conversion function of control signals transmitted was extremely important.

Fig. 1 has provided and has adopted conventional method low voltage level to be transformed into a typical circuit of high voltage level, it comprises pulse generator PG1, the one DMOS manages DM1, the 2nd DMOS manages DM2, first resistance R 1, second resistance R 2 and rest-set flip-flop RS1, pulse generator PG1 has first output and second output (signal of two outputs output is to have phase difference on two phase places but the identical signal of waveform), first output of pulse generator PG1 is connected with the grid of DMOS pipe DM1, the signal of first output output of pulse generator PG1 is as the reset signal of level shifting circuit, second output of pulse generator PG1 is connected with the grid of the 2nd DOMS pipe DM2, the signal of second output output of pulse generator PG1 is as the asserts signal of level shifting circuit, the drain electrode of the one DMOS pipe DM1 is connected with power end (600V) VB of 600V high voltage level by first resistance R 1, the drain electrode of the 2nd DMOS pipe DM2 is connected with the power end VB of 600V high voltage level by second resistance R 2, the source grounding GND of the one DMOS pipe DM1 and the 2nd DOMS pipe DM2, drain electrode is connected with the set end with the reset terminal of rest-set flip-flop RS1 respectively with the 2nd DMOS pipe DM2 in the drain electrode of the one DMOS pipe DM1, the output of rest-set flip-flop RS1 is the high drive output signal end, wherein, DMOS pipe DM1 and the 2nd DMOS pipe DM2 are the DMOS pipe of high pressure resistant 600V.When conventional level change-over circuit shown in Figure 1 is worked, the grid of signal controlling the one DMOS pipe DM1 of first output output of pulse generator PG1, the grid of signal controlling the 2nd DMOS pipe DM2 of second output output of pulse generator PG1, the state that makes win DMOS pipe DM1 and the 2nd DMOS pipe DM2 be in out or close, electric current by first resistance R 1 and second resistance R 2 just can be converted to voltage signal like this, (15V～16V, the operating voltage of pulse generator is usually in the level conversion to high pressure (600V) of 15V～16V) from low pressure to realize control signals transmitted.Usually can take very big area owing to be used for the DMOS pipe of level conversion at domain, so this conventional level change-over circuit, two DMOS pipes domain area occupied in chip of its use is bigger, causes chip cost very high.

China's invention disclosed patent " a kind of high voltage level change-over circuit " (application number: 200510024165.3, publication number: CN1829089A, open day: on 09 06th, 2006), it discloses a kind of single-ended high voltage level change-over circuit that is used for half-bridge drive circuit, it can reduce the chip layout area, and then can reduce chip cost, reduce chip power-consumption, this high voltage level change-over circuit, as shown in Figure 2, which comprises at least: a high pressure DMOS pipe DM1, as switch, grid input low-voltage control signal CS at high pressure DMOS pipe DM1, drain electrode at high pressure DMOS pipe DM1 is connected with a high pressure decoding circuit 14, be used for the signal that the drain electrode of high pressure DMOS pipe DM1 is exported is decoded, DM1 realizes the conversion of low-voltage signal to the high pressure signal by control DMOS pipe, decode by the signal after 14 pairs of conversions of high pressure decoding circuit again, thereby obtain high drive output signal DH, described high pressure decoding circuit mainly is to utilize the rising edge of two triggers to trigger the function that realizes circuit.This high voltage level change-over circuit is compared with conventional level change-over circuit shown in Figure 1, and therefore high voltage bearing DMOS pipe of its needs has effectively dwindled chip area, and then lowered chip cost, has reduced chip power-consumption.This high voltage level change-over circuit has an obvious characteristic in implementation procedure, be exactly that low-voltage control signal CS is made up of the pulse signal of two different duty, promptly be equivalent to input to DMOS pipe two signals of DM1 and this two signals and have different pulse durations, and then check the state of high drive output signal DH by the form that detects pulse duration, also just realized the level transfer of low pressure to high pressure, but because VB generally is a high pressure, when VB is high pressure, even a very short time also can be caused very big electric current and power consumption, service time was longer when therefore the signal controlling DMOS that pulse duration is bigger among the low-voltage control signal CS managed DM1, make chip power-consumption strengthen, easier heating, thus cause chip more harsh to using environment requirement.

Summary of the invention

Technical problem to be solved in the utility model provides and a kind ofly can effectively reduce the chip layout area, reduces chip cost, and can reduce the single-ended high voltage level change-over circuit that is used for bridge drive circuit of chip power-consumption greatly.

The utility model solves the problems of the technologies described above the technical scheme that is adopted: a kind of single-ended high voltage level change-over circuit that is used for bridge drive circuit, it is characterized in that comprising first pulse generator that is used to produce the low voltage control pulse signal of forming by the pulse signal of two groups of different pulse numbers, high voltage bearing DMOS pipe, sampling resistor and high pressure decoding circuit, the signal output part of described first pulse generator is connected with the grid of described DMOS pipe, the equal ground connection of the source electrode of described DMOS pipe and substrate, the drain electrode of described DMOS pipe is connected with second end of described sampling resistor and the signal input part of described high pressure decoding circuit respectively, first end of described sampling resistor all is connected with the power end of high voltage level with the power end of described high pressure decoding circuit, the ground end of described high pressure decoding circuit is connected with the ground end of high voltage level, and the signal output part of described high pressure decoding circuit is the high drive output signal end; The low voltage control pulse signal of the signal output part output of described first pulse generator is controlled described DMOS pipe conducting or disconnection, the switching signal that described sampling resistor is changed described DMOS pipe is that voltage signal is realized the level conversion of low pressure to high pressure, the described high pressure decoding circuit voltage signal after the described sampling resistor conversion of decoding.

The signal output part of described high pressure decoding circuit is connected with PMOS pipe and NMOS pipe, the signal output part of described high pressure decoding circuit is connected with the grid of described PMOS pipe and the grid of described NMOS pipe respectively, the source electrode of described PMOS pipe all is connected with the power end of high voltage level with substrate, the source electrode of described NMOS pipe all is connected with the ground end of high voltage level with substrate, the drain electrode of described PMOS pipe is connected with the drain electrode of described NMOS pipe, and its public connecting end is the high drive output signal end.

In the described low voltage control pulse signal wherein set of pulses signal comprise a pulse, another group pulse signal comprises two pulses in the described low voltage control pulse signal, and the time interval of these two described pulses is a Dead Time of the half-bridge drive circuit of this single-ended high voltage level change-over circuit of use.

Described high pressure decoding circuit mainly produces the pulse of the length of a delay time section greater than the Dead Time of the half-bridge drive circuit that uses this single-ended high voltage level change-over circuit, and described high pressure decoding circuit detects the pulse number of the low voltage control pulse signal of described first pulse generator generation in the delay time section of the pulse of its generation.

Described high pressure decoding circuit is mainly by first inverter, second pulse generator, second inverter, the one or two with the door, the two or two with door and rest-set flip-flop composition, the input of described first inverter is that the signal input part of described high pressure decoding circuit is connected with the drain electrode of described DMOS pipe, the output of described first inverter respectively with the signal input part of described second pulse generator, the described the 1 with input of door with the described the 22 with an input be connected, the signal output part of described second pulse generator is connected with another input of door with the described the 22 with the input of described second inverter respectively, the output of described second inverter is connected with another input of door with the described the 1, the described the 1 with the door output be connected with the set end of described rest-set flip-flop, the described the 22 with the door output be connected with the reset terminal of described rest-set flip-flop, the signal output part of described rest-set flip-flop is the signal output part of described high pressure decoding circuit.

Compared with prior art, advantage of the present utility model is only to have used a DMOS pipe in the level conversion process of high pressure carrying out low pressure, because the shared area in chip of the DMOS pipe with high-voltage resistance capability is relatively large, compare and use two DMOS pipes to realize the conventional level change-over circuit of level conversion, more chip area can be saved, therefore chip cost can be reduced greatly; Compare with the existing high voltage level change-over circuit of a DMOS pipe realization level conversion that also only uses, because existing high voltage level change-over circuit is used for realizing the source electrode of the DMOS pipe of high voltage level conversion and reaches 600 volts with pressure reduction between draining, even very little electric current also can cause very big power, the power consumption of long more generation of service time is big more, therefore its low-voltage control signal is the control signal that adopts at least two different duty, the relative broad of width that wherein has a control signal at least, this signal can produce big power consumption in transfer process, and the utility model can use the shortest low voltage control pulse signal of pulse duration that the grid of DMOS pipe is controlled, just the shortest in the time that switch transition process mesohigh DMOS pipe is opened like this, the power consumption minimum effectively reduces the power consumption of chip.

Description of drawings

Fig. 1 is conventional level change-over circuit figure;

Fig. 2 is existing high voltage level change-over circuit figure;

Fig. 3 is single-ended high voltage level change-over circuit figure of the present utility model;

Fig. 4 is that a kind of physical circuit of single-ended high voltage level change-over circuit of the present utility model is realized schematic diagram;

Fig. 5 realizes the signal waveform schematic diagram of low pressure to the high voltage level conversion for using circuit shown in Figure 4.

Embodiment

Embodiment describes in further detail the utility model below in conjunction with accompanying drawing.

A kind of single-ended high voltage level change-over circuit that is used for bridge drive circuit that the utility model proposes, as shown in Figure 3, it comprises first pulse generator 20 that is used to produce the low voltage control pulse signal of being made up of the pulse signal of two groups of different pulse numbers, be used as the DMOS pipe DM4 of the high pressure resistant 600V of switch, sampling resistor R4 and high pressure decoding circuit 10, the DMOS pipe DM4 of this high pressure resistant 600V has high pressure to be isolated and the switching signal transfer function, the signal output part of first pulse generator 20 is connected with the grid of DMOS pipe DM4, source electrode and the equal ground connection of substrate of DMOS pipe DM4, the drain electrode of DMOS pipe DM4 is connected with second end of sampling resistor R4 and the signal input part of high pressure decoding circuit 10 respectively, first end of sampling resistor R4 all is connected with power end (600V) VB of high voltage level with the power end of high pressure decoding circuit 10, the ground end of high pressure decoding circuit 10 is connected with ground end (585V) VS of high voltage level, and the signal output part of high pressure decoding circuit 10 is the high drive output signal end; Even the grid of the low voltage control pulse signal PS control DMOS pipe DM4 of the signal output part of first pulse generator 20 output makes DMOS pipe DM4 conducting or disconnection DMOS pipe DM4 be in the state that opens or closes, when low voltage control pulse signal PS is high level, DMOS pipe DM4 is for opening state, when low voltage control pulse signal PS is low level, DMOS pipe DM4 is an off status, sampling resistor R4 is converted to voltage signal with the switching signal that DMOS manages DM4, so just realized the level conversion of low pressure to high pressure, decode by the voltage signal after 10 pairs of sampling resistor R4 conversions of high pressure decoding circuit again, thus the state of definite high drive output signal.At this, can adopt multiple existing mode to realize first pulse generator 20 according to the function of first pulse generator 20.

In the actual application, also can be at the signal output part of high pressure decoding circuit 10 to connecting some buffer(buffers between the high-voltage driven signal output) or inverter to increase the driving force of high drive output signal HO, PMOS pipe P1 and NMOS pipe N1 have been connected such as the signal output part of high pressure decoding circuit 10 in this embodiment, PMOS pipe P1 and NMOS pipe N1 form inverter, the signal output part of high pressure decoding circuit 10 is connected with the grid of PMOS pipe P1 and the grid of NMOS pipe N1 respectively, the source electrode of PMOS pipe P1 all is connected with the power end VB of high voltage level with substrate, the source electrode of NMOS pipe N1 all is connected with the ground end VB of high voltage level with substrate, the drain electrode of PMOS pipe P1 is connected with the drain electrode of NMOS pipe N1, and its public connecting end is as high drive output signal end output high drive output signal HO.

In this specific embodiment, as shown in Figure 5, among the low voltage control pulse signal PS wherein set of pulses signal comprise a pulse, another group pulse signal comprises two pulses among the low voltage control pulse signal PS, and the time interval of these two pulses is a Dead Time of the half-bridge drive circuit of this single-ended high voltage level change-over circuit of use.

In this specific embodiment, the major function of high pressure decoding circuit 10 is that the high voltage level pulse signal of finishing after the level conversion is decoded, high pressure decoding circuit 10 can produce the pulse of the length of a delay time section greater than the Dead Time of the half-bridge drive circuit that uses this single-ended high voltage level change-over circuit, its decoding principle is that the pulse number that detects the low voltage control pulse signal of first pulse generator, 20 generations in the delay time section of the pulse of its generation is realized decoding function, after high pressure decoding circuit 10 detects a pulse, produce a signal high drive output signal end is changed to a state that opens or closes, and in a delay time section, detect whether also have second pulse arrival, if in this delay time section, detect second pulse, produce a signal high drive output signal end is changed to the state that open or close opposite with preceding state this moment, if do not detect second pulse in this delay time section, then the on off state of high drive output signal end remains unchanged.At this, the time span of described delay time section is greater than the Dead Time of the half-bridge drive circuit that uses this single-ended high voltage level change-over circuit.

At this, high pressure decoding circuit 10 as shown in Figure 4, it is mainly by first inverter 101, second pulse generator 102, second inverter 103, the one or two with the door 104, the two or two forms with door 105 and rest-set flip-flop 106, first inverter 101 has filter function, the input of first inverter 101 is that the signal input part of high pressure decoding circuit 10 is connected with the drain electrode of DMOS pipe DM4, the output of first inverter 101 respectively with the signal input part of second pulse generator 102, the one or two is connected with an input of 105 with the two or two with input of door 104, the signal output part of second pulse generator 102 is connected with another input of door 105 with the two or two with the input of second inverter 103 respectively, the output of second inverter 103 is connected with another input of door 104 with the one or two, the one or two is connected with the set end of rest-set flip-flop 106 with door 104 output, the two or two is connected with the reset terminal of rest-set flip-flop 106 with door 105 output, and the signal output part of rest-set flip-flop 106 is the signal output part of high pressure decoding circuit 10.

Fig. 5 has provided and has used the signal waveform schematic diagram that circuit shown in Figure 4 realizes that low pressure is changed to high voltage level.Signal LO represents to use the low-voltage driving output signal of the half-bridge drive circuit of this single-ended high voltage level change-over circuit among Fig. 5; Signal PS is the low voltage control pulse signal of grid of DMOS pipe DM4 that is used to drive the 600V high pressure of the signal output part output of first pulse generator 20, also is the pulse signal that this single-ended high voltage level change-over circuit produces according to the sequential needs; Signal PSA represent that the voltage signal after the sampling resistor R4 conversion forms through first inverter, the 101 anti-phase backs with filter function with the similar pulse output signals of low voltage control pulse signal PS; Signal PD represents the pulse delay output signal that the signal output part of second pulse generator 102 produces; Signal HO represents the high drive output signal that public connecting end that the drain electrode of PMOS pipe P1 is connected with the drain electrode of NMOS pipe N1 is exported as the high drive output signal end.Low voltage control pulse signal PS be one with the relevant pulse signal of low-voltage driving output signal LO output state, when being low level, low voltage control pulse signal PS only comprises a pulse at the high drive output signal HO of needs output; When the high drive output signal HO of needs output is high level, low voltage control pulse signal PS can produce a pulse respectively in the moment behind the Dead Time of the trailing edge moment of low-voltage driving output signal LO and the half-bridge drive circuit of delaying time, just produce two pulses in this time period, the high drive output signal is a high level when second pulse arrives like this.

At this, function according to second pulse generator 102 can adopt multiple existing mode to realize second pulse generator 102, the function of second pulse generator 102 is: when the signal input part of second pulse generator 102 does not have pulse output signals PSA to arrive, the pulse delay output signal PD of its signal output part output is low level, i.e. PD=0; During PD=0, when the signal input part of second pulse generator 102 has pulse output signals PSA to arrive, the pulse trailing edge of pulse output signals PSA can make the signal output part of second pulse generator 102 produce a high level time delayed signal, and this moment, pulse delay output signal PD became " 1 " by " 0 "; During PD=1, the pulse output signals PSA that arrives the signal input part of second pulse generator 102 once more can be to the 102 generation effects of second pulse generator; Behind a delay time, the pulse delay output signal PD of the signal output part of second pulse generator 102 output becomes " 0 " by " 1 ", and the delay time of PD=1 state is greater than the Dead Time of half-bridge drive circuit.Below for introducing the detailed process of single-ended high voltage level change-over circuit realization low voltage level of the present utility model in detail to the high voltage level conversion in conjunction with Fig. 4 and Fig. 5:

1), after the DMOS of the low voltage control pulse signal PS arrival 600V high pressure that first pulse generator 20 produces according to the circuit sequence needs manages the grid of DM4, carry out low voltage level to the high voltage level conversion through DMOS pipe DM4 and sampling resistor R4, again through first inverter 101 with filter function anti-phase after, export one and the duplicate pulse output signals PSA of low voltage control pulse signal PS waveform, there is extremely short transmission delay in pulse output signals PSA with respect to low voltage control pulse signal PS, can ignore, each pulse meeting of low voltage control pulse signal PS converts the identical pulse of pulse output signals PSA to;

When 2), the pulse output signals PSA of the output of first inverter 101 output is low level always, the pulse delay output signal PD of the signal output part output of second pulse generator 102 also is a low level, be PD=0, also just obtaining rest-set flip-flop 106(this moment is the basic rest-set flip-flop that two NOR gate are formed) the set end be 0, reset terminal is 0, so the signal Q of the signal output part of rest-set flip-flop 106 output at this moment maintains the original state 1, thereby high drive output signal HO is 0;

When 3), first pulse of the pulse output signals PSA of the output of first inverter 101 output arrives second pulse generator 102, PD=0, the signal PDB=1 of the output output of second inverter 103, the set end that also just obtain rest-set flip-flop 106 this moment is 1, reset terminal is 0, the signal Q of the signal output part of rest-set flip-flop 106 output at this moment is 1, and high drive output signal HO is 0;

4), first pulse upset of the pulse output signals PSA of the output of first inverter 101 output, when being PSA=0, trigger second pulse generator 102 and produce a pulse delay output signal PD, PD=1 in this time period, the signal PDB=0 of the output of second inverter 103 output at this moment, the set end that also just obtain rest-set flip-flop 106 this moment is 0, reset terminal is 0, so the signal Q of the signal output part of rest-set flip-flop 106 output at this moment keeps the state 1 of front, high drive output signal HO still is 0;

5), during pulse delay output signal PD=1, the signal input part of second pulse generator 102 does not have new pulse to arrive, the output state of rest-set flip-flop 106 remains unchanged, the signal Q of the signal output part of rest-set flip-flop 106 output just is 1, high drive output signal HO is 0, remain to the PD upset is 0 always, and so just having got back to preceding surface state 1(is process 1) circulate;

6), during pulse delay output signal PD=1, if the signal input part of second pulse generator 102 has new pulse to arrive, PSA=1 just, this moment pulse delay output signal PD=1, the signal PDB=0 of the output output of second inverter 103, the set end that also just obtain rest-set flip-flop 106 this moment is 0, reset terminal is 1, it is 0 that the signal Q of the signal output part output of rest-set flip-flop 106 is just arranged this moment, and high drive output signal HO is 1;

When 7), pulse output signals PSA overturns, because pulse delay output signal PD=1, this trailing edge can be to the 102 generation effects of second pulse generator, during pulse output signals PSA=0, this moment pulse delay output signal PD=1, the signal PDB=0 of the output output of second inverter 103, the set end that also just obtain rest-set flip-flop 106 this moment is 0, reset terminal is 0, so the signal Q of the signal output part of rest-set flip-flop 106 output at this moment keeps the state 0 of front, high drive output signal HO still is 1;

8), after the delay time of pulse delay output signal PD arrives, pulse delay output signal PD=0, this moment pulse output signals PSA=0, the set end that also just obtain rest-set flip-flop 106 this moment is 0, reset terminal is 0, so the signal Q of the signal output part of rest-set flip-flop 106 output at this moment maintains the original state 0, thereby high drive output signal HO is 1, up to state 3(is process 3) first inverter 101 output output pulse output signals PSA produced first new pulse again when arriving second pulse generator 102, PD=0, the signal PDB=1 of the output output of second inverter 103, the set end that also just obtain rest-set flip-flop 106 this moment is 1, reset terminal is 0, the signal Q of the signal output part of rest-set flip-flop 106 output at this moment is 1, high drive output signal HO is 0, and the 4(that at this moment next just can get the hang of is a process 4) circulated.

In sum, when low voltage control pulse signal PS had only a pulse in the delay time section of pulse delay output signal PD=1, high drive output signal HO was a low level like this, and when two pulses were arranged, high drive output signal HO was a high level.Single-ended high voltage level change-over circuit of the present utility model has only used the DMOS pipe of a high pressure resistant 600V just to finish the level conversion process of low pressure to high pressure, realize that with respect to use conventional method shown in Figure 1 low pressure needs two DMOS pipes to the level shifting circuit of high pressure, the utility model has only used a DMOS pipe, in chip layout, save a large amount of areas, greatly reduced chip cost; Because the drain electrode of DMOS pipe is to the high pressure that between the ground is 600V, even on this DMOS pipe, very small electric current is arranged, also can produce very big power consumption, and power consumption and the service time of this DMOS pipe in one-period almost is directly proportional, high voltage level change-over circuit shown in Figure 2 adopts the signal of different pulse durations to realize that low pressure arrives the level conversion of high pressure, that group signal of pulse duration broad can produce bigger power consumption, and the signal of the utility model control DMOS pipe all adopts pulse to realize, only the moment conducting DMOS that arrives in pulse manages, so can lower power consumption to greatest extent.

Claims

1. single-ended high voltage level change-over circuit that is used for bridge drive circuit, it is characterized in that comprising first pulse generator that is used to produce the low voltage control pulse signal of forming by the pulse signal of two groups of different pulse numbers, high voltage bearing DMOS pipe, sampling resistor and high pressure decoding circuit, the signal output part of described first pulse generator is connected with the grid of described DMOS pipe, the equal ground connection of the source electrode of described DMOS pipe and substrate, the drain electrode of described DMOS pipe is connected with second end of described sampling resistor and the signal input part of described high pressure decoding circuit respectively, first end of described sampling resistor all is connected with the power end of high voltage level with the power end of described high pressure decoding circuit, the ground end of described high pressure decoding circuit is connected with the ground end of high voltage level, and the signal output part of described high pressure decoding circuit is the high drive output signal end; The low voltage control pulse signal of the signal output part output of described first pulse generator is controlled described DMOS pipe conducting or disconnection, the switching signal that described sampling resistor is changed described DMOS pipe is that voltage signal is realized the level conversion of low pressure to high pressure, the described high pressure decoding circuit voltage signal after the described sampling resistor conversion of decoding.

2. a kind of single-ended high voltage level change-over circuit that is used for bridge drive circuit according to claim 1, the signal output part that it is characterized in that described high pressure decoding circuit is connected with PMOS pipe and NMOS pipe, the signal output part of described high pressure decoding circuit is connected with the grid of described PMOS pipe and the grid of described NMOS pipe respectively, the source electrode of described PMOS pipe all is connected with the power end of high voltage level with substrate, the source electrode of described NMOS pipe all is connected with the ground end of high voltage level with substrate, the drain electrode of described PMOS pipe is connected with the drain electrode of described NMOS pipe, and its public connecting end is the high drive output signal end.

3. a kind of single-ended high voltage level change-over circuit that is used for bridge drive circuit according to claim 1 and 2, it is characterized in that in the described low voltage control pulse signal that wherein set of pulses signal comprises a pulse, another group pulse signal comprises two pulses in the described low voltage control pulse signal, and the time interval of these two described pulses is a Dead Time of the half-bridge drive circuit of this single-ended high voltage level change-over circuit of use.

4. a kind of single-ended high voltage level change-over circuit that is used for bridge drive circuit according to claim 3, it is characterized in that described high pressure decoding circuit mainly produces the pulse of the length of a delay time section greater than the Dead Time of the half-bridge drive circuit that uses this single-ended high voltage level change-over circuit, described high pressure decoding circuit detects the pulse number of the low voltage control pulse signal of described first pulse generator generation in the delay time section of the pulse of its generation.

5. a kind of single-ended high voltage level change-over circuit that is used for bridge drive circuit according to claim 4, it is characterized in that described high pressure decoding circuit is mainly by first inverter, second pulse generator, second inverter, the one or two with the door, the two or two with door and rest-set flip-flop composition, the input of described first inverter is that the signal input part of described high pressure decoding circuit is connected with the drain electrode of described DMOS pipe, the output of described first inverter respectively with the signal input part of described second pulse generator, the described the 1 with input of door with the described the 22 with an input be connected, the signal output part of described second pulse generator is connected with another input of door with the described the 22 with the input of described second inverter respectively, the output of described second inverter is connected with another input of door with the described the 1, the described the 1 with the door output be connected with the set end of described rest-set flip-flop, the described the 22 with the door output be connected with the reset terminal of described rest-set flip-flop, the signal output part of described rest-set flip-flop is the signal output part of described high pressure decoding circuit.