CN201839446U

CN201839446U - Heterogeneous network interconnection gateway device

Info

Publication number: CN201839446U
Application number: CN2010205901232U
Authority: CN
Inventors: 陈分雄; 肖万源; 王典洪; 沈耀东; 韩家宝; 彭岳其
Original assignee: China University of Geosciences
Current assignee: China University of Geosciences
Priority date: 2010-11-03
Filing date: 2010-11-03
Publication date: 2011-05-18
Anticipated expiration: 2020-11-03

Abstract

The utility model discloses a heterogeneous network interconnection gateway device, which is composed of a WiFi wireless radio frequency transceiver unit, a ZigBee wireless radio frequency transceiver unit, an Internet interface control unit, an ARM11 embedded processor control unit, a key interface control unit, a touch screen interface control unit, a USB interface and an SD card interface control unit. The WiFi wireless radio frequency transceiver unit, the ZigBee wireless radio frequency transceiver unit, the Internet interface control unit, the touch screen interface control unit, the USB interface and the SD card interface control unit are respectively in two-way electrical connection with the ARM11 embedded processor control unit; and the key interface control unit is in one-way electrical connection with the ARM11 embedded processor control unit. The gateway device realizes interconnection between three heterogeneous networks of WiFi, ZigBee and Internet, provides a plurality of network access schemes for a wireless sensor network, and realizes sharing and transmission of monitoring data among the heterogeneous networks.

Description

A kind of heterogeneous network interconnecting gateway equipment

Technical field

The utility model relates to the wireless sensor network technology field, is specifically related to a kind of heterogeneous network interconnecting gateway equipment.

Background technology

Wireless sensor network is current receive much concern in the world, relate to multidisciplinary height intersection, the integrated hot research field, forward position of knowledge height.Development of technology such as sensor technology, MEMS (micro electro mechanical system), modern network and radio communication, the generation and the development of modern wireless sensor network have been promoted, wireless sensor network has been expanded people's information obtaining ability, the physical message of objective world is linked together with the transmission network, in next generation network, will provide direct, effective, the most real information for people.Wireless sensor network can obtain objective physical message, has very wide application prospect, can be applied to fields such as military and national defense, industrial or agricultural control, city management, biologic medical, environment measuring, rescue and relief work, deathtrap Long-distance Control, cause the great attention of many national academias and industrial quarters, be considered to one of technology of power that 21 century had an immense impact on.

The ZigBee agreement is based upon on the IEEE 802.15.4 (LR_WPAN, low rate wireless personal-area network), is one of networking technology of wireless sensor network first-selection, carries out MANET by the ZigBee agreement between a large amount of sensor nodes.Its major advantage is that agreement realizes simply, cost of investment is low, the network insertion capacity is big, is particularly suitable for the low-power consumption occasion, as: the wireless senser in the industry detects, inferior grade control; Personal monitoring instrument, low-consumption wireless Medical Devices; High-end toy; Electrical equipment networking and control; Wireless consumer device; HVAC and light control etc., under the low power consumption standby mode, common No. 5 dry cells of two joints can use more than 6 months.Between the ZigBee message transmission rate lower (less than 250Kb/s), 10～50 meters of effective coverage ranges, be used for monitor temperature, humidity, illumination equiscalar data more.WiFi is a kind of short-distance wireless communication technology that is based upon on IEEE 802.11a, 802.11b, the 802.11g agreement, the WiFi message transmission rate can reach 54Mb/s, about 100 meters of coverages, be particularly suitable for gathering audio frequency, video image isovector data, and require the higher occasion of transmission rate.Therefore, press for the wireless sensor network of forming by the heterogeneous nodes that meets different agreement.And existing in a large number wireless senser network node equipment is difficult to bear the function of gateway various protocols conversion, and has that antijamming capability is low, power consumption is high, cost is expensive and bulky problem.

Summary of the invention

The purpose of this utility model is to provide a kind of heterogeneous network interconnecting gateway equipment, it not only can carry out various administering and maintaining to the wireless sensor network that carries out MANET by WiFi and ZigBee agreement between a large amount of sensor nodes, receive and the display network topological structure, the network health state, work such as Monitoring Data, also can be wireless sensor network the multiple network access scheme is provided, can realize sharing and transmission of Monitoring Data between three kinds of heterogeneous networks, thus the transparent forwarding that makes the WiFi network that is linked into the Internet and ZigBee network have Monitoring Data, network remote monitoring, the function of diagnosis and management.

The utility model is for achieving the above object, adopt following technical scheme: a kind of heterogeneous network interconnecting gateway equipment is provided, forms by WiFi radio transceiver unit, ZigBee radio transceiver unit, ARM11 flush bonding processor control unit, internet interface control unit, touch-screen device interface control unit, keystroke interface control unit, USB interface and SD card control unit.WiFi radio transceiver unit, ZigBee radio transceiver unit, internet interface control unit, touch-screen device interface control unit, USB interface and SD card control unit respectively with two-way electrical connection of ARM11 flush bonding processor control unit; The keystroke interface control unit is connected with ARM11 flush bonding processor control unit unidirectional electrical.

WiFi radio transceiver unit adopts the WM-G-MR-09 chip, ZigBee radio transceiver unit adopts the CC2530 chip, the internet interface control unit adopts the DM9000AE chip, ARM11 flush bonding processor control unit adopts the S3C6410 chip, touch-screen device interface control unit adopts the AT043TN24V.1 chip, USB interface and SD card control unit carry out outside expansion by S3C6410 chip internal resource, can outer tape splicing SD interface, the equipment of USB interface.

Processing and control element (PCE) of the present utility model adopts the ARM11 processor, can change gateway and insert single shortcoming.The ARM11 processor has the superiority than traditional ARM7, ARM9 processor, and it is providing the high performance while, has also guaranteed the finiteness of low-power consumption and area.The streamline of ARM11 processor is different with former ARM kernel, and it is made up of 8 level production lines, has improved at least 40% throughput than former ARM kernel, and 8 level production lines can make 8 instructions be performed simultaneously.The ARM11 processor is avoided data collision in the streamline by forwarding, and by realizing that the jump forecasting technology keeps best pipeline efficiency.When the ARM11 processor is used for making its processing to be optimized to higher streamline throughput by making of these special techniques, can also keep and the same validity of 8 level production lines (ARM9 processor).

Relevant informations such as WiFi and the transmission of ZigBee network self network topology structure, network health state, Monitoring Data, after being transferred to ARM11 flush bonding processor control unit and handling by serial ports, show and receive the orders such as network management of user's key entry by touch-screen device interface control unit, or pass through the internet interface control unit and insert the Internet.

WiFi radio transceiver unit and two-way electrical connection of ARM11 flush bonding processor control unit.The 1st pin GND of WM-G-MR-09, the 3rd pin GND, the 8th pin GND ground connection, the 2nd pin ANT1 of WM-G-MR-09 connects inductance L 1, and inductance L 1 meets inductance L 2 and antenna F1, inductance L 2 ground connection; The 7th pin ECSn of WM-G-MR-09 is by resistance R 2 ground connection; The 9th pin VDD_HOST_IO of WM-G-MR-09 connects capacitor C 1 and 3.3V power supply, capacitor C 1 ground connection; The 4th pin ANT_SEL_P of WM-G-MR-09, the 6th pin SCLK, the 10th pin GPIO[6], the 11st pin GPIO[5], the 13rd pin GPIO[2], the 15th pin GPIO[4], the 29th pin BT_STATE, the 30th pin WL_ACTIVE, the 33rd pin BT_PRIORITY, the 34th pin GPIO[0] unsettled; The 16th pin GPIO[1 of WM-G-MR-09] negative terminal of sending and receiving optical diode D1, the anode of D1 connects the 3.3V power supply by resistance R 1; The 17th pin VDD1.8 of WM-G-MR-09 is by capacitor C 6 ground connection; The 18th pin VDD1.2 of WM-G-MR-09 is by capacitor C 7 ground connection; The 19th pin GND ground connection of WM-G-MR-09; The 23rd pin IF_SEL_1 of WM-G-MR-09 is by resistance R 3 ground connection; The 24th pin IF_SEL_2 of WM-G-MR-09 is by resistance R 4 ground connection; The 25th pin VDD1.8A of WM-G-MR-09 is by capacitor C 2, C8 ground connection; The 26th pin GND ground connection of WM-G-MR-09; The 27th pin VDD3.3 of WM-G-MR-09 connects capacitor C 3 and 3.3V power supply, capacitor C 3 ground connection; The 28th pin VDD3.3 of WM-G-MR-09 links to each other with the 27th pin VDD3.3 of WM-G-MR-09; The 20th pin SD_CMD/SPI_SDI of WM-G-MR-09, the 14th pin SD_CLK/SPI_CLK, the 21st pin SD_DAT[0]/SPI_SCSn, the 5th pin SD_DAT[1]/SPI_SDO, the 22nd pin SD_DAT[2]/SPI_SINTn, the 12nd pin SD_DAT[3], the 31st pin PDn, the 32nd pin RESETn respectively with the A16 pin X_MmcCMD1 of S3C6410, J11 pin X_MmcCLK1, H11 pin X_MmcDATA1_0, C17 pin X_MmcDATA1_1, B16 pin X_MmcDATA1_2, H10 pin X_MmcDATA1_3, C4 pin GPE2, B3 pin GPE1 links to each other; The 31st pin PDn connecting resistance R5 and the capacitor C 4 of WM-G-MR-09, resistance R 5 connects the 3.3V power supply, capacitor C 4 ground connection; The 32nd pin RESETn connecting resistance R6 and the capacitor C 5 of WM-G-MR-09, resistance R 6 connects the 3.3V power supply, capacitor C 5 ground connection.

ZigBee radio transceiver unit and two-way electrical connection of ARM11 flush bonding processor control unit.The B21 pin X_uTXD3 of S3C6410 links to each other with the 17th pin RX of CC2530, the J14 pin X_uRXD3 of S3C6410 links to each other with the 16th pin of CC2530, the 10th pin DVDD of CC2530, the 39th pin AVDD_DREG, the 21st pin AVDD5/AVDD_SOC, the 31st pin AVDD_GUARD connects the 3.3V power supply, and respectively by capacitor C 1, C4, C2, C3 ground connection, the 1st pin DGND_USB of CC2530, the 2nd pin USB_M, the 3rd pin USB_P, the equal ground connection of the 4th pin DVDD_USB, the 20th pin RESET_N connecting resistance R1 and the capacitor C 5 of CC2530, resistance R 1 connects the 3.3V power supply, capacitor C 5 ground connection, the 41st pin GND Exposed ground connection of CC2530, the 30th pin RBIAS of CC2530 is by resistance R 2 ground connection, the 25th pin RF_P of CC2530 connects inductance L 1 by C7, inductance L 2, capacitor C 11, inductance L 1 ground connection, the 26th pin RF_N of CC2530 connects inductance L 2 by capacitor C 8, inductance L 3, capacitor C 12, capacitor C 12 ground connection, inductance L 3 connects capacitor C 9, C10, C11, capacitor C 9 ground connection, capacitor C 10 connects antenna and capacitor C 17, capacitor C 17 ground connection, the 32nd pin P2.4/XOSC32_Q2 of CC2530, the 33rd pin P2.3/XOSC32_Q1 is respectively by capacitor C 16, capacitor C 15 ground connection, the 32nd pin P2.4/XOSC32_Q2 of CC2530, the 33rd pin P2.3/XOSC32_Q1 links to each other by crystal oscillator Y2, the 22nd pin XOSC_Q1 of CC2530, the 23rd pin XOSC_Q2 is respectively by capacitor C 14, capacitor C 13 ground connection, the 22nd pin XOSC_Q1 of CC2530, the 23rd pin XOSC_Q2 links to each other by crystal oscillator Y1, and the 40th pin of CC2530 is by capacitor C 6 ground connection.

Internet interface control unit and two-way electrical connection of ARM11 flush bonding processor control unit.The AC19 pin X_EINT7 of S3C6410 meets the 34th pin INT of DM9000AE, the D1 pin Xm0_ADDR2 of S3C6410 meets the 32nd pin CMD of DM9000AE, the L4 pin Xm0_OEn of S3C6410 meets the 35 pin IOR# of DM9000AE, the J2 pin Xm0_WEn of S3C6410 meets the 36th pin IOW# of DM9000AE, the R3 pin Xm0_CSn1 of S3C6410 meets the 37 pin CS# of DM9000AE, the AD16 pin X_nRSTOUT of S3C6410 meets the 40 pin PWRST# of DM9000AE, the N2 pin Xm0_DATA0 of S3C6410, N1 pin Xm0_DATA1, M7 pin Xm0_DATA2, N3 pin Xm0_DATA3, M8 pin Xm0_DATA4, P2 pin Xm0_DATA5, N4 pin Xm0_DATA6, P3 pin Xm0_DATA7, M2 pin Xm0_DATA8, M4 pin Xm0_DATA9, L7 pin Xm0_DATA10, M3 pin Xm0_DATA11, L8 pin Xm0_DATA12, L2 pin Xm0_DATA13, K4 pin Xm0_DATA14, K1 pin Xm0_DATA15 respectively with the 18th pin SD0 of DM9000AE, the 17th pin SD1, the 16th pin SD2, the 14th pin SD3, the 13rd pin SD4, the 12nd pin SD5, the 11st pin SD6, the 10th pin SD7, the 31st pin SD8, the 29th pin SD9, the 28th pin SD10, the 27th pin SD11, the 26th pin SD12, the 25th pin SD13, the 24th pin SD14, the 22nd pin SD15 links to each other, the 43rd pin X2 of DM9000AE, the 41st pin X1 is respectively by capacitor C 1, C2 ground connection, the 43rd pin X2 of DM9000AE, the 41st pin X1 links to each other by crystal oscillator Y1, the 8th pin TX-of DM9000AE links to each other with the 2nd pin TD-of resistance R 1 with NET (U3 element), the 7th pin TX+ of DM9000AE links to each other with the 1st pin TD+ of resistance R 2 and NET, the 4th pin RX-of DM9000AE links to each other with the 6th pin RX-of resistance R 3 and NET, the 3rd pin RX+ of DM9000AE links to each other with the 3rd pin RX+ of resistance R 4 and NET, resistance R 1 and electronics R2 link to each other with capacitor C 3, electronics R3 and electronics R4 link to each other with capacitor C 4, capacitor C 3, C4 ground connection, the 38th pin LED2 of DM9000AE links to each other with the 10th pin LEDG-of NET, the 39th pin LED1 of DM9000AE links to each other with the 11st pin LEDY-of NET, the 9th pin LEDG+ of NET, the 12nd pin LEDY+ connects the 3.3V power supply, the 8th pin CHS_GND ground connection of NET.

The heterogeneous network interconnecting gateway equipment that the utility model provides has the following advantages:

1. the utility model is with low-power consumption, resourceful ARM11 flush bonding processor is a core, by meeting 802.11b agreement WiFi network chip WM-G-MR-09, the ZigBee network chip CC2530 and the Internet chip DM9000AE that meets ICP/IP protocol that meet the IEEE802.15.4 agreement, insert the WiFi network respectively, ZigBee network and the Internet, WiFi is provided, ZigBee, be interconnected between the three kinds of heterogeneous networks in the Internet, it is strong to have antijamming capability, low in energy consumption, with low cost and small and exquisite characteristics of volume, can be wireless sensor network the multiple network access scheme is provided, realize the shared and transmission of Monitoring Data between the heterogeneous network, thereby the transparent forwarding that makes the WiFi network that is linked into the Internet and ZigBee network have Monitoring Data, network remote monitoring, the function of diagnosis and management has vast market prospect.

2. gateway device of the present utility model can constitute complete control system with a slice ARM11 flush bonding processor S3C6410 chip and a small amount of peripheral circuit, owing to made full use of the flush bonding processor internal resource, system's hardware and software design reached minimize.

Description of drawings

Fig. 1 is a heterogeneous network interconnecting gateway device hardware of the present utility model system pie graph.

Fig. 2 is ARM11 flush bonding processor control unit of the present utility model and WiFi radio transceiver unit connecting circuit figure.

Fig. 3 is ARM11 flush bonding processor control unit of the present utility model and ZigBee radio transceiver unit connecting circuit figure.

Fig. 4 is the connecting circuit figure of ARM11 flush bonding processor control unit of the present utility model and internet interface control unit.

Fig. 5 is the connecting circuit figure of ARM11 flush bonding processor control unit of the present utility model and touch-screen device interface control unit.

Fig. 6 is the connecting circuit figure of ARM11 flush bonding processor control unit of the present utility model and keystroke interface control unit.

Fig. 7 is USB interface and the SD card control unit that ARM11 flush bonding processor control unit of the present utility model extends out.

Embodiment

In conjunction with the accompanying drawings the utility model is described in further detail with specific embodiment below.

Fig. 1 shows that heterogeneous network interconnecting gateway device hardware of the present utility model system constitutes.Form by WiFi radio transceiver unit 10, ZigBee radio transceiver unit 11, internet interface control unit 12, ARM11 flush bonding processor control unit 13, keystroke interface control unit 14, touch-screen device interface control unit 15, USB interface and SD card control unit 16.ARM11 flush bonding processor control unit respectively with WiFi radio transceiver unit, ZigBee radio transceiver unit, internet interface control unit, touch-screen device interface control unit, USB interface and two-way electrical connection of SD card control unit, be connected with keystroke interface control unit unidirectional electrical.

WiFi radio transceiver unit adopts the WM-G-MR-09 chip, ZigBee radio transceiver unit adopts the CC2530 chip, the internet interface control unit adopts the DM9000AE chip, ARM11 flush bonding processor control unit adopts the S3C6410 chip, and touch-screen device interface control unit adopts the AT043TN24V.1 chip.

At work, relevant informations such as WiFi and the transmission of ZigBee network self network topology structure, network health state, Monitoring Data, after being transferred to ARM11 flush bonding processor control unit and handling by serial ports, show and receive the orders such as network management of user's key entry by touch-screen device interface control unit, or send to the user terminal in a distant place by internet interface control unit access the Internet.

Fig. 2 show WiFi radio transceiver unit of the present utility model and with the connecting circuit figure of ARM11 flush bonding processor control unit, WiFi radio transceiver unit and two-way electrical connection of ARM11 flush bonding processor control unit.WiFi radio transceiver unit adopts the WM-G-MR-09 chip.WiFi full name Wireless Fidelity, claim the 802.11b standard again, it is a kind of short range wireless transmission technology, can in hundreds of feet scopes, support the radio signal that the Internet inserts, its great advantage is that transmission speed is higher, can reach 11Mbps, its effective propagation path is longer in addition, simultaneously with various existing 802.11DSSS hardware compatibilities, WM-G-MR-09 adopts SDIO 4-Bit pattern to be connected with S3C6410, the 21st pin of WM-G-MR-09, the 5th pin, the 22nd pin, the corresponding 4 bit data position DATA[0:3 of the 12nd pin], wherein the 5th pin is multiplexed with interrupt pin again, control to WM-G-MR-09 is mainly operated the WM-G-MR-09 internal register exactly, when sending data, earlier data are write in the transmission buffering area of WM-G-MR-09, write the command register that sends a command to WM-G-MR-09 then and send data, when WM-G-MR-09 receives data, the 5th pin SD_DAT[1 of WM-G-MR-09]/SPI_SDO can produce an interrupt signal, and S3C6410 reads received data in interrupt function.

Fig. 3 show ZigBee radio transceiver unit of the present utility model and with the connecting circuit figure of ARM11 flush bonding processor control unit, ZigBee radio transceiver unit and two-way electrical connection of ARM11 flush bonding processor control unit.The core component of ZigBee wireless receiving and dispatching control unit is CC2530, it is based on the on-chip system chip of IEEE802.15.4 agreement and ZigBee protocol application, CC2530 is integrated leading RF transceiver and strengthen the 8051MCU kernel of industrial standard can be finished powerful wireless sensor network node design with extremely low cost.The wireless receiving and dispatching control unit is stored, is compressed and pack the data of node collection, and form complete frame format packet and send with wireless mode, perhaps receive the packet of telegon in the ZigBee network, be transferred to ARM11 flush bonding processor control unit by serial ports and further handle.

Fig. 4 show internet interface control unit of the present utility model and with the connecting circuit figure of ARM11 flush bonding processor control unit, internet interface control unit and two-way electrical connection of ARM11 flush bonding processor control unit, this figure mainly illustrates the annexation of data signal pin and control signal pin, data[0:15 wherein] be data signal pin, INT, CMD, IOR#, IOW#, CS#, PWRST# are the control signal pin.INT is the interrupt signal pin, when DM9000AE receives data from network, produces an interrupt signal by the INT pin, and the notice microprocessor receives data; CMD is that address, data are selected pin, when the CMD pin is low level, and data[0:15] what transmit is address signal, when CMD is high level, data[0:15] what transmit is data-signal; The IOR# pin is selected for reading, and when IOR# is low level DM9000AE is carried out read operation, and is invalid when IOR# is high level; The IOW# pin is carried out write operation to DM9000AE for writing selection when IOW# is low level, invalid when IOW# is high level; The CS# pin is a chip selection signal, and low level is effective; PWRST# is the electrification reset pin, and when PWRST# produced the low level of 20ms, DM9000AE resetted.

Among Fig. 4, internet controller cell operation principle is: deposit RX FIFO when DM9000AE receives a packet in after by CRC check, on the INT pin, produce an interrupt signal, the head that one 4 byte is all arranged in each packet front that receives, can read the information of the packet that receives with MRCMDX and MRCMD register, wherein first byte is to receive Data Labels, judged whether that by reading this position data arrive, if this position is 0x01 then represents to have data to be received and to be saved among the RX SRAM, at this time data can be read and handled; If this position is 0x00, expression does not receive data; If, at this moment the DM9000AE chip will be restarted so that chip returns to normal condition neither 0x01 is not again 0x00 then thinks that unusual generation is arranged.Second byte is state information, and this byte is the status word that receives packet, and content wherein is identical with content among the accepting state register RSR.Can be used for judging whether the packet that is received is normal, or it is unusual which kind of has taken place, so just can carry out different operations, the control of the receipts that achieve a butt joint task unusually at different.The 3rd byte, the 4th byte have the length of data package that receives, and will control with this length in read data packet.The packet header of these four bytes is the information that DM9000AE adds when receiving data, does not belong to the content of packet.Be only the content of real packet since the data of the 5th byte, its length defines in the 3rd, 4 bytes.When sending bag data, check the mode of operation of DM9000AE earlier, then the data that will send are write TX FIFO SRAM, then the high byte that will send data length is write the MDRAH register, the low byte that will send data length is write the MDRAL register, be provided with at last and transmit sign, the 0th position of TCR register is set to 1, and DM9000AE will send depositing the data that send the data buffer zone in.

Fig. 5 show touch-screen device interface control unit of the present utility model and with the connecting circuit figure of ARM11 flush bonding processor control unit, touch-screen device interface control unit and two-way electrical connection of ARM11 flush bonding processor control unit.Touch-screen device interface control unit adopts LCD chip AT043TN24V.1, the AD19 pin X_EINT11/GPN11 of S3C6410, AA25 pin X_LCD_HSYNC/GPJ8, W22 pin X_LCD_VSYNC/GPJ9, AA24 pin X_LCD_VDEN/GPJ10, V19 pin X_LCD_VCLK/GPJ11, AE3 pin X_ADC_AIN4, AD4 pin X_ADC_AIN5, AE4 pin X_ADC_AIN6, AC3 pin X_ADC_AIN7 respectively with the 31st pin DISP of LCD, the 32nd pin HSYNC, the 33rd pin VSYNC, the 34th pin DE, the 30th pin PCLK, the 37th pin X1, the 38th pin Y1, the 39th pin X2, the 40th pin Y2 links to each other, the AE21 pin X_VD0/GPI0 of S3C6410, W14 pin X_VD1/GPI1, AE22 pin X_VD2/GPI2, V13 pin X_VD3/GPI3, AD21 pin X_VD4/GPI4, AB20 pin X_VD5/GPI5, W15 pin X_VD6/GPI6, AE23 pin X_VD7/GPI7, V14 pin X_VD8/GPI8, AC21 pin X_VD9/GPI9, AC22 pin X_VD10/GPI10, W16 pin X_VD11/GPI11, V15 pin X_VD12/GPI12, AD23 pin X_VD13/GPI13, W17 pin X_VD14/GPI14, AC24 pin X_VD15/GPI15, V16 pin X_VD16/GPJ0, AD24 pin X_VD17/GPJ1, Y22 pin X_VD18/GPJ2, AC25 pin X_VD19/GPJ3, AB25 pin X_VD20/GPJ4, AB24 pin X_VD21/GPJ5, W18 pin X_VD22/GPJ6, AB23 pin X_VD23/GPJ7 respectively with the 5th pin R0 of LCD, the 6th pin R1, the 7th pin R2, the 8th pin R3, the 9th pin R4, the 10th pin R5, the 11st pin R6, the 12nd pin R7, the 13rd pin G0, the 14th pin G1, the 15th pin G2, the 16th pin G3, the 17th pin G4, the 18th pin G5, the 19th pin G6, the 20th pin G7, the 21st pin B0, the 22nd pin B1, the 23rd pin B2, the 24th pin B3, the 25th pin B4, the 26th pin B5, the 27th pin B6, the 28th pin B7 links to each other, the 36th pin GND of LCD, the 3rd pin GND, the 29th pin GND ground connection, the 35th pin NC of LCD is unsettled, LCD the 1st pin VLED-is by resistance R 1 ground connection, the 2nd pin VLED+ is by capacitor C 1 ground connection, the 3rd pin FB of chip YB1518 meets the 1st pin VLED-of LCD, the 1st pin SW of YB1518 connects inductance L 1 and Schottky diode D1 anode, Schottky diode D1 negative terminal meets the 2nd pin VLED+ of LCD, the 5th pin VIN of YB5158 connects inductance L 1, the 5V power supply, capacitor C 3, capacitor C 2, capacitor C 3 and C2 ground connection, YB5158 the 2nd pin GND ground connection, YB5158 the 4th pin CTRL connecting resistance R2 and R3, resistance R 3 connects the 5V power supply, and resistance R 2 links to each other with the D23 pin X PwmTOUT1/GPF15 of S3C6410.

Its operation principle is: LCD is divided into 3 sub-pixels of red, green, blue with lattice pixels, and each sub-pixel accounts for 8 positions, respectively the R[0:7 of corresponding LCD], G[0:7], B[0:7] pin.When showing piece image, at first on the VSYNC of LCD pin, produce a high level, represent the beginning of a frame scan, then on the HSYNC of LCD pin, produce a high level, represent the beginning of a line scanning, if at this moment the DE pin of LCD is a high level, then at each rising edge of the clock signal PCLK of LCD, data VD[0:23] just write corresponding pixel, later on each point all so line by line one by one scanning go down.The X1 of LCD, Y1, X2, Y2 pin are for touching pin, AT043TN24V.1 is with the touch-screen of one 4 line resistance, when outer gauge pressure acts on that certain is some on the touch-screen, a conductive layer of touch-screen is connected the directions X power supply, just can detect this voltage at another conductive layer, the voltage signal of obtaining is carried out the A/D conversion, and the size of power supply voltage compares the coordinate that just can obtain the directions X of touch point with magnitude of voltage that obtains and add, and in like manner also can calculate the coordinate of Y direction.

Fig. 6 shows the connecting circuit figure of ARM11 flush bonding processor control unit of the present utility model and keystroke interface control unit, and the keystroke interface control unit is connected with ARM11 flush bonding processor control unit unidirectional electrical.The 1st of the AE17 pin X_EINT0/KpROW0/GPN0 connecting resistance R1 of S3C6410 and button K1, the 2nd pin, the 3rd of button K1, the 4th pin ground connection, resistance R 1 connects the 3.3V power supply, the 1st of the V10 pin X_EINT1/KpROW1/GPN1 connecting resistance R2 of S3C6410 and button K2, the 2nd pin, the 3rd of button K2, the 4th pin ground connection, resistance R 2 connects the 3.3V power supply, the 1st of the AD17 pin X_EINT2/KpROW2/GPN2 connecting resistance R3 of S3C6410 and button K3, the 2nd pin, the 3rd of button K3, the 4th pin ground connection, resistance R 3 connects the 3.3V power supply, the 1st of the AB17 pin X_EINT3/KpROW3/GPN3 connecting resistance R4 of S3C6410 and button K4, the 2nd pin, the 3rd of button K4, the 4th pin ground connection, resistance R 4 connects the 3.3V power supply, the 1st of the AE18 pin X_EINT4/KpROW4/GPN4 connecting resistance R5 of S3C6410 and button K5, the 2nd pin, the 3rd of button K5, the 4th pin ground connection, resistance R 5 connects the 3.3V power supply, the 1st of the AC18 pin X_EINT5/KpROW5/GPN5 connecting resistance R6 of S3C6410 and button K6, the 2nd pin, the 3rd of button K6, the 4th pin ground connection, resistance R 6 connects the 3.3V power supply.

The operation principle of button is: each button all follows the external interrupt pin of S3C6410 to connect, signal is not a high level on the pin when button is pressed, when button is pressed, produce a low level on the pin, S3C6410 will produce an interrupt signal, call the corresponding key interrupt service subroutine by interrupt mode, finish the function of button appointment.

Fig. 7 shows USB interface and the SD card control unit connecting circuit figure that ARM11 flush bonding processor control unit of the present utility model extends out, can outer tape splicing SD interface, the equipment of USB interface, and as USB flash disk, SD card etc.As can realize the operating system loading of this gateway equipment by the SD card.

The A17 pin X_MmcCDN0/MmcCDN1/GPG6 of S3C6410 and resistance R 8, the 11st pin nCD of SD interface links to each other, resistance R 8 connects the 3.3V power supply, the N17 pin Xhi_DATA16/EINT21/GPL13 of S3C6410 and resistance R 7, the 10th pin WP of SD interface links to each other, resistance R 7 connects the 3.3V power supply, the H13X_MmcDATA0_1/GPG3 of S3C6410 and resistance R 6, the 8th pin DAT1 of SD interface links to each other, resistance R 6 connects the 3.3V power supply, the B18 pin X_MmcDATA0_0/ADDR_CF2/GPG2 of S3C6410 and resistance R 5, the 7th pin DAT0 of SD interface links to each other, resistance R 5 connects the 3.3V power supply, the A18 pin X_MmcCLK0/ADDR_CF0/GPG0 of S3C6410 and resistance R 4, the 5th pin CLK of SD interface links to each other, resistance R 5 connects the 3.3V power supply, the G13 pin X_MmcCMD0/ADDR_CF1/GPG1 of S3C6410 and resistance R 3, the 2nd pin CMD of SD interface links to each other, resistance R 3 connects the 3.3V power supply, the G12X_MmcDATA0_3/GPG5 of S3C6410 and resistance R 2, the 1st pin CD/DAT3 of SD interface links to each other, resistance R 2 connects the 3.3V power supply, the C18X_MmcDATA0_2/GPG4 of S3C6410 and resistance R 1, the 9th pin DAT2 of SD interface links to each other, resistance R 1 connects the 3.3V power supply, the 6th pin VSS2 of SD interface, the 3rd pin VSS1, the 12nd pin VSS3, the 13rd pin VSS4 ground connection, the 4th pin VDD of SD interface connects 3.3V power supply and capacitor C 2, capacitor C 2 ground connection.

The P22 pin X_UsbDN connecting resistance R9 of S3C6410 and the 2nd pin D-of USB interface, resistance R 9 ground connection, the N22 pin X_UsbDP of S3C6410 links to each other with the 3rd pin D+ of resistance R 10 and USB interface, resistance R 10 ground connection, the 4th pin of USB interface, the 5th pin NC, the 6th pin NC, the 7th pin NC, the 8th pin NCGND ground connection, the 1st pin VBUS of USB connects inductance L 1, and inductance L 1 connects 5V power supply and capacitor C 1, capacitor C 1 ground connection.

In whole gateway device system, at first transplanting a (SuSE) Linux OS and network interface card drives, WiFi and ZigBee network send self network topology structure, the network health state, relevant informations such as Monitoring Data, after being transferred to ARM11 flush bonding processor control unit and handling by serial ports, show and receive the orders such as network management of user's key entry by touch-screen device interface control unit, or insert the user terminal that the Internet sends to a distant place by the internet interface control unit, whole system hard, software configuration is divided into three layers, the bottom be by the WiFi wireless communication module, the ZigBee wireless communication module, internet controller, the ARM11 processor, LCD, button, the hardware that SD card and USB interface are formed; The intermediate layer is to be made of (SuSE) Linux OS and hardware drive program, hardware driver package is drawn together WiFi module drive, ZigBee module drive, network interface card driving, serial port drive, LCD driving, button driving, USB driving, the driving of SD card etc., can realize the management of whole system hardware resource and software resource and the scheduling of each task well by (SuSE) Linux OS; By hardware driving such as network interface card, serial ports, provide the interface of operating each hardware of bottom to upper level applications, make upper level applications accomplish hardware independence; The superiors be application layer, comprise relevant informations such as network topology structure, network health state, Monitoring Data are handled, the demonstration of data receives the order that the user keys in, and utilizes ICP/IP protocol to the retransmission process of data etc. by the internet interface control unit.

Claims

1. a heterogeneous network interconnecting gateway equipment is characterized in that: be made up of WiFi radio transceiver unit (10), ZigBee radio transceiver unit (11), internet interface control unit (12), ARM11 flush bonding processor control unit (13), keystroke interface control unit (14), touch-screen device interface control unit (15), USB interface and SD card control unit (16);

Wherein WiFi radio transceiver unit, ZigBee radio transceiver unit, internet interface control unit, touch-screen device interface control unit, USB interface and SD card control unit respectively with two-way electrical connection of ARM11 flush bonding processor control unit; The keystroke interface control unit is connected with ARM11 flush bonding processor control unit unidirectional electrical.

2. heterogeneous network interconnecting gateway equipment according to claim 1, it is characterized in that: WiFi radio transceiver unit adopts the WM-G-MR-09 chip, ZigBee radio transceiver unit adopts the CC2530 chip, the internet interface control unit adopts the DM9000AE chip, ARM11 flush bonding processor control unit adopts the S3C6410 chip, and touch-screen device interface control unit adopts the AT043TN24V.1 chip.

3. heterogeneous network interconnecting gateway equipment according to claim 2, it is characterized in that: the 1st pin GND of WM-G-MR-09, the 3rd pin GND, the 8th pin GND ground connection, the 2nd pin ANT1 of WM-G-MR-09 connects inductance L 1, and inductance L 1 meets inductance L 2 and antenna F1, inductance L 2 ground connection; The 7th pin ECSn of WM-G-MR-09 is by resistance R 2 ground connection; The 9th pin VDD_HOST_IO of WM-G-MR-09 connects capacitor C 1 and 3.3V power supply, capacitor C 1 ground connection; The 4th pin ANT_SEL_P of WM-G-MR-09, the 6th pin SCLK, the 10th pin GPIO[6], the 11st pin GPIO[5], the 13rd pin GPIO[2], the 15th pin GPIO[4], the 29th pin BT_STATE, the 30th pin WL_ACTIVE, the 33rd pin BT_PRIORITY, the 34th pin GPIO[0] unsettled; The 16th pin GPIO[1 of WM-G-MR-09] negative terminal of sending and receiving optical diode D1, the anode of D1 connects the 3.3V power supply by resistance R 1; The 17th pin VDD1.8 of WM-G-MR-09 is by capacitor C 6 ground connection; The 18th pin VDD1.2 of WM-G-MR-09 is by capacitor C 7 ground connection; The 19th pin GND ground connection of WM-G-MR-09; The 23rd pin IF_SEL_1 of WM-G-MR-09 is by resistance R 3 ground connection; The 24th pin IF_SEL_2 of WM-G-MR-09 is by resistance R 4 ground connection; The 25th pin VDD1.8A of WM-G-MR-09 is by capacitor C 2, C8 ground connection; The 26th pin GND ground connection of WM-G-MR-09; The 27th pin VDD3.3 of WM-G-MR-09 connects capacitor C 3 and 3.3V power supply, capacitor C 3 ground connection; The 28th pin VDD3.3 of WM-G-MR-09 links to each other with the 27th pin VDD3.3 of WM-G-MR-09; The 20th pin SD_CMD/SPI_SDI of WM-G-MR-09, the 14th pin SD_CLK/SPI_CLK, the 21st pin SD_DAT[0]/SPI_SCSn, the 5th pin SD_DAT[1]/SPI_SDO, the 22nd pin SD_DAT[2]/SPI_SINTn, the 12nd pin SD_DAT[3], the 31st pin PDn, the 32nd pin RESETn respectively with the A16 pin X_MmcCMD1 of S3C6410, J11 pin X_MmcCLK1, H11 pin X_MmcDATA1_0, C17 pin X_MmcDATA1_1, B16 pin X_MmcDATA1_2, H10 pin X_MmcDATA1_3, C4 pin GPE2, B3 pin GPE1 links to each other; The 31st pin PDn connecting resistance R5 and the capacitor C 4 of WM-G-MR-09, resistance R 5 connects the 3.3V power supply, capacitor C 4 ground connection; The 32nd pin RESETn connecting resistance R6 and the capacitor C 5 of WM-G-MR-09, resistance R 6 connects the 3.3V power supply, capacitor C 5 ground connection.

4. heterogeneous network interconnecting gateway equipment according to claim 2, it is characterized in that: the B21 pin X_uTXD3 of S3C6410 links to each other with the 17th pin RX of CC2530, the J14 pin X_uRXD3 of S3C6410 links to each other with the 16th pin of CC2530, the 10th pin DVDD of CC2530, the 39th pin AVDD_DREG, the 21st pin AVDD5/AVDD_SOC, the 31st pin AVDD_GUARD connects the 3.3V power supply, and respectively by capacitor C 1, C4, C2, C3 ground connection, the 1st pin DGND_USB of CC2530, the 2nd pin USB_M, the 3rd pin USB_P, the equal ground connection of the 4th pin DVDD_USB, the 20th pin RESET_N connecting resistance R1 and the capacitor C 5 of CC2530, resistance R 1 connects the 3.3V power supply, capacitor C 5 ground connection, the 41st pin GND Exposed ground connection of CC2530, the 30th pin RBIAS of CC2530 is by resistance R 2 ground connection, the 25th pin RF_P of CC2530 connects inductance L 1 by C7, inductance L 2, capacitor C 11, inductance L 1 ground connection, the 26th pin RF_N of CC2530 connects inductance L 2 by capacitor C 8, inductance L 3, capacitor C 12, capacitor C 12 ground connection, inductance L 3 connects capacitor C 9, C10, C11, capacitor C 9 ground connection, capacitor C 10 connects antenna and capacitor C 17, capacitor C 17 ground connection, the 32nd pin P2.4/XOSC32_Q2 of CC2530, the 33rd pin P2.3/XOSC32_Q1 is respectively by capacitor C 16, capacitor C 15 ground connection, the 32nd pin P2.4/XOSC32_Q2 of CC2530, the 33rd pin P2.3/XOSC32_Q1 links to each other by crystal oscillator Y2, the 22nd pin XOSC_Q1 of CC2530, the 23rd pin XOSC_Q2 is respectively by capacitor C 14, capacitor C 13 ground connection, the 22nd pin XOSC_Q1 of CC2530, the 23rd pin XOSC_Q2 links to each other by crystal oscillator Y1, and the 40th pin of CC2530 is by capacitor C 6 ground connection.

5. heterogeneous network interconnecting gateway equipment according to claim 2, it is characterized in that: the AC19 pin X_EINT7 of S3C6410 meets the 34th pin INT of DM9000AE, the D1 pin Xm0_ADDR2 of S3C6410 meets the 32nd pin CMD of DM9000AE, the L4 pin Xm0_OEn of S3C6410 meets the 35 pin IOR# of DM9000AE, the J2 pin Xm0_WEn of S3C6410 meets the 36th pin IOW# of DM9000AE, the R3 pin Xm0_CSn1 of S3C6410 meets the 37 pin CS# of DM9000AE, the AD16 pin X_nRSTOUT of S3C6410 meets the 40 pin PWRST# of DM9000AE, the N2 pin Xm0_DATA0 of S3C6410, N1 pin Xm0_DATA1, M7 pin Xm0_DATA2, N3 pin Xm0_DATA3, M8 pin Xm0_DATA4, P2 pin Xm0_DATA5, N4 pin Xm0_DATA6, P3 pin Xm0_DATA7, M2 pin Xm0_DATA8, M4 pin Xm0_DATA9, L7 pin Xm0_DATA10, M3 pin Xm0_DATA11, L8 pin Xm0_DATA12, L2 pin Xm0_DATA13, K4 pin Xm0_DATA14, K1 pin Xm0_DATA15 respectively with the 18th pin SD0 of DM9000AE, the 17th pin SD1, the 16th pin SD2, the 14th pin SD3, the 13rd pin SD4, the 12nd pin SD5, the 11st pin SD6, the 10th pin SD7, the 31st pin SD8, the 29th pin SD9, the 28th pin SD10, the 27th pin SD11, the 26th pin SD12, the 25th pin SD13, the 24th pin SD14, the 22nd pin SD15 links to each other, the 43rd pin X2 of DM9000AE, the 41st pin X1 is respectively by capacitor C 1, C2 ground connection, the 43rd pin X2 of DM9000AE, the 41st pin X1 links to each other by crystal oscillator Y1, the 8th pin TX-of DM9000AE links to each other with the 2nd pin TD-of resistance R 1 and NET, the 7th pin TX+ of DM9000AE links to each other with the 1st pin TD+ of resistance R 2 and NET, the 4th pin RX-of DM9000AE links to each other with the 6th pin RX-of resistance R 3 and NET, the 3rd pin RX+ of DM9000AE links to each other with the 3rd pin RX+ of resistance R 4 and NET, resistance R 1 and electronics R2 link to each other with capacitor C 3, resistance R 3 and resistance R 4 link to each other with capacitor C 4, capacitor C 3, C4 ground connection, the 38th pin LED2 of DM9000AE links to each other with the 10th pin LEDG-of NET, the 39th pin LED1 of DM9000AE links to each other with the 11st pin LEDY-of NET, the 9th pin LEDG+ of NET, the 12nd pin LEDY+ connects the 3.3V power supply, the 8th pin CHS_GND ground connection of NET.