CN201830209U - Multipath differential compensation amplifying circuit suitable for high-orbit platforms - Google Patents
Multipath differential compensation amplifying circuit suitable for high-orbit platforms Download PDFInfo
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- CN201830209U CN201830209U CN2010205976741U CN201020597674U CN201830209U CN 201830209 U CN201830209 U CN 201830209U CN 2010205976741 U CN2010205976741 U CN 2010205976741U CN 201020597674 U CN201020597674 U CN 201020597674U CN 201830209 U CN201830209 U CN 201830209U
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- analog switch
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- amplifying circuit
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Abstract
The utility model relates to a multipath differential compensation amplifying circuit suitable for high-orbit platforms, which is used for centralized detection on the loop current of direct-current distribution systems and can realize the time division multiplexing detection of 60 paths of current at most. The while circuit consists of three main functional units: a check analogue switch combinational circuit, a sequential logic and address decoding circuit and a differential compensation amplifying circuit. The multipath differential compensation amplifying circuit is mainly applied to centralized detection on the loop current of the direct-current distribution systems in spacecrafts, and can be applied to other occasions with centralized time division amplifying of multipath electric signals.
Description
Technical field
The utility model relates to a kind of multichannel difference compensation amplifying circuit, is mainly used in the centralized detecting of spacecraft direct-flow distribution system loop line electric current, and the concentrated time-sharing multiplex that also can be used for other multi-channel electric signal amplifies.
Background technology
Along with the develop rapidly of space technology, spacecraft direct-flow distribution system scale constantly increases, and distribution branch road quantity constantly increases, because the characteristic requirement of space flight distribution system need take remote measurement to each branch current.Respectively the power current detecting of branch road of existing spacecraft distribution system, the patterns that adopt discrete detection more, every detection one road electric current all needs to be furnished with corresponding current/voltage signaling conversion circuit, signal amplification circuit, and then need provide power supply to these peripheral circuits.Cause whole current detection circuit system scale big, volume is big, and quality is big, takies a large amount of load, causes difficulty also for the circuit design of distribution system.
In order to simplify circuit volume, scale and the weight of spacecraft direct-flow distribution system, need carry out integrated design to major function circuit such as the control of distribution system, detection, remote measurements, improve each functional circuit performance and efficient, simplify the circuit volume and weight.
The utility model content
Technology of the present utility model is dealt with problems and is: overcome the deficiencies in the prior art, a kind of multichannel difference compensation amplifying circuit that is applicable to high rail platform is provided, the cumulative volume and the total weight of the current detection circuit of spacecraft distribution system have been reduced, the time-sharing multiplex that can realize maximum 60 road electric currents detects, and has the advantages that volume is little, in light weight, efficient is high, response speed is fast.
Technical solution of the present utility model is:
A kind of multichannel difference compensation amplifying circuit that is applicable to high rail platform, comprise: difference compensation amplifying circuit, sequential logic and address decoding circuitry and final election analog switch combinational circuit, wherein difference compensation amplifying circuit comprises differential amplifier circuit, error sampling hold circuit and analog switch again, and sequential logic and address decoding circuitry comprise address decoding circuitry and logic time-delay circuit; Logic time-delay circuit is delayed time the enable signal AN_EN of outside input, and the outside enable signal AN_EN of output and input reverse signal S/H give error sampling hold circuit and address decoding circuitry, and logic time-delay circuit is also exported the inversion signal of S/H simultaneously
Control end to the analog switch in the difference compensation amplifying circuit; Address decoding circuitry is given final election analog switch combinational circuit with the address signal decoding of input and output analog switch enable signal and analog switch address signal, final election analog switch combinational circuit receives the voltage signal of input and output signal is sent into the input of differential amplifier circuit, differential amplifier circuit is exported output signal, and simultaneously output signal being sent into the input of error sampling hold circuit, the compensation end REF of differential amplifier circuit is connected with ground with the output of error sampling hold circuit respectively by the analog switch in the difference compensation amplifying circuit.
It is the instrument amplifier chip of AD620 that described differential amplifier circuit adopts model.
It is the sampling holder chip of AD585 that described error sampling hold circuit adopts model.
It is the analog switch chip of HS-303 that described analog switch adopts model.
It is that 16 of HS-1840 selects 1 final election analog switch chip that described final election analog switch combinational circuit adopts model.
The utility model advantage compared with prior art is:
(1) the existing spacecraft distribution system current detecting of branch road of respectively powering, the patterns that adopt discrete detection more, every detection one road electric current is except that the current/voltage signaling conversion circuit of necessity, also are furnished with special-purpose signal amplification circuit and A/D translation circuit etc., and then also need to provide power supply to these circuit, taken a large amount of load of spacecraft.The utility model carries out integrated to the current detection circuit of spacecraft distribution system, concentrate and use same signal amplification circuit, is convenient to error compensation, improves precision, can finish maximum 60 tunnel loop line current concentration and detect; Only need output termination 1 road A/D translation circuit simultaneously at this circuit, and control circuit is simple, like this utility model can effectively simplify current detection circuit in the whole distribution system total scale, reduce the volume and weight of current detection circuit, improve the service efficiency and the performance of current detection circuit, thereby be applied to high rail platform more.
(2) the utility model adopts the design of systematic error real-time sampling compensation, all carries out primary system zero error originated from input compensation for calibrating errors before each road/time detection automatically.Compensating circuit is made of 1 sampling holder and 1 analog switch, the control of compensating circuit is finished by inner sequential logic and address circuit, do not need special external control, can pair amplifier zero partially and the temperature of circuit float equal error and carry out real-time sampling and compensation, effectively improved accuracy of detection.
(3) the utility model can utilize computer to pass through 8 bit address lines (AN_EN+Ext_BUS) this circuit is controlled, can realize in 60 road electric currents arbitrarily the road carry out the monitoring of random order.8 bit address signals are after the sequential logic and address decoding circuitry processing of circuit inside, generation is used for the enable signal and the address signal of inner each the functional unit control of circuit, entire timing logical AND address decoding circuitry is made of 3 basic door integrated circuit and other Resistor-Capacitor Units, and is simple in structure.
Description of drawings:
Fig. 1 is the utility model circuit diagram;
Fig. 2 is the utility model difference compensation amplifying circuit schematic diagram;
Fig. 3 is the utility model address decoding circuitry schematic diagram;
Fig. 4 is the utility model logic time-delay circuit schematic diagram;
Fig. 5 is the utility model final election analog switch combinational circuit schematic diagram;
Fig. 6 is the utility model external control signal and internal control signal logic timing figure.
Embodiment
A kind of multichannel difference compensation amplifying circuit that is applicable to high rail platform, its circuit structure sketch as shown in Figure 1, this circuit compensates amplifying circuit, sequential logic and address decoding circuitry by difference and 3 functional units of final election analog switch combinational circuit constitute.The physical circuit of difference compensation amplifying circuit is used for that input signal is carried out error compensation and amplifies as shown in Figure 2, and its internal circuit structure can be divided into differential amplifier circuit, error sampling hold circuit and analog switch 3 parts again; The differential amplifier circuit voltage signal of the input of runback modeling plan switch combination circuit in the future amplifies output, and simultaneously output signal is sent into the input of error sampling hold circuit, the compensation end REF of differential amplifier circuit by the single-pole double throw analog switch the different operating stage respectively with the output of error sampling hold circuit be connected with reference to ground.Sequential logic and address decoding circuitry comprise address decoding circuitry and logic time-delay circuit, and physical circuit figure sees Fig. 3 and Fig. 4 respectively; Logic time-delay circuit is delayed time the enable signal AN_EN of outside input, and output and AN_EN reverse enable signal S/H give error sampling hold circuit and address decoding circuitry, and logic time-delay circuit is also exported the enable signal reverse with S/H simultaneously
Control end to the analog switch in the difference compensation amplifying circuit; Address decoding circuitry with address signal (Ext_BUS) decoding of input and output analog switch enable signal (CS1～CS4) and analog switch address signal A[3..0] give final election analog switch combinational circuit.Final election analog switch combinational circuit is that 4 couples 16 1 couples 64 that select 1 analog switch to constitute select 1 analog switch, physical circuit as shown in Figure 5, this circuit receives the voltage signal of input and output signal is sent into the input of differential amplifier circuit.
What Fig. 6 provided is the logical sequence relation of the external control signal and the internal control signal of multichannel difference compensation amplifying circuit.Multichannel difference compensated amplifier is whenever finished one tunnel/time testing all will amplify two processes of output through systematic error sampling and error compensation, respectively time period Tc and the Ts in the corresponding diagram 6.
During the work of multichannel difference compensation amplifying circuit, the external control computer at first sends address signal Ext_BUS and enable signal AN_EN compensates amplifying circuit to the multichannel difference.Logic time-delay circuit is to the AN_EN Tc that delays time, between time delay, multichannel difference compensation amplifying circuit is in the systematic error sample states, at this moment: S/H forces address signal A[3..0] be changed to [1111], selected the 16th pin (the IN16 pin of U1 in the corresponding diagram 5～8, this pin ground connection during use) conducting of 1 analog switch by 16 of gating;
Drive the REF end ground connection that the single-pole double throw analog switch makes differential amplifier circuit, differential amplifier circuit is output as the systematic error under the input grounding condition; S/H also makes the error sampling hold circuit work in sample phase, and this error signal is sampled by the error sampling hold circuit.After time-delay was finished, multichannel difference compensation amplifying circuit entered error compensation and amplifies output services states (Ts), and at this moment: S/H reaches
The level upset, the error sampling hold circuit enters the maintenance output state, the REF end of differential amplifier circuit is connected with the output of error sampling hold circuit by analog switch, simultaneously, A[3..0] output is normally, the tested passage of final election analog switch combinational circuit gating, differential amplifier circuit output is through the amplifying signal of compensation of error, and entire circuit is finished one-time detection work.
The embodiment of each functional unit and working condition thereof are as follows in the circuit:
1) difference compensation amplifying circuit
Difference compensation amplifying circuit can be divided into differential amplifier circuit, error sampling hold circuit and analog switch 3 parts, and physical circuit figure sees Fig. 2.Differential amplifier circuit is directly realized with the instrument amplifier AD620 of AD company, is used for the processing and amplifying to measured signal, has the advantage of low noise, high cmrr; Also be connected with 7～8V voltage-stabiliser tube between the positive and negative input of AD620 and the power supply ground, be used for the overvoltage protection of AD620 input.The error sampling hold circuit directly uses the sampling holder AD585 of AD company to realize, the sampling magnifying state of error sampling hold circuit and the conversion of maintenance output state, and the enable signal S/H that is provided by logic time-delay circuit controls.Analog switch in the difference compensation amplifying circuit is the single-pole double throw analog switch, utilize in parallel realization of two-way among the 4 path analoging switch HS-303RH of Intersil company, two inputs of analog switch connect the output with reference to ground and AD585 respectively, the reference potential end REF of output termination AD620; The strobe state of HS-303RH is by enable signal
Control, the REF end that makes AD620 the Tc stage (
Be 0) ground connection, the Ts stage (
Be 1) connect error sampling hold circuit output;
The of short duration time-delay of S/H relatively, but delay time is much smaller than Tc.
The Tc stage (S/H is 1): the input of differential amplifier circuit AD620 is by final election analog switch combinational circuit ground connection, and the REF of AD620 end is by analog switch HS-303RH ground connection, and AD620 is output as the systematic error V under zero initial conditions
OffsetSimultaneously, error sampling hold circuit AD585 is to the zero error originated from input V of AD620 output
OffsetSample, and oppositely amplify 1 times of output-V
OffsetTs is during the stage: error sampling hold circuit AD585 enters the maintenance output state, keeps output voltage signal-V
OffsetThe input of AD620 is connected measured signal by the final election analog switch, and reference potential end REF meets the output-V of error sampling hold circuit by analog switch HS-303RH
Offset, the systematic error of output signal is compensated, finally finish the error compensation of measured signal and amplify output.Output signal Vout after the error compensation can express with following formula:
V
out＝(V
in×Gain+V
offset ＊)-V
offset
V
Offset *Be the systematic error in Ts stage, be similar to and think and V
OffsetEquate.The systematic error V of circuit
Offset *Mainly be by amplifier zero partially, the temperature of input impedance, final election switch leakage current and the circuit of filter circuit floats and causes, utilizes error compensation circuit, can eliminate this error substantially.Multichannel difference compensated amplifier whenever carries out 1 tunnel/time detection difference compensation amplifying circuit all can carry out the first-order error sampling again.
2) sequential logic and address decoding circuitry
Sequential logic and address decoding circuitry are made of address decoding circuitry (see figure 3) and logic time-delay circuit (see figure 4) two parts.
Address decoding circuitry is used for the processing of the 7 bit address signal Ext_BUS (ADD[6..0]) to outside input, and its core devices is 3/8 decoder (adopting the 54HC138 of T.I. company) and four tunnel OR circuit (CD4071 of employing T.I. company).Address signal ADD[6..4] be decoded into the enable signal CS1～CS4 of final election analog switch by 54HC138, be input to 4 pairs 16 Enable Pins of selecting 1 analog switch respectively, make the wherein gating of 1 pair of module switch, other shutoff.4 bit address signal ADD[3..0] send into or the input of door CD4071 the address signal A[3..0 of CD4071 output respectively with the S/H signal] be the passage gating address signal of analog switch, send into all and 16 select 1 analog switch.In the Tc stage, enable signal S/H is a high level, or the output A[3..0 of door CD4071] be forced to be changed to [1111], the 16th passage conducting (ground connection) of gating analog switch; Equal Input Address signal ADD[3..0 in Ts stage A [3..0]], the tested passage conducting of analog switch.
Logic time-delay circuit utilizes the NAND gate circuit CD4011 of company (adopt T.I.) that enable signal AN_EN is converted to reverse with it S/H signal, therebetween the RC delay circuit with the S/H signal by the flip-flop transition of 1-0 relative AN_EN by the upset time-delay Tc of 0-1; Also comprise a diode 1N4148 who is used for the delay capacitor discharge in the RC delay circuit, be used for the capacitor discharge of RC delay circuit, make the S/H signal follow the upset of AN_EN by 1-0 by the upset of 0-1.The S/H signal produces through the RC time-delay and oppositely once more
Be used for the break-make control of analog switch HS303RH.In the Tc stage, AN_EN is by 0-1, and S/H is still 1 owing to delay time,
Be 0; In the Ts stage, AN_EN remains 1, and S/H is by 1-0,
By 0-1; After single sense cycle Tw=Tc+Ts finished, it was 0 that AN_EN replys by 1, and S/H is by 0-1,
By 1-0.
3) final election analog switch combinational circuit
Final election analog switch combinational circuit (see figure 5) selects 1 final election analog switch (adopting the HS1840ARH of Intersil company) to constitute by 2 groups each 4 16, these 2 groups of switches constitute 1 64 respectively and select 1 final election analog switch, be symmetrical distribution on function and the structure, corresponding switch and passage thereof are by identical enable signal (CS1～CS4) and address (A[3..0]) control; These 2 groups of switches are respectively applied for the break-make control of current sense resistor two ends (high and low current potential) voltage signal to the positive and negative input of differential amplifier circuit AD620.
In the Tc stage, passage gating address signal A[3..0] be forced to be changed to 1111, by the 16th passage of CSx signal gating analog switch x (in the corresponding diagram 5 ± IN16, ± IN32, ± IN48, ± IN64) conducting, the equal ground connection of this passage during use is used for the systematic error (V under zero input state
Offset) sampling; In the Ts stage, passage gating address signal A[3..0] equal external address signal ADD[3..0], by the respective detection passage conducting of the analog switch x of CSx signal gating, the electric potential signal at tested current sense resistor two ends is admitted to the input of amplifier AD620, carry out processing and amplifying, AD620 output is finished measuring ability through the current detection signal of error compensation.
The content that is not described in detail in the utility model specification belongs to this area professional and technical personnel's known technology.
Claims (5)
1. a multichannel difference that is applicable to high rail platform compensates amplifying circuit, it is characterized in that comprising: difference compensation amplifying circuit, sequential logic and address decoding circuitry and final election analog switch combinational circuit, wherein difference compensation amplifying circuit comprises differential amplifier circuit, error sampling hold circuit and analog switch again, and sequential logic and address decoding circuitry comprise address decoding circuitry and logic time-delay circuit; Logic time-delay circuit is delayed time the enable signal AN_EN of outside input, and the outside enable signal AN_EN of output and input reverse signal S/H give error sampling hold circuit and address decoding circuitry, and logic time-delay circuit is also exported the inversion signal of S/H simultaneously
Control end to the analog switch in the difference compensation amplifying circuit; Address decoding circuitry is given final election analog switch combinational circuit with the address signal decoding of input and output analog switch enable signal and analog switch address signal, final election analog switch combinational circuit receives the voltage signal of input and output signal is sent into the input of differential amplifier circuit, differential amplifier circuit is exported output signal, and simultaneously output signal being sent into the input of error sampling hold circuit, the compensation end REF of differential amplifier circuit is connected with ground with the output of error sampling hold circuit respectively by the analog switch in the difference compensation amplifying circuit.
2. a kind of multichannel difference compensation amplifying circuit that is applicable to high rail platform according to claim 1, it is characterized in that: it is the instrument amplifier chip of AD620 that described differential amplifier circuit adopts model.
3. a kind of multichannel difference compensation amplifying circuit that is applicable to high rail platform according to claim 1, it is characterized in that: it is the sampling holder chip of AD585 that described error sampling hold circuit adopts model.
4. a kind of multichannel difference compensation amplifying circuit that is applicable to high rail platform according to claim 1, it is characterized in that: it is the analog switch chip of HS-303 that described analog switch adopts model.
5. a kind of multichannel difference compensation amplifying circuit that is applicable to high rail platform according to claim 1, it is characterized in that: it is that 16 of HS-1840 selects 1 final election analog switch chip that described final election analog switch combinational circuit adopts model.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205976741U CN201830209U (en) | 2010-11-04 | 2010-11-04 | Multipath differential compensation amplifying circuit suitable for high-orbit platforms |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205976741U CN201830209U (en) | 2010-11-04 | 2010-11-04 | Multipath differential compensation amplifying circuit suitable for high-orbit platforms |
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| CN201830209U true CN201830209U (en) | 2011-05-11 |
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| CN2010205976741U Expired - Lifetime CN201830209U (en) | 2010-11-04 | 2010-11-04 | Multipath differential compensation amplifying circuit suitable for high-orbit platforms |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103118196A (en) * | 2013-02-04 | 2013-05-22 | 厦门亿联网络技术股份有限公司 | Signal conversion device capable of realizing various talk modes |
| CN103368512A (en) * | 2013-07-10 | 2013-10-23 | 深圳市航天新源科技有限公司 | Multichannel differential amplification circuit and accuracy compensation method thereof |
| CN109842414A (en) * | 2017-11-27 | 2019-06-04 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of working method of analog collection system and the system |
-
2010
- 2010-11-04 CN CN2010205976741U patent/CN201830209U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103118196A (en) * | 2013-02-04 | 2013-05-22 | 厦门亿联网络技术股份有限公司 | Signal conversion device capable of realizing various talk modes |
| CN103118196B (en) * | 2013-02-04 | 2014-10-22 | 厦门亿联网络技术股份有限公司 | Signal conversion device capable of realizing various talk modes |
| CN103368512A (en) * | 2013-07-10 | 2013-10-23 | 深圳市航天新源科技有限公司 | Multichannel differential amplification circuit and accuracy compensation method thereof |
| CN103368512B (en) * | 2013-07-10 | 2017-06-06 | 深圳市航天新源科技有限公司 | A kind of multichannel differential amplifier circuit and its precision compensation method |
| CN109842414A (en) * | 2017-11-27 | 2019-06-04 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of working method of analog collection system and the system |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110511 |