CN201820221U - Expansion circuit used for I/O interface of single chip microcomputer - Google Patents
Expansion circuit used for I/O interface of single chip microcomputer Download PDFInfo
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- CN201820221U CN201820221U CN2010205667786U CN201020566778U CN201820221U CN 201820221 U CN201820221 U CN 201820221U CN 2010205667786 U CN2010205667786 U CN 2010205667786U CN 201020566778 U CN201020566778 U CN 201020566778U CN 201820221 U CN201820221 U CN 201820221U
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Abstract
The utility model relates to an expansion circuit used for I/O interfaces of a single chip microcomputer, comprising a single chip microcomputer MCU and an integrated chip D, five I/O ports INY0, INY1, INY2, INY3, and INY4 of the single chip microcomputer MCU are respectively connected with ports D1, D2, D3, and D4 disposed on several integrated chips, an I/O port of the single chip microcomputer MCU is respectively connected with an STB port disposed on the integrated chip D, three I/O ports addrA, addrB, and addrC of the single chip microcomputer MCU are respectively connected with an addrA port, an addrB port, and an addrC port disposed on the integrated chip D to work as address lines of the integrate chip D, a D0 port, the D1port, the D2 port, the D3 port, the D4 port, a D5 port, a D6 port, and a D7 port respectively disposed on the integrated chip D are respectively connected with external signals. The expansion circuit for an I/O interface is characterized in that: the I/O interface of the single chip microcomputer is expanded. Three-bit address signals are used to realize logical control of eight input ports. ternary output function is realized; parallel input and output function of external signals is realized. Further expansion can be performed, possession of 64 I/O interfaces are realized, and three-bit address line is expanded, forming bit choice of 64 I/O interfaces.
Description
Technical field
The utility model relates to a kind of I/O interface expanded circuit that is used for single-chip microcomputer.
Background technology
Along with the development of singlechip technology, single-chip microcomputer in the application of electronic product and industrial control field more and more widely.On the one hand, wish that the embedded system function of single-chip microcomputer formation is powerful as far as possible, processing power is strong, and controlling object is many; On the one hand, wish that again the cost of total system is low as far as possible in addition, promptly cost performance is good.Therefore, can run into the not enough situation of single-chip processor i/o interface resource in the practical application.In some complicated application systems, because controlled device is more, as control a plurality of LED charactrons demonstrations, surpass the demonstration of 30 line states etc., at this moment, the port imbalance between supply and demand is especially outstanding.
Summary of the invention
In view of the situation that prior art exists, the utility model provides the I/O interface expanded circuit of the single-chip microcomputer that a kind of SN54LS251 of employing integrated chip expands the single-chip processor i/o interface.
The utility model for achieving the above object, the technical scheme of being taked is: 1, a kind of I/O interface expanded circuit of single-chip microcomputer, it is characterized in that: comprise single-chip microprocessor MCU, integrated chip D, five I/O port INY0 of described single-chip microprocessor MCU, INY1, INY2, INY3, the port D1 that INY4 is provided with the several piece integrated chip respectively, D2, D3, D4 connects, the I/O port STB of single-chip microprocessor MCU is connected with the STB port that several piece integrated chip D is provided with respectively, three I/O port addrA of single-chip microprocessor MCU, addrB, the addrA port that addrC is provided with several piece integrated chip D respectively, the addrB port, the addrC port connects the address wire as integrated chip D, the D0 port that is respectively equipped with on the several piece integrated chip D, the D1 port, the D2 port, the D3 mouth, the D4 port, the D5 port, the D6 port, the D7 port links to each other with external signal respectively.
Characteristics of the present utility model are: the I/O interface of 1, having expanded single-chip microcomputer.2, with the logic control of 3 bit address signals realization to 8 input ports.3, realized ternary output function.4, can utilize the input of identical address line by connecting a plurality of SN54LS251 integrated chips, realize the parallel input/output function of external signal.5, expand to 35 I/O interfaces by 9 I/O interfaces on the single-chip microcomputer.6, can carry out the expansion in a nearlyer step, expand to 8 SN54LS251 integrated chips, realize having 64 I/O interfaces, expand 3 bit address lines simultaneously, form the position of 64 I/O interfaces is selected.
Description of drawings
Fig. 1 is the utility model I/O interface Extended Principle Diagram.
Fig. 2 is the utility model SN54LS251 integrated chip truth table.
Embodiment
After utilizing SN54LS251 integrated chip D that the I/O interface of C8051F020 single-chip microprocessor MCU is expanded as shown in Figure 1, draw 5 I/O ports (pin) INY0 from single-chip microprocessor MCU, INY1, INY2, INY3, INY4 is connected respectively to the D0 port that several piece integrated chip D is provided with, the D1 port, the D2 port, the D3 port, the D4 port, the I/O port STB of single-chip microprocessor MCU is connected with the STB port that several piece integrated chip D is provided with respectively, draw three I/O ports (pin) addrA from single-chip microprocessor MCU again, addrB, addrC is as address selection line, be connected respectively to the addrA port that several piece integrated chip D is provided with, the addrB port, the addrC port, the D0 port that is respectively equipped with on the several piece integrated chip D, the D1 port, the D2 port, the D3 mouth, the D4 port, the D5 port, the D6 port, the D7 port links to each other with external signal respectively.The several piece integrated chip is five.
The method of selecting IO interface is shown in following integrated chip truth table, pass through addrA, addrB, the different input values of addrC are selected different IO interface, common address wire has connected 5 SN54LS251 integrated chips, after the address is selected to determine, have the operation that 5 interface concurrents carry out input and output, realized the expansion of I/O interface.
Claims (2)
1. the I/O interface expanded circuit of a single-chip microcomputer, it is characterized in that: comprise single-chip microprocessor MCU, integrated chip D, five I/O port INY0 of described single-chip microprocessor MCU, INY1, INY2, INY3, the port D1 that INY4 is provided with the several piece integrated chip respectively, D2, D3, D4 connects, the I/O port STB of single-chip microprocessor MCU is connected with the STB port that several piece integrated chip D is provided with respectively, three I/O port addrA of single-chip microprocessor MCU, addrB, the addrA port that addrC is provided with several piece integrated chip D respectively, the addrB port, the addrC port connects the address wire as integrated chip D, the D0 port that is respectively equipped with on the several piece integrated chip D, the D1 port, the D2 port, the D3 mouth, the D4 port, the D5 port, the D6 port, the D7 port links to each other with external signal respectively.
2. the I/O interface expanded circuit of single-chip microcomputer according to claim 1, it is characterized in that: several piece integrated chip D is five.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205667786U CN201820221U (en) | 2010-10-19 | 2010-10-19 | Expansion circuit used for I/O interface of single chip microcomputer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205667786U CN201820221U (en) | 2010-10-19 | 2010-10-19 | Expansion circuit used for I/O interface of single chip microcomputer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201820221U true CN201820221U (en) | 2011-05-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010205667786U Expired - Fee Related CN201820221U (en) | 2010-10-19 | 2010-10-19 | Expansion circuit used for I/O interface of single chip microcomputer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201820221U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110568790A (en) * | 2019-08-30 | 2019-12-13 | 珠海格力电器股份有限公司 | Address extension circuit and air conditioning unit |
-
2010
- 2010-10-19 CN CN2010205667786U patent/CN201820221U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110568790A (en) * | 2019-08-30 | 2019-12-13 | 珠海格力电器股份有限公司 | Address extension circuit and air conditioning unit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110504 Termination date: 20131019 |