CN201805409U - Reset circuit of FPGA system - Google Patents
Reset circuit of FPGA system Download PDFInfo
- Publication number
- CN201805409U CN201805409U CN2010205296536U CN201020529653U CN201805409U CN 201805409 U CN201805409 U CN 201805409U CN 2010205296536 U CN2010205296536 U CN 2010205296536U CN 201020529653 U CN201020529653 U CN 201020529653U CN 201805409 U CN201805409 U CN 201805409U
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- resets
- reset
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Abstract
The embodiment of the utility model discloses a reset circuit of a FPGA (Field Programmable Gate Array) system, and relates to the field of integrated circuits, which realizes the reliable resetting of the system and the stability improvement of the reset system. The reset circuit comprises a reset chip and a reset branch connected with a manual control reset pin of the reset chip; and the reset branch produces low level signals, so as to control the reset chip to produce low level signals serving as reset signals of the system. The reset circuit is applied to integrated circuits.
Description
Technical field
The utility model relates to integrated circuit fields, relates in particular to the reset circuit of a kind of field programmable gate array (Field-Programmable Gate Array is hereinafter to be referred as FPGA) system.
Background technology
FPGA occurs as a kind of semi-custom circuit in application-specific integrated circuit (ASIC) (ASIC) field, has both solved the deficiency of custom circuit, has overcome the limited shortcoming of original programming device gate circuit number again.
In the FPGA system design, the inventor finds that mostly the reset circuit that prior art provides is that simple switch ground connection drags down, and causes system's shakiness easily, and on the one hand, imperfect earth appears in simple ground connection easily, does not have reset response; On the other hand, simple touchdown speed is very fast, and static is introduced and caused electric current excessive, can cause damage to the FPGA system.
The utility model content
Technical problem to be solved in the utility model is to provide the reset circuit of a kind of FPGA system, realizes the reliable reset of system, has improved the stability of the back system that resets.
For solving the problems of the technologies described above, the reset circuit of the utility model FPGA system adopts following technical scheme:
The reset circuit of a kind of FPGA system, comprise: chip and the branch road that resets that is connected with the manual reset pin of the described chip that resets reset, the described branch road that resets produces low level signal, thereby controls the described low level signal of chip generation as systematic reset signal that reset.
The described branch road that resets comprises:
First resistance, one end connected system operating supply voltage output, the other end connects the manual reset pin of the described chip that resets;
First diode, described first resistance of its anodal connection, negative pole is by switch ground connection.
Described switch is a touch-switch.
Also comprise: be used for the detection loop of detection system operating supply voltage, comprise: power-fail detects the input branch road and power-fail detects the output branch road,
Described power-fail detects an end connected system operating supply voltage output of input branch road, and the power-fail that the other end connects the described chip that resets detects input pin;
The power-fail that described power-fail detects the described chip that resets of end connection of output branch road detects output pin, and the other end connects the manual reset pin of the described chip that resets,
Wherein, to detect the system power supply operating voltage low excessively when described power-fail detects the input branch road, make be input to voltage that described power-fail detects input pin be lower than the reset coil film gate ration the power supply press after, detect output pin output low level signal by described power-fail, thereby control the manual reset pin output low level signal that described power-fail detects the described chip that resets of output Zhi Luxiang.
Described power-fail detects the input branch road and comprises:
Second resistance, the one end connects the system power supply operating voltage output of the described chip that resets, and the power-fail that the other end connects the described chip that resets detects input pin;
The power-fail that second resistance, one end connect described first resistance and the described chip that resets detects input pin, other end ground connection.
Described power-fail detects the output branch road and comprises:
Second diode, its anodal power-fail that connects the described chip that resets detects output pin, and negative pole connects described manual reset pin and described first resistance.
Also comprise: be used for showing the indication branch road that effectively resets that resets, the described indication branch road that resets comprises:
Light-emitting diode, its anodal high level reseting pin that connects the described chip that resets, minus earth.
The described indicating circuit that resets also comprises:
The 4th resistance, the one end connects the high level reseting pin of the described chip that resets, and the other end connects described light-emitting diode.
Also comprise: the power filter branch road comprises: inductance, first electric capacity and second electric capacity,
Described inductance, the one end connects the system power supply operating voltage output of the described chip that resets, and the other end connects the voltage input pin of the described chip that resets, described first electric capacity and described second electric capacity respectively;
Described first electric capacity, one end connect the voltage input pin of described inductance and the described chip that resets, other end ground connection respectively;
Described second electric capacity, one end connect the voltage input pin of described inductance and the described chip that resets, other end ground connection respectively.
The low level reseting pin of the described chip that resets is by the 5th grounding through resistance.
In the technical scheme of present embodiment, reset chip and peripheral circuit thereof of employing controlled, and each signal all will successively produce according to sequential in the chip that resets, the problem that produces in the time of simple ground connection therefore can not occurring, this reset circuit is more reliable, has improved the stability of the back system that resets.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, the accompanying drawing of required use is done to introduce simply in will describing embodiment below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the utility model FPGA system reset proof procedure schematic diagram;
Fig. 2 is the reset circuit structural representation of the utility model FPGA system.
Embodiment
The utility model embodiment provides the reset circuit of a kind of FPGA system, realizes the reliable reset of system, has improved the stability of the back system that resets.
Be described in detail below in conjunction with the reset circuit of accompanying drawing the utility model embodiment F PGA system.
Owing to will in the system of FPGA platform building, carry out functional verification at the chip functions modular design initial stage.The circuit code code may occur and run disorderly when moving in PFGA, therefore the state of endless loop, need provide a reset circuit, and system is resetted.
Particularly, as shown in Figure 1, certain functional module code is poured in the FPGA system, if working properly, system promptly can the authentication function module.But if the situation of operation irregularity just needs the external reset circuit that system is resetted.The external reset circuit can produce (Reset) signal that resets, the FPGA platform need reserve an IO mouth therewith signal communicate.After this IO mouth received the Reset signal, system was reset, and the functional module checking is carried out in initialization then again.
The utility model embodiment provides the reset circuit of a kind of FPGA system, and as shown in Figure 2, this reset circuit comprises: reset chip U and the peripheral circuit that is connected with this chip U that resets, and wherein, each functions of pins of chip U that resets is as follows:
/ MR (Manual Reset Input) (1 pin): manual reset pin.Low level is effective.When this pin senses when voltage is low level, the chip U that resets will produce (RESET) signal that resets.
VCC (2 pin): voltage input pin.Be used to provide the operating voltage of chip of resetting.
GND (3 pin): ground pin.
PFI (4 pin): power-fail detects input pin PFI.This pin voltage input compares with the normal voltage of the chip U builtin voltage comparator that resets, and when input voltage was lower than inner comparative voltage ,/PFO will output low level.
/ PFO (5 pin): power-fail detects output pin.Low level is effective.
/ RESET (7 pin): high level reseting pin.High level is effective.
RESET (8 pin): low level reseting pin.Low level is effective.
The peripheral circuit of chip U of resetting comprises at least: the branch road that resets that is connected with manual reset pin/MR, and the described branch road that resets produces low level signal, chip U produces the low level signal as systematic reset signal thereby control resets.
Particularly, this branch road that resets comprises: first resistance R 5 and the first diode VD2,
Wherein, first resistance R 5, one end connected system operating supply voltage output Vcc, the other end connects manual reset pin/MR of the chip U that resets; The first diode VD2, described first resistance R 5 of its anodal connection, negative pole is by switch SW K1 ground connection.
As shown in Figure 2, in the present embodiment, the chip U that resets can adopt the chip that resets (IC_RST).The concrete operations that reset are: Push switch SWK1, make its ground connection, at this moment, the first diode VD2 conducting, wherein, the second diode VD1 can prevent the static introducing, and 1 pin/MR is a low level, after the chip U that resets receives the low level of 1 pin/MR, will produce of reset signal (sys_RESET) output of a low level from 8 pin RESET as the PFGA system.The IO mouth of reserving in the FPGA system will carry out system reset after receiving the sys_RESET signal.
In the technical scheme of present embodiment, reset chip and peripheral circuit thereof of employing controlled, and each signal all will successively produce according to sequential in the chip that resets, the problem that produces in the time of simple ground connection therefore can not occurring, this reset circuit is more reliable, has improved the stability of the back system that resets.
Further, above-mentioned switch SW K1 can be touch-switch.Touch-switch is simple to operate.
Again further, whether all right detection system operating supply voltage of the reset circuit that present embodiment provides is low excessively, then this reset circuit also comprises: be used for the detection loop of detection system operating supply voltage, comprise: power-fail detects the input branch road and power-fail detects the output branch road.
Particularly, power-fail detects an end connected system operating supply voltage output Vcc of input branch road, and the power-fail that the other end connects this chip U that resets detects input pin PFI; Power-fail detects power-fail detection output pin/PFO that an end of exporting branch road connects the chip U that resets, and the other end connects manual reset pin/MR of the chip U that resets;
Wherein, to detect the system power supply operating voltage low excessively when power-fail detects the input branch road, make be input to voltage that power-fail detects input pin PFI be lower than the reset coil film gate ration the power supply press after, detect output pin/PFO output low level signal by described power-fail, detect the described manual reset pin of output Zhi Luxiang/MR output low level signal thereby control described power-fail.
Particularly, described power-fail detection input branch road comprises: second resistance R 1 and second resistance R 1.
Described power-fail detects the output branch road and comprises: the second diode VD1, and its anodal power-fail that connects the chip U that resets detects output pin/PFO, and negative pole connects the manual reset pin/MR and first resistance R 5 of the chip U that resets.
As shown in Figure 2, when carrying out the detection of system power supply operating voltage, the voltage of 4 pin PFI is obtained system power supply operating voltage Vcc dividing potential drop by second resistance R 1 and the 3rd resistance R 2, R1, and the resistance of R2 will be calculated coupling according to the chip internal comparator normal voltage that resets of concrete use.
When system power supply operating voltage VCC brownout make the voltage of 4 pin PFI be lower than the reset coil film gate ration the power supply press after, 5 pin/PFO will export a low level signal, at this moment, the second diode VD1 conducting, 1 pin/MR also can be dragged down, then 8 pin RESET produce a low level signal, export as systematic reset signal (sys_RESET).
Again further, this reset circuit also comprises: be used for showing the indication branch road that effectively resets that resets, the described indication branch road that resets comprises:
Light-emitting diode VD3, its anodal high level reseting pin/RESET that connects the chip U that resets, minus earth.Produce a low level at 8 pin RESET, when exporting as the reset signal (sys_RESET) of PFGA system, 7 pin/RESET can produce a high level, makes this LED lamp of the 3rd diode VD3 luminous, this time resets effectively in order to show.
Further, this indication branch road that resets also comprises: the 4th resistance R 3, and the one end connects the high level reseting pin/RESET of the described chip that resets, and the other end connects described light-emitting diode VD3.The 4th resistance R 3 is a current-limiting resistance, plays the effect of current-limiting protection.
Further, this reset circuit also comprises: be used for the power filter branch road of filtering, comprise: inductance L, first capacitor C 1 and second capacitor C 2.
Inductance L, one end connected system operating supply voltage output Vcc, the other end connects the voltage input pin Vcc of the described chip U that resets, described first capacitor C 1 and described second capacitor C 2 respectively; First capacitor C 1, one end connect described inductance L and described voltage input pin Vcc, other end ground connection respectively; Second capacitor C 2, one end connect described inductance L and described voltage input pin Vcc, other end ground connection respectively.
Further, the low level reseting pin RESET of the described chip U that resets is by the 5th resistance R 4 ground connection.The 5th resistance R 4 is a current-limiting resistance, plays the effect of current-limiting protection.
In the technical scheme of present embodiment, by employing reset chip and peripheral circuit thereof, being embodied as the FPGA system provides the detection of reset signal and system power supply operating voltage, each signal all will successively produce according to sequential in the chip owing to reset, therefore the problem that produces in the time of simple ground connection can not occurring, this reset circuit is more reliable, has improved the stability of the back system that resets.
The above; it only is embodiment of the present utility model; but protection range of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; can expect easily changing or replacing, all should be encompassed within the protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of described claim.
Claims (10)
1. the reset circuit of a field programmable gate array system, it is characterized in that, comprise: chip and the branch road that resets that is connected with the manual reset pin of the described chip that resets reset, the described branch road that resets produces low level signal, thereby controls the described low level signal of chip generation as systematic reset signal that reset.
2. reset circuit according to claim 1 is characterized in that, the described branch road that resets comprises:
First resistance, one end connected system operating supply voltage output, the other end connects the manual reset pin of the described chip that resets;
First diode, described first resistance of its anodal connection, negative pole is by switch ground connection.
3. reset circuit according to claim 2 is characterized in that, described switch is a touch-switch.
4. reset circuit according to claim 2 is characterized in that, also comprises: be used for the detection loop of detection system operating supply voltage, comprise: power-fail detects the input branch road and power-fail detects the output branch road,
Described power-fail detects an end connected system operating supply voltage output of input branch road, and the power-fail that the other end connects the described chip that resets detects input pin;
The power-fail that described power-fail detects the described chip that resets of end connection of output branch road detects output pin, and the other end connects the manual reset pin of the described chip that resets,
Wherein, to detect the system power supply operating voltage low excessively when described power-fail detects the input branch road, make be input to voltage that described power-fail detects input pin be lower than the reset coil film gate ration the power supply press after, detect output pin output low level signal by described power-fail, thereby control the manual reset pin output low level signal that described power-fail detects the described chip that resets of output Zhi Luxiang.
5. reset circuit according to claim 4 is characterized in that, described power-fail detects the input branch road and comprises:
Second resistance, the one end connects the system power supply operating voltage output of the described chip that resets, and the power-fail that the other end connects the described chip that resets detects input pin;
The power-fail that second resistance, one end connect described first resistance and the described chip that resets detects input pin, other end ground connection.
6. reset circuit according to claim 4 is characterized in that, described power-fail detects the output branch road and comprises:
Second diode, its anodal power-fail that connects the described chip that resets detects output pin, and negative pole connects described manual reset pin and described first resistance.
7. according to the described reset circuit of the arbitrary claim of claim 1-6, it is characterized in that, also comprise: be used for showing the indication branch road that effectively resets that resets, the described indication branch road that resets comprises:
Light-emitting diode, its anodal high level reseting pin that connects the described chip that resets, minus earth.
8. reset circuit according to claim 7 is characterized in that, the described indicating circuit that resets also comprises:
The 4th resistance, the one end connects the high level reseting pin of the described chip that resets, and the other end connects described light-emitting diode.
9. reset circuit according to claim 8 is characterized in that, also comprises: the power filter branch road comprises: inductance, first electric capacity and second electric capacity,
Described inductance, the one end connects the system power supply operating voltage output of the described chip that resets, and the other end connects the voltage input pin of the described chip that resets, described first electric capacity and described second electric capacity respectively;
Described first electric capacity, one end connect the voltage input pin of described inductance and the described chip that resets, other end ground connection respectively;
Described second electric capacity, one end connect the voltage input pin of described inductance and the described chip that resets, other end ground connection respectively.
10. reset circuit according to claim 9 is characterized in that, the low level reseting pin of the described chip that resets is by the 5th grounding through resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205296536U CN201805409U (en) | 2010-09-15 | 2010-09-15 | Reset circuit of FPGA system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205296536U CN201805409U (en) | 2010-09-15 | 2010-09-15 | Reset circuit of FPGA system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201805409U true CN201805409U (en) | 2011-04-20 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010205296536U Expired - Fee Related CN201805409U (en) | 2010-09-15 | 2010-09-15 | Reset circuit of FPGA system |
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| CN (1) | CN201805409U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102868387A (en) * | 2012-09-12 | 2013-01-09 | 广东欧珀移动通信有限公司 | Level jump reset IC (integrated circuit) design circuit |
| CN111585555A (en) * | 2020-05-22 | 2020-08-25 | 广东电网有限责任公司 | Anti-oscillation circuit and method and intelligent terminal |
-
2010
- 2010-09-15 CN CN2010205296536U patent/CN201805409U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102868387A (en) * | 2012-09-12 | 2013-01-09 | 广东欧珀移动通信有限公司 | Level jump reset IC (integrated circuit) design circuit |
| CN102868387B (en) * | 2012-09-12 | 2015-09-30 | 广东欧珀移动通信有限公司 | A kind of level saltus step reset IC design circuit |
| CN111585555A (en) * | 2020-05-22 | 2020-08-25 | 广东电网有限责任公司 | Anti-oscillation circuit and method and intelligent terminal |
| CN111585555B (en) * | 2020-05-22 | 2023-11-28 | 广东电网有限责任公司 | Anti-vibration circuit, method and intelligent terminal |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110420 Termination date: 20190915 |
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| CF01 | Termination of patent right due to non-payment of annual fee |