CN201804864U - Power device packaging structure - Google Patents

Power device packaging structure Download PDF

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Publication number
CN201804864U
CN201804864U CN2010201868288U CN201020186828U CN201804864U CN 201804864 U CN201804864 U CN 201804864U CN 2010201868288 U CN2010201868288 U CN 2010201868288U CN 201020186828 U CN201020186828 U CN 201020186828U CN 201804864 U CN201804864 U CN 201804864U
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CN
China
Prior art keywords
chip
electrically
backing plate
power device
conductive backing
Prior art date
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Expired - Lifetime
Application number
CN2010201868288U
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Chinese (zh)
Inventor
梁平镇
张文雁
田晓宇
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BYD Co Ltd
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BYD Co Ltd
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Publication date
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Priority to CN2010201868288U priority Critical patent/CN201804864U/en
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Publication of CN201804864U publication Critical patent/CN201804864U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model provides a power device packaging structure, and belongs to the field of integrated chip packaging. The packaging structure structurally comprises a first conductive substrate, a second conductive substrate electrically connected with the first conductive substrate, a first chip and a second chip, wherein the second conductive substrate is positioned above the first conductive substrate; the first chip is positioned on the surface of the first conductive substrate adjacent to the second conductive substrate, and is electrically connected with the first conductive substrate; and the second chip is positioned on the surface of the second conductive substrate nonadjacent to the first conductive substrate, and is electrically connected with the second conductive substrate. According to the utility model, the first chip and the second chip can be separated by the second conductive substrate skillfully, and the chip structures can be adhered on the effective areas of the substrates effectively, thereby achieving the purpose of outputting larger rated current.

Description

A kind of power device encapsulating structure
Technical field
The utility model belongs to the integrated chip encapsulation field, relates in particular to a kind of power device encapsulating structure.
Background technology
Existing power device packing forms mainly is single-chip package and the flat encapsulation of multicore sheet.The single-chip package structure comprises as shown in Figure 1: substrate 10, and described substrate 10 is provided with first pin one 01; First chip 11 is bonded on described substrate 10 centers with adhesive, and described adhesive has conductive characteristic, and chip signal output is drawn from first pin one 01; First lead 14 is drawn the output signal of chip 11 from second pin one 2; Second lead 15 is drawn the output signal of chip 11 from three-prong 13; The moulding of last mould envelope.The flat encapsulating structure of multicore sheet comprises as shown in Figure 2: substrate 20, and described substrate 20 is provided with first pin two 01; First chip 21 is bonded in described substrate 20 1 sides with adhesive; Second chip 22 is bonded in described substrate 20 opposite sides side by side with adhesive, and described adhesive has conductive characteristic, and first chip 21, second chip, 22 output signals are drawn from first pin two 01; First lead 25 is drawn the output signal of first chip 21, second chip 22 from second pin two 3; Second lead 26 is drawn the output signal of first chip 21, second chip 22 from three-prong 24; The moulding of last mould envelope.
The described single-chip package structure of Fig. 1 is subjected to the restriction of wafer manufacturing process, allows the load current value that passes through limited, and it is very difficult further to improve its load current value, and cost is higher.The flat encapsulation of the described multicore sheet of Fig. 2, load current value can reach requirement, but structural volume is big, the packaging cost height.
The utility model content
The utility model provides the power device that a kind of encapsulation volume is little, load current value is big encapsulating structure for solving the less technical problem of load current value in the existing power device encapsulating structure.
A kind of power device encapsulating structure comprises:
First electrically-conductive backing plate, second electrically-conductive backing plate that is electrically connected with first electrically-conductive backing plate, first chip, second chip;
Described second electrically-conductive backing plate is positioned at first electrically-conductive backing plate top;
Described first chip is positioned on the first electrically-conductive backing plate surface adjacent with second electrically-conductive backing plate, and is electrically connected with first electrically-conductive backing plate;
Described second chip be positioned at the non-conterminous second electrically-conductive backing plate surface of first electrically-conductive backing plate on, and be electrically connected with second electrically-conductive backing plate.
Further preferred, described first electrically-conductive backing plate is provided with first pin.
Further preferred, described power device encapsulating structure also comprises: be used to export first chip, second pin of second chip signal, three-prong.
Further preferred, described power device encapsulating structure also comprises: first lead, described first chip, second chip signal output are drawn from second pin; Second lead is drawn described first chip, second chip signal output from three-prong.
Further preferred, described power device encapsulating structure also comprises: be used for fixing the plastic packaging shell of first pin, second pin and protective core chip system, described plastic packaging shell is positioned at first electrically-conductive backing plate chip side is set.
Further preferred, the face that described second electrically-conductive backing plate is relative with first chip is provided with cavity, and first chip is positioned at this cavity.
Further preferred, described power device is a metal-oxide-semiconductor.
Further preferred, described power device is the IGBT pipe.
Ingenious second electrically-conductive backing plate that utilizes of the utility model power device encapsulating structure separates first chip, second chip, pastes chip structure on first electrically-conductive backing plate of limited area, reaches the bigger purpose of output rated current.
Description of drawings
Fig. 1 is the single-chip package structural representation that prior art provides;
Fig. 2 is the flat encapsulating structure schematic diagram of multicore sheet that prior art provides;
Fig. 3 is the power device encapsulating structure decomposing schematic representation that the utility model provides;
Fig. 4 is the power device encapsulating structure decomposing schematic representation that the utility model provides;
Fig. 5 is the power device encapsulating structure decomposing schematic representation that the utility model provides;
Fig. 6 is the power device encapsulating structure schematic diagram that the utility model provides.
Embodiment
Clearer for technical problem, technical scheme and beneficial effect that the utility model is solved, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
A kind of power device encapsulating structure as shown in Figure 6, comprising: first electrically-conductive backing plate 30, first pin 301, first chip 31, second pin 32, three-prong 33, second electrically-conductive backing plate 34, second chip 35, first lead 36, second lead 37.
As shown in Figure 3, described first electrically-conductive backing plate 30 is provided with first pin 301; Described first chip 31 is positioned at described first electrically-conductive backing plate, 30 1 sides, is electrically connected with first electrically-conductive backing plate 30; Described second pin 32, three-prong 33 temporarily are fixed on first electrically-conductive backing plate 30.
As shown in Figure 4, second electrically-conductive backing plate 34 sticks on described first electrically-conductive backing plate, 30 opposite sides and cover part first chip 31, is electrically connected with first electrically-conductive backing plate 30.Reserve a part of first chip 31 surfaces, be convenient to drawing of first chip 31 holding wires.
As shown in Figure 5, described second chip 35 is positioned on described second electrically-conductive backing plate 34, is electrically connected with second electrically-conductive backing plate 34.
As shown in Figure 6, first lead 36 is drawn described first chip 31, second chip, 35 output signals from second pin 32; Second lead 37 is drawn described first chip 31, second chip, 35 output signals from three-prong 33.
Preferred version; described power device encapsulating structure also comprises the plastic packaging shell that is used for fixing second pin 32, three-prong 33 and protective core chip system; described plastic packaging shell is positioned at first electrically-conductive backing plate 30 chip side is set; fix second pin 32, three-prong 33, chip system is isolated from the outside.
Preferred version, the face that described second electrically-conductive backing plate 34 is relative with first chip 31 is provided with cavity, and first chip 31 is positioned at this cavity.Make 31 of second electrically-conductive backing plate 34 and first chips reserve certain interval, first chip 31 does not contact with second electrically-conductive backing plate 34.
Preferred version, described power device are metal-oxide-semiconductor.
Preferred version, described power device are the IGBT pipe.
The utility model power device encapsulating structure utilizes second electrically-conductive backing plate 33 that first chip 32, second chip 34 are separated cleverly, pastes chip structure on effective first electrically-conductive backing plate, 30 areas, reaches the bigger purpose of output rated current.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.

Claims (8)

1. power device encapsulating structure is characterized in that: comprising:
First electrically-conductive backing plate, second electrically-conductive backing plate that is electrically connected with first electrically-conductive backing plate, first chip, second chip;
Described second electrically-conductive backing plate is positioned at first electrically-conductive backing plate top;
Described first chip is positioned on the first electrically-conductive backing plate surface adjacent with second electrically-conductive backing plate, and is electrically connected with first electrically-conductive backing plate;
Described second chip be positioned at the non-conterminous second electrically-conductive backing plate surface of first electrically-conductive backing plate on, and be electrically connected with second electrically-conductive backing plate.
2. power device encapsulating structure as claimed in claim 1 is characterized in that: described first electrically-conductive backing plate is provided with first pin.
3. power device encapsulating structure as claimed in claim 2 is characterized in that: described power device encapsulating structure also comprises: be used to export first chip, second pin of second chip signal, three-prong.
4. power device encapsulating structure as claimed in claim 3 is characterized in that: described power device encapsulating structure also comprises:
First lead is drawn the output signal of described first chip, second chip from described second pin;
Second lead is drawn the output signal of described first chip, second chip from described three-prong.
5. as each described power device encapsulating structure of claim 1 to 4; it is characterized in that: described power device encapsulating structure also comprises: be used for fixing the plastic packaging shell of second pin, three-prong and protective core chip system, described plastic packaging shell is positioned at first electrically-conductive backing plate chip side is set.
6. as each described power device encapsulating structure of claim 1 to 4, it is characterized in that: the face that described second electrically-conductive backing plate is relative with first chip is provided with cavity, and first chip is positioned at this cavity.
7. as each described power device encapsulating structure of claim 1 to 4, it is characterized in that: described power device is a metal-oxide-semiconductor.
8. as each described power device encapsulating structure of claim 1 to 4, it is characterized in that: described power device is the IGBT pipe.
CN2010201868288U 2010-04-30 2010-04-30 Power device packaging structure Expired - Lifetime CN201804864U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4261878A1 (en) * 2022-04-13 2023-10-18 Infineon Technologies Austria AG Multi-chip device with gate redistribution structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4261878A1 (en) * 2022-04-13 2023-10-18 Infineon Technologies Austria AG Multi-chip device with gate redistribution structure

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