CN201804106U

CN201804106U - Novel answer probability tester

Info

Publication number: CN201804106U
Application number: CN2010205035004U
Authority: CN
Inventors: 任宏伟
Original assignee: Tianjin 764 Communication and Navigation Technology Corp
Current assignee: Tianjin 764 Communication and Navigation Technology Corp
Priority date: 2010-08-25
Filing date: 2010-08-25
Publication date: 2011-04-20
Anticipated expiration: 2020-08-25

Abstract

The utility model relates to a set of aviation distance measuring equipment, and particularly to a novel answer probability tester. The tester comprises a test circuit which is embedded into a test box body. The test circuit comprises the following components: a single chip microcomputer, a crystal oscillator, and a field programmable gate array FPGA which is composed of the following components: a frequency divider, a time delay unit, a coded pulse generator A, a coded pulse generator B, a selector, a time-delay and gate forming circuit and a counter, wherein, the utility model is characterized in that: the single chip microcomputer is respectively connected with the time delay unit, the coded pulse generator A, the coded pulse generator B, the selector, the time-delay and gate forming circuit of the filed programmable gate array FPGA; the single chip microcomputer is connected with a PC machine; and the crystal oscillator is connected with the frequency divider of the field programmable gate array FPGA. The tester can simultaneously provide two inquiry signals and can randomly control front and back positions of two signals and a distance therebetween. The indexes such as distant echo restriction, near echo restriction, 8us recovery time and decoding performance can be measured thereby satisfying the requirement of the DME equipment to the testing instrument.

Description

Novel answer probabilistic testing instrument

Technical field

The utility model relates to airborne range equipment, relates in particular to a kind of novel answer probabilistic testing instrument.

Background technology

Answering the probabilistic testing instrument is the special test equipment of shoran platform (TACAN) and airborne range equipment (DME).It matches with standard signal generator, is used for measuring the sensitivity of Tacan earth station or DME receiver and answers probability.Present answer probabilistic testing instrument can only provide one road interrogating signal, is used for measuring receiver and answers probability, can not satisfy DME equipment to distant echo suppress, near echo suppresses, the test request of 8us release time, decoding performance index.

Summary of the invention

In view of above-mentioned prior art situation, the purpose of this utility model provides a kind of novel answer probabilistic testing instrument.This novel answer probabilistic testing instrument adopts on-site programmable gate array FPGA+single-chip microcomputer framework, simultaneously, with PC that single-chip microcomputer is connected on testing software is installed, can satisfy and realize of the requirement of DME equipment to testing tool.

The technical scheme that the utility model is taked for achieving the above object is: a kind of novel answer probabilistic testing instrument, it comprises the test circuit that is embedded in the test box body, it is characterized in that: test circuit comprises single-chip microcomputer, crystal oscillator and by frequency divider, chronotron, coded pulse generator A, coded pulse generator B, selector switch, time-delay and door form the on-site programmable gate array FPGA that the circuit sum counter constitutes, wherein: single-chip microcomputer respectively with the chronotron of on-site programmable gate array FPGA, coded pulse generator A, coded pulse generator B, selector switch, time-delay and door form circuit and are connected, single-chip microcomputer is connected with PC, and crystal oscillator is connected with the frequency divider of on-site programmable gate array FPGA.

The beneficial effect that the utility model produced is: this tester can provide the two-way interrogating signal simultaneously, and can arbitrarily control the front and back position and the distance of two signals, can measure that distant echo suppresses, near echo suppresses, indexs such as 8us release time, decoding performance.Thereby satisfy of the requirement of DME equipment to testing tool.

Description of drawings

Fig. 1 is the utility model circuit catenation principle block diagram.

Fig. 2 is that the utility model front panel interface is provided with synoptic diagram.

Fig. 3 is the utility model and external unit connection diagram.

Fig. 4 is that the utility model testing software is at PC interface display synoptic diagram.

Embodiment

The utility model is described in further detail below in conjunction with accompanying drawing.

With reference to Fig. 1, novel answer probabilistic testing instrument comprises the test circuit that is inlaid in the testing cassete, test circuit comprises single-chip microcomputer, crystal oscillator and by frequency divider, chronotron, coded pulse generator A, coded pulse generator B, selector switch, time-delay and door form the on-site programmable gate array FPGA that the circuit sum counter constitutes, wherein: single-chip microcomputer respectively with the chronotron of on-site programmable gate array FPGA, coded pulse generator A, coded pulse generator B, selector switch, time-delay and door form circuit and are connected, single-chip microcomputer is connected with PC, and crystal oscillator is connected with the frequency divider of on-site programmable gate array FPGA.

Above device function is as follows:

Single-chip microcomputer: the control core of entire circuit is used for and the outer PC communication, and finishes measuring task.

Frequency divider: the quantity of control debugging pulse signal, can be by the single-chip microcomputer setting.

Coded pulse generator A: produce modulated pulse signal, can be set the recurrent interval by single-chip microcomputer.

Coded pulse generator B: produce modulated pulse signal, can be set the recurrent interval, in practice, generally lag behind the modulated pulse signal that coded pulse generator A produces by single-chip microcomputer.

Chronotron: control coded pulse generator B falls behind the time of coded pulse generator A, can be by the single-chip microcomputer setting.

Selector switch: select to determine normal interrogating signal and disturbing pulse signal according to test event.Time-delay and door form circuit: produce and lag behind normal interrogation pulse signals 50 μ s (X pattern), the 4 μ pulses of 56 μ s (Y mode).

Counter: the output number of measuring reply pulse.

The on-site programmable gate array FPGA model is EP1C12Q24017N, and the single-chip microcomputer model is AT89S8253.

As seen in Figure 1, if form the pulse matching that circuit produces with time-delay and door in time, can think that then this pulse is a recall signal from the coded pulse signal of DME main frame.It is the answer probability of DME equipment that the umber of pulse that counter records produces the interrogation pulse number divided by the coded pulse generator.

Answer the probabilistic testing instrument and adopt FPGA+ single-chip microcomputer framework, single-chip microcomputer is finished the serial communication with PC, with control to whole test circuit, utilize the FPGA device to make up frequency divider, chronotron, coded pulse generator, selector switch, counter, time-delay and door and form circuit, finish communication with single-chip microcomputer by data bus and address bus (bold arrow among Fig. 1).Wherein, circuit such as the frequency divider of FPGA inside, chronotron, coded pulse generator, selector switch, counter, time-delay and door formation utilize VHDL language to write, and customization is strong, and debugging flexibly, conveniently.Single-chip microcomputer utilizes the C language compilation, realizes the control to whole test system.

With reference to Fig. 2, the front panel of testing cassete is provided with and is used for the counting input end mouth, recall signal port, modulation signal A port, modulation signal B port, encoder port like those shown, power port and the serial ports that are connected with external unit.

Counting input end mouth: institute's test signal is connected to go forward side by side horizontal pulse counting of this port.

The recall signal port: the recall signal output port is connected to the counting input end mouth and counts.

Modulation signal A port: the modulating pulse output port, the output modulating pulse is to (normal interrogating signal).

Modulation signal B port: the modulating pulse output port, the output modulating pulse is to (undesired signal).

Encoder port like those shown: coded signal input port.

Power port :+5V power supply side mouth.

Serial ports: with the computing machine PORT COM.

With reference to Fig. 3 and Fig. 4, this tester connects external meters, and testing software can be installed in the standard PC, cooperates novel answer probabilistic testing instrument to finish test assignment jointly.By PC answer probabilistic testing instrument parameter and test event are set, signal source frequency, amplitude are transferred to desirable value, modulation system strobe pulse external modulation.According to the answer probability numbers of screen display, cooperate and adjust signal source measurement respective item.The detailed programs measuring method is referring to " DME900 detailed technology index and method of testing ".

User interface is very friendly, and the left side, interface is used to be provided with the pattern and the speed of computing machine communication serial ports, interrogation pulse for the hurdle is set.The right side is a test interface, is divided into the test of receiver performance test and decoding performance, choose corresponding test event after, click the beginning testing button, test result can be presented in the digital display box above the right side.

The utility model principle of work: answer the probabilistic testing instrument and produce the two-way modulated pulse signal, one the tunnel is used to simulate normal aircraft interrogating signal, another road is used for simulaed interference signal, this two paths of signals is respectively by after the signal source modulation, send into DME equipment as test signal through combiner, the coded signal of DME equipment output takes back tester, tester is by built-in counter, recall signal in the circuit extraction coded signals such as chronotron, and recall signal counted, pass test result back PC by serial ports and show.

Claims

1. novel answer probabilistic testing instrument, it comprises the test circuit that is inlaid in the testing cassete, it is characterized in that: test circuit comprises single-chip microcomputer, crystal oscillator and by frequency divider, chronotron, coded pulse generator A, coded pulse generator B, selector switch, time-delay and door form the on-site programmable gate array FPGA that the circuit sum counter constitutes, wherein: single-chip microcomputer respectively with the chronotron of on-site programmable gate array FPGA, coded pulse generator A, coded pulse generator B, selector switch, time-delay and door form circuit and are connected, single-chip microcomputer is connected with PC, and crystal oscillator is connected with the frequency divider of on-site programmable gate array FPGA.

2. novel answer probabilistic testing instrument according to claim 1 is characterized in that: the front panel of testing cassete is provided with and is used for the counting input end mouth, recall signal port, modulation signal A port, modulation signal B port, encoder port like those shown, power port and the serial ports that are connected with external unit.