CN203596805U

CN203596805U - Timing signal simulator

Info

Publication number: CN203596805U
Application number: CN201320696993.1U
Authority: CN
Inventors: 李本任; 夏全国; 黄平华; 刘奎永; 孙朝江; 刘少伟; 黄士亮; 马康; 郭小溪; 严东
Original assignee: PLA 92941 ARMY
Current assignee: PLA 92941 ARMY
Priority date: 2013-11-05
Filing date: 2013-11-05
Publication date: 2014-05-14
Anticipated expiration: 2023-11-05

Abstract

The utility model provides a timing signal simulator with simple control, convenient operation, good real-time performance, low fault rate, low cost and high precision. The circuit comprises a clock circuit used for generating internal clock signals, a frequency dividing circuit used for converting the internal clock signals into clock signals with different frequency grades and a frequency grading output circuit used for outputting one selected from the clock signals with different frequency grades. The frequency grading output circuit provides uniform clock signals for at least two test systems. The beneficial effects of the device are that, the device has advantages of simple control, convenient operation, good real-time performance, low cost, low fault rate and high precision; the measurement accuracy and the dynamic recurrence precision of the whole system are raised during test devices of multiple systems carries out collection tests at the same time.

Description

Timing Signal analogue means

Technical field

The utility model belongs to physical simulation ship sway controlling test field of measuring technique.Particularly relate to a kind of Timing Signal analogue means that is applied to simulation test stand.

Background technology

Timing Signal analogue means---be the Timing Signal analogue means that sends data for gathering in the same time in large ship simulation test device system multichannel measuring and controlling equipment system.He provides dynamic load to wave position tracking measurement data to gather in the same time the clock of transmission, guarantees closed loop and the kinetic measurement parameter reproducibility accurately of system.

The data acquisition of carrying out measuring system be debugged or be tested to past simulation test device can only by single system, in large ship simulation test device, be that multiloop loop system is measured, there is no unified clock signal in debug process time, can not guarantee large system dynamic tracking measurement data, make whole system closed loop complete test.Timing Signal analogue means---provide unified clock in the time that multisystem is tested, to receive in the same time or send measurement image data, guarantee that multisystem data acquisition in the same time makes system dynamic measuring data accurate.

Summary of the invention

The problems referred to above that the utility model exists for prior art, provide a kind of control simple, easy to operate, real-time is good, failure rate and cost low, the Timing Signal analogue means that precision is high.

Goal of the invention of the present utility model realizes by following scheme: Timing Signal analogue means, comprise for generation of the clock circuit of internal clock signal, for internal clock signal being converted to the frequency dividing circuit of different frequency grade clock signal, for different frequency grade clock signal being selected to the frequency stepping output circuit of an output, frequency stepping output circuit provides unified clock signal for two-way pilot system at least.

Further, described frequency stepping output circuit output is also connected with one for regulating the monostable trigger-action circuit of internal clock signal duty ratio.

Further, monostable trigger-action circuit output separates at least three tunnels by the pilot system Timing Signal of drive circuit and difference channel output, and first via difference Timing Signal is connected with comprehensive control system input; Two-pass DINSAR Timing Signal is connected with simulation TT&C system input; Third Road difference Timing Signal is connected with check system input.

Further, monostable trigger-action circuit output is also exported Si road Timing Signal by drive circuit and TTL circuit to tilter angle measuring system.

Further, also comprise a choice device that internal clock signal and outside timing system signal are united in the time that tilter angle measuring system is selected the inside/outside of output.

Further, outside timing system system comprises outside timing system signal receiving circuit and difference channel, and the outside timing system signal of difference channel output one of the choice device input of uniting during with inside/outside by drive circuit and TTL circuit is connected.

Further, described outside timing system clock signal is taken from gps signal.

Further, frequency dividing circuit frequency division grade at least comprises 1Hz, 10Hz, 2Hz, 50Hz, five grades of 100Hz.

Further, monostable trigger-action circuit comprises one-shot multivibrator 74LS123 and peripheral circuit.

Further, each road clock signal is introduced pilot system by shielding conductor.

The beneficial effects of the utility model are: Timing Signal analogue means---in the time of large ship simulation test device single channel, the debugging of multichannel TT&C system, provide Timing Signal to replace gps signal for gathering in the same time transmission data, guarantee the closed loop of system and kinetic measurement parameter accurately, while guaranteeing finally to adopt GPS regulator signal in the time that large ship multisystem emulator test once successfully.Have control simple, easy to operate, real-time is good, the feature of cost and failure rate is low, and at multiloop loop system testing equipment in the same time when acquisition test, has improved whole system certainty of measurement and dynamic reproducibility.

Accompanying drawing explanation

Fig. 1 is circuit block diagram of the present utility model.

Embodiment

Below in conjunction with specific embodiments and the drawings, the utility model is described in further detail:

Shown in Fig. 1, Timing Signal analogue means of the present utility model, comprise for generation of the clock circuit of internal clock signal, for internal clock signal being converted to the frequency dividing circuit of different frequency grade clock signal, for different frequency grade clock signal being selected to the frequency stepping output circuit of an output, frequency stepping output circuit provides unified clock signal for two-way pilot system at least.Frequency stepping output circuit output is also connected with one for regulating the monostable trigger-action circuit of internal clock signal duty ratio.

Monostable trigger-action circuit output separates at least three tunnels by the pilot system Timing Signal of drive circuit and difference channel output, and first via difference Timing Signal is connected with comprehensive control system input, i.e. XX1 end; Two-pass DINSAR Timing Signal is connected with simulation TT&C system input, i.e. XX2 end; Third Road difference Timing Signal is connected with check system input, i.e. XX3 end.Monostable trigger-action circuit output is also exported Si road Timing Signal by drive circuit and TTL circuit to tilter angle measuring system, i.e. H/YBT end.This device also comprises a choice device that internal clock signal and outside timing system signal are united in the time that tilter angle measuring system is selected the inside/outside of output.

Outside timing system system comprises outside timing system signal receiving circuit and difference channel, and the outside timing system signal of difference channel output one of the choice device input of uniting during with inside/outside by drive circuit and TTL circuit is connected.Described outside timing system clock signal is taken from gps signal.Simplify circuit for adapting to the merging of various test sites, frequency dividing circuit frequency division grade at least comprises 1Hz, 10Hz, 2Hz, 50Hz, five grades of 100Hz as far as possible.

The monostable trigger-action circuit that the present embodiment adopts comprises one-shot multivibrator 74LS123 and peripheral circuit.For improving interference free performance, each road clock signal is introduced pilot system by shielding conductor.

Principle, the key of circuit is, to the clock adjustment of frequency division and pulse duration accurately, if adopt conventional frequency divider, to need various frequency dividing circuit circuit compared with very complicated.The design adopts two four decimal systems of medium scale integrated circuit 74LS390 and binary counter as divider, realizes the output of multi-frequency signal through drive circuit, difference channel, greatly simplifies circuit structure.Pulse width regulating circuit adopts retriggerable one-shot multivibrator 74LS123, and sort circuit is by selecting its external definition resistance and capacitance to determine output pulse width.

Although the utility model illustrates and describes by reference to preferred embodiment, but those of ordinary skills should understand, can be not limited to the description of the present embodiment, in the scope of claims, can make the various variations in form and details.

Claims

1. Timing Signal analogue means, it is characterized in that comprising for generation of the clock circuit of internal clock signal, for internal clock signal being converted to the frequency dividing circuit of different frequency grade clock signal, for different frequency grade clock signal being selected to the frequency stepping output circuit of an output, frequency stepping output circuit provides unified clock signal for two-way pilot system at least.

2. Timing Signal analogue means according to claim 1, is characterized in that: described frequency stepping output circuit output is also connected with one for regulating the monostable trigger-action circuit of internal clock signal duty ratio.

3. Timing Signal analogue means according to claim 2, it is characterized in that: monostable trigger-action circuit output separates at least three tunnels by the pilot system Timing Signal of drive circuit and difference channel output, and first via difference Timing Signal is connected with comprehensive control system input; Two-pass DINSAR Timing Signal is connected with simulation TT&C system input; Third Road difference Timing Signal is connected with check system input.

4. Timing Signal analogue means according to claim 3, is characterized in that: monostable trigger-action circuit output is also exported Si road Timing Signal by drive circuit and TTL circuit to tilter angle measuring system.

5. Timing Signal analogue means according to claim 4, is characterized in that: also comprise a choice device that internal clock signal and outside timing system signal are united in the time that tilter angle measuring system is selected the inside/outside of output.

6. Timing Signal analogue means according to claim 5, it is characterized in that: outside timing system system comprises outside timing system signal receiving circuit and difference channel, the outside timing system signal of difference channel output one of the choice device input of uniting during with inside/outside by drive circuit and TTL circuit is connected.

7. Timing Signal analogue means according to claim 6, is characterized in that: described outside timing system clock signal is taken from gps signal.

8. according to the Timing Signal analogue means described in claim 1 to 7 any one, it is characterized in that: frequency dividing circuit frequency division grade at least comprises 1Hz, 10Hz, 2Hz, 50Hz, five grades of 100Hz.

9. according to the Timing Signal analogue means described in claim 1 to 7 any one, it is characterized in that: monostable trigger-action circuit comprises one-shot multivibrator 74LS123 and peripheral circuit.

10. according to the Timing Signal analogue means described in claim 1 to 7 any one, it is characterized in that: each road clock signal is introduced pilot system by shielding conductor.