CN106199540A - A kind of Secondary Surveillance Radar Signal Simulator based on FPGA design device - Google Patents
A kind of Secondary Surveillance Radar Signal Simulator based on FPGA design device Download PDFInfo
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- CN106199540A CN106199540A CN201610473261.4A CN201610473261A CN106199540A CN 106199540 A CN106199540 A CN 106199540A CN 201610473261 A CN201610473261 A CN 201610473261A CN 106199540 A CN106199540 A CN 106199540A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
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- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention discloses a kind of Secondary Surveillance Radar Signal Simulator based on FPGA design device, including data acquisition subsystem plate and control panel, described control panel left end connects radar return detector, described data acquisition subsystem plate includes subsystem memory, the input of described subsystem memory connects pulse-generating circuit, described pulse-generating circuit is connected with trigger signal controller by fixing cable, in described trigger signal controller, surface-mounted integrated circuit is installed, the left end of described surface-mounted integrated circuit is provided with multiple sample clock frequency: primary for clock frequency detector, the outfan of described clock frequency detector connects embedded computer, the outfan of described embedded computer connects signal conditioning circuit；Being provided with digital signal processor and flush bonding processor in described control panel, the communication data port of described digital signal processor is connected with flush bonding processor by RS232 communication interface.
Description
Technical field
The present invention relates to signal simulator design field, a kind of secondary radar signals based on FPGA is simulated
Device design device.
Background technology
Increasingly sophisticated along with radar system, traditional direct analyzing method cannot meet demand, and computer
Performance is continuously available raising, provides the condition of necessity to radar simulation technology.Carry out radar simulation with computer, not only economy but also
Flexibly, use radar simulation technology that radar is simulated, repeatable high, can repeatedly simulate same in the case of the property of radar
Can, it is simple to analyzing, why real time radar signal imitation is capable of, in that the property that the radar signal received is had
Matter, it practice, these radar signals may be considered by transmitted waveform reproduction waveform institute after time delay and Doppler frequency shift
Constituting, the full detail content of radar environments is all to exist as the modulation of transmitted waveform.Here it is radar simulation is able to
The main theoretical basis of the reform of Chinese economic structure realized, the core of radar simulation is to set up radar target signal and the scattering of various noise signal, biography
Broadcast the model of characteristic, but be as developing rapidly of sub-interference and anti-ECM technique, make how to test and assess and assess electronic interferences with
Counter-measure effect also becomes a difficult problem, causes modern radar system the most complicated, and the direct analysis method of general employing is entered
It is relatively difficult that row processes, and financial resources, material resources and radar simulation method that general outfield experiments is spent are by comparison
Surprising.
Summary of the invention
For problem above, the invention provides a kind of Secondary Surveillance Radar Signal Simulator based on FPGA design device, logical
Cross and data acquisition subsystem plate is set, use coherent video simulation, it is possible to reappear realistically and not only comprise amplitude but also comprise phase
Position coherent video, reappear this signal transmitting, spatial transmission, be scattered body reflection and carry out in receiver
The overall process processed, and coherent video make use of the phase place of signal, it contain radar environments whole for information about,
As long as the elementary object provided and environmental model are the best, so that it may so that the precision of coherent video simulation is the highest, permissible
Effectively solve the problem in background technology.
For achieving the above object, the present invention provides following technical scheme: a kind of secondary radar signals based on FPGA is simulated
Device design device, including data acquisition subsystem plate and control panel, described control panel left end connect have liquid crystal display and
Radar return detector, described data acquisition subsystem plate includes subsystem memory, the input of described subsystem memory
Connecting has pulse-generating circuit, described pulse-generating circuit to be connected with trigger signal controller by fixing cable, described tactile
Being provided with surface-mounted integrated circuit in signalling controller, the left end of described surface-mounted integrated circuit is provided with multiple sample clock frequency: just
Level is clock frequency detector, and the outfan of described clock frequency detector connects embedded computer, described embedded meter
The outfan of calculation machine connects signal conditioning circuit, and the outfan of described signal conditioning circuit connects simulation single-chip microcomputer；Described
Digital signal processor and flush bonding processor, the communication data port of described digital signal processor are installed in control panel
Being connected with flush bonding processor by RS232 communication interface, flush bonding processor connects data storage and serial communication
Module.
As a kind of preferably technical scheme of the present invention, the input of described signalling controller and pulse-generating circuit
Outfan is connected, and the outfan of pulse-generating circuit is also connected with waveshape detector.
As a kind of preferably technical scheme of the present invention, described embedded computer includes Human-machine Control interface and industrial computer
Interface monitor, the control end at described Human-machine Control interface is connected to flush bonding processor, described industrial computer interface by cable
Monitor connects miniature video camera head driver.
As a kind of preferably technical scheme of the present invention, described radar return detector includes constant-current amplifier, described perseverance
The outfan of stream amplifier connects high pass filter, and the outfan of described high pass filter connects analog-digital converter.
As a kind of preferably technical scheme of the present invention, the input of described simulation single-chip microcomputer and the output of high pass filter
End is connected, and described high pass filter uses the digital filter with FPGA as control core.
As a kind of preferably technical scheme of the present invention, the outfan of described simulation single-chip microcomputer connects has wireless data to send
Device, described wireless receiver and flush bonding processor carry out data communication.
As a kind of preferably technical scheme of the present invention, described serial communication modular includes RJ45 network adapter, RJ45
The outfan of network adapter connects cpci bus interface, and the outfan of described cpci bus interface connects receiver.
As a kind of preferably technical scheme of the present invention, described flush bonding processor uses the ARM11 series of STM32 kernel
Single-chip microcomputer, described digital signal processor uses the process chip of TIC66X series, and described data storage uses DDR2 storage
Device, described subsystem memory uses the SRAM cache district of internal system.
Compared with prior art, the invention has the beneficial effects as follows: should Secondary Surveillance Radar Signal Simulator based on FPGA design
Device, by arranging data acquisition subsystem plate, uses coherent video simulation, it is possible to reappear realistically not only comprise amplitude but also
Comprise the coherent video of phase place, reappear this signal transmitting, spatial transmission, be scattered body reflection and at receiver
Inside carrying out the overall process processed, and coherent video make use of the phase place of signal, it contains the whole of radar environments has
Pass information, as long as the elementary object provided and environmental model are the best, so that it may so that the precision of coherent video simulation is very
Height, and use radar return detector, sometimes can be under conditions of actual radar system front end possess, after radar system
Level signal processing is debugged and is tested, and it provides easily and effectively to the design and analysis of radar system and performance test
Instrument.
Accompanying drawing explanation
Fig. 1 is present configuration schematic diagram；
Fig. 2 is present system frame structure schematic diagram.
In figure: 1-data acquisition subsystem plate；2-control panel；3-LCDs；4-radar return detector；5-
System storage；6-pulse-generating circuit；7-trigger signal controller；8-surface-mounted integrated circuit；9-clock frequency detector；10-
Embedded computer；11-signal conditioning circuit；12-simulates single-chip microcomputer；13-DSP digital processing unit；14-flush bonding processor；
15-data storage；16-RS232 communication interface；17-serial communication modular；18-waveshape detector；19-Human-machine Control interface；
20-industrial computer interface monitor；21-constant-current amplifier；22-high pass filter；23-analog-digital converter；24-minisize pick-up head drives
Dynamic device；25-RJ45 network adapter；26-CPCI EBI；27-receiver；28-wireless receiver.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
Embodiment:
Referring to Fig. 1 and Fig. 2, the present invention provides a kind of technical scheme: a kind of secondary radar signals based on FPGA is simulated
Device design device, including data acquisition subsystem plate 1 and control panel 2, described control panel 2 left end connects liquid crystal display
3 and radar return detector 4, described radar return detector 4 includes constant-current amplifier 21, the output of described constant-current amplifier 21
End connection has high pass filter 22, and the outfan of described high pass filter 22 connects analog-digital converter 23, described data acquisition
Subsystem plate 1 includes that subsystem memory 5, subsystem memory 5 mainly gather radar echo signal when triggering signal and arriving,
And store, radar return can be produced, for signal processor according to the unlimited simulation of the running parameter of radar after storage
Exploitation debugging uses, and the input of described subsystem memory 5 connects pulse-generating circuit 6, and described pulse-generating circuit 6 leads to
Cross fixing cable to be connected with trigger signal controller 7, the input of described trigger signal controller 7 and pulse-generating circuit 6
Outfan be connected, the outfan of pulse-generating circuit 6 is also connected with waveshape detector 18, described trigger signal controller
Being provided with surface-mounted integrated circuit 8 in 7, the left end of described surface-mounted integrated circuit 8 is provided with multiple sample clock frequency: clock frequency when primary is
Rate detector 9, the outfan of described clock frequency detector 9 connects embedded computer 10, described embedded computer 10
Including Human-machine Control interface 19 and industrial computer interface monitor 20, industrial computer sends command parameter by PCI to acquisition subsystem,
Acquisition subsystem starts to gather radar echo signal, transfers data to signal processing subsystem by LVDS, and industrial computer passes through
PCI sends command parameter, and signal processing subsystem passes through the good data of PCI transmission process to industrial computer imaging of interface, described people
Machine controls the control end at interface 19 and is connected to flush bonding processor 14 by cable, and described industrial computer interface monitor 20 connects to be had
Miniature video camera head driver 24, the outfan of described embedded computer 10 connects signal conditioning circuit 11, and described signal is adjusted
The outfan of reason circuit 11 connects simulation single-chip microcomputer 12, and the input of described simulation single-chip microcomputer 12 is defeated with high pass filter 22
Going out end to be connected, described high pass filter 22 uses the digital filter with FPGA as control core, described simulation single-chip microcomputer 12
Outfan connect and have a wireless data transmitter 28, described wireless receiver 28 and flush bonding processor 14 carry out data and lead to
Letter；Digital signal processor 13 and flush bonding processor 14, described digital signal processor 13 are installed in described control panel 2
Communication data port be connected with flush bonding processor 14 by RS232 communication interface 16, described flush bonding processor 14 is adopted
With the ARM11 series monolithic of STM32 kernel, described digital signal processor 13 uses the process chip of TIC66X series, institute
Stating data storage 15 uses DDR2 memorizer, described subsystem memory 5 to use the SRAM cache district of internal system, and
Flush bonding processor 14 connects has data storage 15 and serial communication modular 17, described serial communication modular 17 to include RJ45 net
Network adapter 25, the outfan of RJ45 network adapter 25 connects cpci bus interface 26, described cpci bus interface 26
Outfan connects receiver 27.
The command control word that the cpci bus interface module of the present invention is mainly inputted by CPCI interface according to single board computer,
Radio-frequency (RF) switch in each up-converter module and up-converter module is led to by the radiofrequency signal of input by controlling logical block
Disconnected setting, thus produce the radio frequency letter of respective frequencies.
The acquisition subsystem of the present invention gathers radar echo signal under conditions of supply triggers signal and sampling clock, adopts
The echo-signal of collection can be transferred to signal processing subsystem and carry out imaging, it is also possible to is transferred to storage subsystem and stores；
Storage subsystem can be transferred to playback subsystem the echo digital signal of storage；Playback subsystem supply trigger signal and
Digital echo signal is reduced under conditions of sampling clock analogue signal, and waveform playback is transferred to gather son by SMA interface
System.
The operation principle of the present invention: Secondary Surveillance Radar Signal Simulator based on FPGA should design device, by arranging data
Acquisition subsystem plate, uses coherent video simulation, it is possible to reappears realistically not only to comprise amplitude but also comprise the relevant of phase place and regards
Frequently signal, reappear this signal transmitting, spatial transmission, be scattered body reflection and in receiver, carry out the full mistake processed
Journey, and coherent video make use of the phase place of signal, it contain radar environments whole for information about, as long as being provided
Elementary object and environmental model the best, so that it may so that coherent video simulation precision the highest, and use radar return
Detector, can enter radar system rear class signal processing sometimes under conditions of actual radar system front end does not possesses
Row debugging and test, it provides instrument easily and effectively to the design and analysis of radar system and performance test.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Any amendment, equivalent and the improvement etc. made within god and principle, should be included within the scope of the present invention.
Claims (8)
1. Secondary Surveillance Radar Signal Simulator based on a FPGA design device, including data acquisition subsystem plate (1) and control
Panel (2), described control panel (2) left end connects liquid crystal display (3) and radar return detector (4), it is characterised in that:
Described data acquisition subsystem plate (1) includes subsystem memory (5), and the input of described subsystem memory (5) connects to be had
Pulse-generating circuit (6), described pulse-generating circuit (6) is connected with trigger signal controller (7) by fixing cable, described
Being provided with surface-mounted integrated circuit (8) in trigger signal controller (7), the left end of described surface-mounted integrated circuit (8) is provided with multiple sampling
Clock frequency: primary is clock frequency detector (9), the outfan of described clock frequency detector (9) connects embedded meter
Calculation machine (10), the outfan of described embedded computer (10) connects signal conditioning circuit (11), described signal conditioning circuit
(11) outfan connects simulation single-chip microcomputer (12)；Be provided with in described control panel (2) digital signal processor (13) and
Flush bonding processor (14), the communication data port of described digital signal processor (13) by RS232 communication interface (16) with
Flush bonding processor (14) is connected, and flush bonding processor (14) connects data storage (15) and serial communication modular
(17)。
A kind of Secondary Surveillance Radar Signal Simulator based on FPGA the most according to claim 1 design device, it is characterised in that:
The input of described trigger signal controller (7) is connected with the outfan of pulse-generating circuit (6), pulse-generating circuit (6)
Outfan be also connected with waveshape detector (18).
A kind of Secondary Surveillance Radar Signal Simulator based on FPGA the most according to claim 1 design device, it is characterised in that:
Described embedded computer (10) includes Human-machine Control interface (19) and industrial computer interface monitor (20), described Human-machine Control circle
The control end in face (19) is connected to flush bonding processor (14) by cable, and the connection of described industrial computer interface monitor (20) has micro-
Type webcam driver device (24).
A kind of Secondary Surveillance Radar Signal Simulator based on FPGA the most according to claim 1 design device, it is characterised in that:
Described radar return detector (4) includes constant-current amplifier (21), and the outfan of described constant-current amplifier (21) connects high pass
Wave filter (22), the outfan of described high pass filter (22) connects analog-digital converter (23).
A kind of Secondary Surveillance Radar Signal Simulator based on FPGA the most according to claim 1 design device, it is characterised in that:
The input of described simulation single-chip microcomputer (12) is connected with the outfan of high pass filter (22), and described high pass filter (22) is adopted
It is the digital filter of control core in order to FPGA.
A kind of Secondary Surveillance Radar Signal Simulator based on FPGA the most according to claim 1 design device, it is characterised in that:
The outfan of described simulation single-chip microcomputer (12) connects wireless data transmitter (28), and described wireless receiver (28) is with embedding
Enter formula processor (14) and carry out data communication.
A kind of Secondary Surveillance Radar Signal Simulator based on FPGA the most according to claim 1 design device, it is characterised in that:
Described serial communication modular (17) includes RJ45 network adapter (25), and the outfan of RJ45 network adapter (25) connects to be had
Cpci bus interface (26), the outfan of described cpci bus interface (26) connects receiver (27).
A kind of Secondary Surveillance Radar Signal Simulator based on FPGA the most according to claim 1 design device, it is characterised in that:
Described flush bonding processor (14) uses the ARM11 series monolithic of STM32 kernel, and described digital signal processor (13) uses
The process chip of TIC66X series, described data storage (15) uses DDR2 memorizer, and described subsystem memory (5) uses
The SRAM cache district of internal system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610473261.4A CN106199540A (en) | 2016-06-27 | 2016-06-27 | A kind of Secondary Surveillance Radar Signal Simulator based on FPGA design device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610473261.4A CN106199540A (en) | 2016-06-27 | 2016-06-27 | A kind of Secondary Surveillance Radar Signal Simulator based on FPGA design device |
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| CN106199540A true CN106199540A (en) | 2016-12-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610473261.4A Pending CN106199540A (en) | 2016-06-27 | 2016-06-27 | A kind of Secondary Surveillance Radar Signal Simulator based on FPGA design device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108761409A (en) * | 2018-07-19 | 2018-11-06 | 电子科技大学 | A kind of generation of secondary radar signals and test method |
| CN112731302A (en) * | 2021-04-06 | 2021-04-30 | 湖南纳雷科技有限公司 | STM32 and FPGA-based reverse radar signal processing system and method |
-
2016
- 2016-06-27 CN CN201610473261.4A patent/CN106199540A/en active Pending
Non-Patent Citations (2)
| Title |
|---|
| 刘培生: "雷达成像信号模拟器设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 苗旺: "基于FPGA的雷达信号模拟器设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108761409A (en) * | 2018-07-19 | 2018-11-06 | 电子科技大学 | A kind of generation of secondary radar signals and test method |
| CN108761409B (en) * | 2018-07-19 | 2022-03-25 | 电子科技大学 | Secondary radar signal generation and test method |
| CN112731302A (en) * | 2021-04-06 | 2021-04-30 | 湖南纳雷科技有限公司 | STM32 and FPGA-based reverse radar signal processing system and method |
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Application publication date: 20161207 |
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