CN201780798U - NAND flash memory with high error correcting capability - Google Patents
NAND flash memory with high error correcting capability Download PDFInfo
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- CN201780798U CN201780798U CN2009202828410U CN200920282841U CN201780798U CN 201780798 U CN201780798 U CN 201780798U CN 2009202828410 U CN2009202828410 U CN 2009202828410U CN 200920282841 U CN200920282841 U CN 200920282841U CN 201780798 U CN201780798 U CN 201780798U
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Abstract
The utility model discloses an NAND flash memory with high error correcting capability. The NAND flash memory is characterized in that all NAND types and designs are supported by an external ECC circuit, the method also has other advantages in terms of performances, interfaces and the like, an ECC and an NAND chip are packed or externally arranged without changing an NAND controller so as to improve error correcting performance and the performance of the integral flash memory, simultaneously profound influences can be generated on a master control, for example, a table-block data structure of the flash memory can be changed, page data (2/4/8Kbytes)+redundant data (12/24/48bytes)+ECC checking codes are generated, the master control can omit an ECC circuit while the ECC can be packed as an independent chip, or ECC naked particles and flash memory naked particles can be packed together into a chip, and consequently design flexibility of the flash memory is improved.
Description
Technical field
The utility model relates to a kind of nand flash memory, relates in particular to a kind of nand flash memory with high error correction ability.
Background technology
At present, nand flash memory has become the main selection that is used as mass memory in the consumer application, have the advantage that cost of bit is lower, storage density is higher because it compares the NOR flash memory, and have the size littler, lower power consumption and more reliable advantage than hard disk.Because the demand of nand flash memory on the consumption market be very high, thereby carrying cost descends very soon, can reach higher density with lower cost with nand memory as POS (point of sale) terminal, printer and other application.
Yet owing to the requirement of these Embedded Application to higher nand flash memory density improving constantly, the designer need make suitable selection from various nand flash memory types, density, supplier and development course figure and implementation.First of use nand flash memory also is that most important choice criteria is the realization of NAND controller.All nand flash memory devices all need to be arranged in the maintenance costs of software and reliable to guarantee data as the peripheral control unit of hardware, make the life-span maximum of nand flash memory device, and improve performance.Three major functions of NAND controller are bad block management, wear leveling and Error Correction of Coding (ECC).
Nand flash memory with bunch form carry out data storage, promptly so-called.Most of nand flash memory devices will have been found some bad pieces when manufacturing test, these bad pieces are markd in supplier's device specification explanation.That is to say that nand flash memory just has the storage unit of damage when dispatching from the factory, in addition, good piece also may reduce performance in the NAND life cycle, in use also can constantly produce the storage unit of new damage after dispatching from the factory.Therefore, one, must follow the tracks of by software, and carry out bad block management; Two, specific piece is carried out continuous read-write operation and may cause this piece very fast " wearing and tearing " and become bad piece, in order to ensure the longest life-span of NAND device, the quantity of restriction wear block need utilize the wear leveling technology to allow all pieces read and write the number of times equilibrium; Three,, therefore must realize that ECC finds and correct these error codes with software or hardware mode because stopping or operating of certain unit may produce error code.ECC is defined as the code bit number that can correct in per 512 bytes or 1024 byte sector by industry usually.
In people's routine work, the use of flash disk is more and more general.Believe that many people once ran into the problem of loss of data.Usually only say so on the flash disk operation instruction misplug pull out due to, the reason that causes the flash disk loss of data is not that only this is a kind of, also exist other several may.One of them is that because the characteristic of flash memory itself, the mistake that takes place can not be avoided fully when carrying out reading and writing data, in order to reduce wrong generation as far as possible, just must adopt ECC numeral error correcting technique.This technology is a kind of technology that generally is applied to the computer data integrity detection, and it can be when carrying out Data Detection, and the very first time is revised error in data, thereby various fortuitous events such as the mess code that occurs in the document copying, compressed package damage are significantly reduced.
Each cell stores individual character position (1 bit) of SLC nand flash memory, each piece all have long serviceable life and reliability, therefore need less ECC, and excellent performance can be provided.Each cell stores double word position (2 bit) of MLC nand flash memory, performance is then lower, and is difficult to realize, because it needs more high-grade bad block management, wear leveling and ECC.Yet with regard to the price of single-bit, it approximately has only 1/3 of SLC NAND.Because the cost gap is increasing between SLC and the MLC NAND, great majority are used the application that begins to turn to MLC NAND, particularly higher density, can reduce material cost widely like this.Along with MLC NAND technology node continue dwindle, support the required ECC grade of this nand memory to become more and more higher.The required ECC grade of MLC NAND is 8 bits at present, but will soon bring up to 12 bits and 24 bits.The ECC of greater number needs the hardware supported in the NAND controller.Yet the developing steps of microprocessor are much slower than fast-developing MLC NAND.And TL CNAND has appearred now, and each cell stores three word bit (3 bit), this kind flash memory is higher for the requirement of ECC, has reached 48 bits.Therefore in the present stage of nand flash memory fast development, except the development of accelerating microprocessor, also pressing for some can be at the temporary transient technology or the product that more but can not improve flash memory performance in the changer controller.
The utility model content
The technical problems to be solved in the utility model is under the prerequisite of the nand flash memory controller of not upgrading, and a kind of nand flash memory with high error correction ability is provided.
For solving the problems of the technologies described above, the utility model has adopted following technical scheme: a kind of nand flash memory of high error correcting capability, comprise NAND ECC controller and nand flash memory chip, the master controller of using this type of high error correcting capability nand flash memory does not need to be provided with the ECC circuit, and described ECC circuit is arranged on the master controller outside.
A kind of preferred version as the nand flash memory of high error correcting capability described in the utility model: described ECC circuit is packaged into a chips with the naked particle of flash memory, and this chip is provided with the flash interface of standard.
A kind of preferred version as the nand flash memory of high error correcting capability described in the utility model: described ECC circuit is as an independent Chip Packaging, and it is provided with the interface of standard.
A kind of preferred version as the nand flash memory of high error correcting capability described in the utility model: contain Bose-Chaudhuri Hocquenghem error correction codes in the described ECC circuit.
A kind of preferred version as the nand flash memory of high error correcting capability described in the utility model: described Bose-Chaudhuri Hocquenghem error correction codes is programmed to 24.
A kind of preferred version as the nand flash memory of high error correcting capability described in the utility model: described Bose-Chaudhuri Hocquenghem error correction codes is programmed to 14.
A kind of preferred version as the nand flash memory of high error correcting capability described in the utility model: described Bose-Chaudhuri Hocquenghem error correction codes is programmed to 48.
A kind of preferred version as the nand flash memory of high error correcting capability described in the utility model: the basic status control of described ECC is drawn by on input and the output interface, drop-down realization.
A kind of preferred version as the nand flash memory of high error correcting capability described in the utility model: the NAND order of described ECC chip utilization expansion is controlled it.
A kind of preferred version as the nand flash memory of high error correcting capability described in the utility model: the built-in ECC data block buffer of described flash memory.
Utilize external ECC circuit described in the utility model to support all NAND type and design, this method can also provide other benefits of aspects such as performance and interface, it is under the prerequisite that does not change the NAND controller, with ECC and NAND Chip Packaging or external, thereby the raising error correcting capability promotes the performance of whole flash memory.Also can exert far reaching influence for master control simultaneously, for example: will change Hash memory pages blocks of data layout: page data (2/4/8Kbytes)+redundant data (12/24/48bytes)+ECC check code; Master control can not need to be provided with the ECC circuit, but need to judge whether the data that read are wrong, if wrong, do not need to read again, and the ECC chip has been read again 3 times or the number of times of other settings, can sentence it as bad piece; Can also read OOB data, i.e. redundant data separately; Can bring extra delay though correct random error, yet because main frame does not need to do any correction at random, for main frame, the delay of total reading of data is the same.Can be with ECC as an independent Chip Packaging; Or naked particle of ECC and the naked particle of flash memory be packaged together, become a chips.These have all increased the design flexibility of flash memory.
After adopting structure described in the utility model, this flash memory is also supported many flash memories sheet choosing (as many as 8), supports 8 word bits and 16 word bit flash memories, support different page or leaf block sizes, such as 2K, 4K, 8Kbytes supports the order of all nand flash memories, supports the flash interface and the ONFI flash interface of standard.Can also utilize simultaneously the NAND order of expansion to control, comprise control and status register the ECC chip, and firmware upgrade, by firmware upgrade, can support order in the future; The control of its basic status can by draw on the IO, drop-down realization (do not need expand NAND order).
All right built-in ECC data block buffer (such as 4 ECC data block buffers, each buffer zone 1Kbytes), all flash memories are shared these data block buffers, and read operation and write operation are shared these data block buffers; Can utilize streamline to improve the performance of read and write, can reduce the number of data block buffer, but can bring the performance decrease of read and write.The ECC data block buffer is finished the write order at random of NAND or non-whole page or leaf write order or whole page or leaf write order: a, the data page buffer zone is used to cushion page data; B, to the data of discontented whole page or leaf, insert 0 or 1 and make data reach the size of full ECC piece; C is used to calculate the ECC check code.The reading of data page buffer is used for the ECC error correction, at first, data is read into buffer zone; But if the random error number within the error correction scope of ECC, random error will be repaired, and with correct transmission of data blocks to main frame; Correct random error and can bring extra delay, yet because main frame does not need to do any correction at random, for main frame, the delay of total reading of data is the same; If but the random error number not within the error correction scope of ECC, is not transferred to main frame through the original data block of error correction, when main frame read the mode bit of read command, main frame will be read the state of ECC mistake; The ECC control chip can be read (limited number of times is such as 3 times) again automatically the data block that can not correct random error.Can also discern flash block data and redundant data automatically, and use different error correcting code (BCH or Hamming code), main frame cannot be read and write the ECC check code that is stored in the redundant data piece, and the ECC check code in the redundant data piece can be positioned over ending place of page data piece.
Description of drawings
Fig. 1 is the contrast synoptic diagram that the relevant ECC circuit with the utility model of prior art is provided with.
Embodiment
Describe embodiment of the present utility model in detail below in conjunction with accompanying drawing.
In Fig. 1, the left side synoptic diagram has been described the connected mode of flash controller and ECC circuit in the prior art, and promptly the master controller of flash memory and ECC circuit package are together.As for the connected mode between flash controller and the flash chip, multiple choices are still arranged, various connected modes respectively have quality.If systematic microprocessor has built-in SLC or MLC controller, just do not need external devices or logic.Otherwise controlled NAND method is also good, because it carries out encapsulation by NAND supplier, does not need external logic or chip equally.Yet in order to obtain maximum dirigibility, the developer can utilize outside NAND controller to support all NAND type and preference, and this method can also provide other benefits of aspects such as performance and interface.
Fig. 1 right side synoptic diagram has been described the connected mode of ECC and nand flash memory controller in the utility model, ECC circuit and nand flash memory are combined, the flash interface of standard is provided for master control simultaneously, and master control does not need to have the ECC function, only needs to judge whether the data that read are correct.And ECC error correction energy, if adopt Bose-Chaudhuri Hocquenghem error correction codes, every 1K bit data block can be corrected 48 random errors, is programmable to 24 or 14; If adopt Hamming (HAMMING) error correcting code, per 12 bits of redundancy data pieces can be corrected 1 random error, detect 2 random errors.Certainly also can adopt other error correcting codes.
Claims (3)
1. the nand flash memory of a high error correcting capability, comprise NAND ECC controller and nand flash memory chip, it is characterized in that: the ECC circuit is arranged on the master controller outside of nand flash memory, the ECC circuit is packaged into a chips with the naked particle of flash memory, and the flash interface that this chip is provided with standard is connected with the master controller of nand flash memory.
2. the nand flash memory of high error correcting capability according to claim 1, it is characterized in that: described ECC circuit is as an independent Chip Packaging, and it is provided with the interface of standard.
3. the nand flash memory of high error correcting capability according to claim 2 is characterized in that: the built-in ECC data block buffer of described flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009202828410U CN201780798U (en) | 2009-12-24 | 2009-12-24 | NAND flash memory with high error correcting capability |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009202828410U CN201780798U (en) | 2009-12-24 | 2009-12-24 | NAND flash memory with high error correcting capability |
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| CN201780798U true CN201780798U (en) | 2011-03-30 |
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| CN2009202828410U Expired - Lifetime CN201780798U (en) | 2009-12-24 | 2009-12-24 | NAND flash memory with high error correcting capability |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104375953A (en) * | 2013-08-15 | 2015-02-25 | 联想(北京)有限公司 | Equipment control method and electronic equipment |
| CN108062260A (en) * | 2018-01-12 | 2018-05-22 | 江苏华存电子科技有限公司 | A kind of flash data guard method using false data |
-
2009
- 2009-12-24 CN CN2009202828410U patent/CN201780798U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104375953A (en) * | 2013-08-15 | 2015-02-25 | 联想(北京)有限公司 | Equipment control method and electronic equipment |
| CN104375953B (en) * | 2013-08-15 | 2018-07-06 | 联想(北京)有限公司 | Apparatus control method and electronic equipment |
| CN108062260A (en) * | 2018-01-12 | 2018-05-22 | 江苏华存电子科技有限公司 | A kind of flash data guard method using false data |
| WO2019136971A1 (en) * | 2018-01-12 | 2019-07-18 | 江苏华存电子科技有限公司 | Flash data protection method using false data |
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Effective date of registration: 20170303 Address after: Pudong New Area Zhangjiang hi tech road 201203 Shanghai City No. 1158 Zhang No. 2 Building 7 floor Patentee after: Brite Semiconductor (Shanghai) Corporation Address before: Suzhou City, Jiangsu province 215021 international science and Technology Park No. 1355 Jinji Lake Avenue Suzhou industrial park two D102-2 Patentee before: Suzhou Liangzhi Technology Co., Ltd. |
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Granted publication date: 20110330 |
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| CX01 | Expiry of patent term |