CN201732133U - Terminal tester - Google Patents
Terminal tester Download PDFInfo
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- CN201732133U CN201732133U CN2010201557081U CN201020155708U CN201732133U CN 201732133 U CN201732133 U CN 201732133U CN 2010201557081 U CN2010201557081 U CN 2010201557081U CN 201020155708 U CN201020155708 U CN 201020155708U CN 201732133 U CN201732133 U CN 201732133U
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Abstract
The utility model relates to a terminal tester used for detecting the polarities or welding situation of diodes in a junction box via appointed current. The terminal tester comprises a testing circuit (1) and a digital display voltmeter (2), wherein the testing circuit (1) comprises a time-base circuit (11), a sequential circuit (12), an alarming circuit (13), a voltage comparison circuit (14), a measuring save circuit (15), a differential amplifying circuit (16) and a current generation control circuit (17). The terminal tester can accurately detect the positive and negative polarities and welding situation of the diodes connected in series in the junction box.
Description
(1) technical field
The utility model relates to a kind of terminal tester, is used for detecting by specified current flow the whole conduction of terminal box.
(2) background technology
At present, adopt multimeter to carry out single detection for the detection of diode more, to determine its positive-negative polarity or welding situation, but the situation for a plurality of diode series connection in the terminal box can't effectively detect, whether can't determine whether the diode both positive and negative polarity connects correctly or do not have the rosin joint phenomenon, it is normal more can't to detect the internal wiring welding.
(3) utility model content
The purpose of this utility model is to overcome above-mentioned deficiency, and a kind of terminal tester that can accurately detect diode in series positive-negative polarity in the terminal box and welding situation by specified current flow is provided.
The purpose of this utility model is achieved in that terminal tester, include test circuit and digital display voltage table, described test circuit includes time base circuit, sequential circuit, warning circuit, voltage comparator circuit, measurement preservation circuit, differential amplifier circuit and electric current generation control circuit
Described time base circuit constitutes multivibrator by 555 timer JP1, be the 1 pin ground connection of described 555 timer JP1, the 2 pin back one tunnel that links to each other with 6 pin links to each other with 7 pin through resistance R 1, another road is through capacitor C 2 ground connection, 4 pin link to each other with high level VCC with 8 pin, 5 foot meridian capacitor C1 ground connection, 7 pin link to each other with high level VCC through resistance R 2;
Described sequential circuit includes timing sequencer CD4017JP2,5 pin of described timing sequencer CD4017JP2 link to each other with the positive pole of diode D1 and D2 respectively with 6 pin, the negative pole of described diode D1 and the D2 back one tunnel that links to each other links to each other with the negative pole of diode D3, another road links to each other with the base stage of triode Q1 through R37, the positive pole of described diode D3 links to each other with 9 pin, the grounded emitter of described Q3, collector one tunnel links to each other with loudspeaker LS1 power cathode, another road links to each other with the negative pole of light emitting diode D4 after resistance R 4, the positive pole of D4 links to each other with the positive pole of loudspeaker LS1, and the positive pole of loudspeaker LS1 links to each other with high level VCC, 8 pin of described JP2 and the equal ground connection of 13 pin, 16 pin link to each other with high level VCC, and 14 pin link to each other with 3 pin of JP1,15 pin one tunnel link to each other with 3 pin through R3, another road links to each other with the collector of triode Q6, the grounded emitter of triode Q6, and base stage links to each other with the end of two-way switch S2 through resistance R 35, the other end ground connection of S2, described two-way switch S1 is through capacitor C 3 ground connection;
Described warning circuit includes CD4013JP3,3 pin of described JP3,5 pin, 7 pin, 9 pin and the equal ground connection of 11 pin, 4 pin respectively with diode D5, one end of the negative pole of D6 and resistance R 7 links to each other, described D5, the positive pole of D6 links to each other with 1 pin with 3 pin of JP2 respectively, described resistance R 7 ground connection, 6 pin one tunnel of described JP3 link to each other with 4 pin of JP2, another road is through resistance R 6 ground connection, 10 pin one tunnel of described JP3 link to each other with 2 pin of JP2, one the tunnel through resistance R 5 ground connection, 14 pin of described JP3 link to each other with high level VCC, 13 pin link to each other through the base stage of resistance R 8 with triode Q2, the grounded emitter of described triode Q2, and collector one tunnel links to each other through the negative pole of resistance R 9 with light emitting diode D7, another road links to each other with the power cathode of loudspeaker LS2, and the positive pole of the positive source of described loudspeaker LS2 and light emitting diode D7 all links to each other with high level VCC;
Described voltage comparator circuit includes LM358JP7,4 pin of described JP7 all link to each other with high level VCC with 8 pin, 6 pin one tunnel link to each other with the digital display voltage table, another road links to each other with the slide plate of slide rheostat R34, described slide rheostat R34 one end ground connection, another termination high level VCC, 7 pin of described JJP7 link to each other with the positive pole of diode D20, the negative pole one tunnel of described diode D20 is through resistance R 29 ground connection, and another road links to each other with 8 pin of JP3;
Described measurement is preserved circuit and is included LF398JP8,1 pin of described JP8 links to each other with high level VCC with 4 pin, 2 pin and 6 pin are respectively through capacitor C 4 and C7 ground connection, 3 pin link to each other with 5 pin of JP7 through resistance R 32,5 pin of described JP8 link to each other with the digital display voltage table through resistance R 33, and 8 pin of described JP8 link to each other with 10 pin of JP2;
Described differential amplifier circuit includes LM358JP6,1 pin one tunnel of described JP6 links to each other with 6 pin through R25, another road links to each other with 2 pin through R39,2 pin of described JP6 link to each other with test node A after resistance R 26,2 pin of described JP6 link to each other with the negative pole of diode D16 and the positive pole of D17, the positive pole of described diode D16 links to each other back one tunnel through R30 ground connection with the negative pole of D17, another road directly links to each other with 3 pin, 3 pin of described JP7 link to each other with test node B through resistance R 27, described test node B ground connection, 4 pin of described JP6 link to each other with high level VCC with 8 pin, 7 pin one tunnel link to each other with 6 pin through resistance R 28, another road directly links to each other with 5 pin of JP7,6 pin of described JP6 link to each other with the negative pole of diode D18 and the positive pole of D19, the positive pole of the described diode D18 negative pole of D19 links to each other back one tunnel through resistance R 31 ground connection, and another road links to each other with 5 pin of JP6;
Described electric current generation control circuit includes LM358JP4 and LM358JP5,1 pin of described JP4 links to each other with 2 pin through resistance R 18,2 pin link to each other with 2 pin of JP5 through resistance R 17,3 pin one tunnel of described JP4 link to each other with the digital display voltage table, another road links to each other with the slide plate of slide rheostat R19, described slide rheostat R19 one end ground connection, the other end links to each other with high level VCC, 4 pin of described JP4 all link to each other with high level VCC with 8 pin, 1 pin one tunnel of described JP5 links to each other with 2 pin through resistance R 15, another road links to each other with 6 pin with resistance R 16,2 pin of described JP5 link to each other with the negative pole of the positive pole of diode D13 and D14, after linking to each other with the positive pole of D14, the negative pole of described diode D13 links to each other with 3 pin of JP5,3 pin of described JP5 are through resistance R 12 ground connection, 4 pin of described JP5 link to each other with high level VCC with 8 pin, 5 pin of described JP5 link to each other with the positive pole of the negative pole of diode D10 and D12, after linking to each other with the negative pole of D12, the positive pole of described D10 links to each other with 6 pin of JP5,5 pin of described JP5 are through resistance R 11 ground connection, be parallel with a capacitor C 5 on this resistance R 11,5 pin of described JP5 link to each other with test node A through resistance R 38,6 pin of described JP5 link to each other with the negative pole of diode D15, the positive pole of described diode D16 links to each other with 2 pin of JP3,6 pin of described JP5 link to each other through the emitter of resistance R 13 with triode Q5,7 pin of described JP5 link to each other with the base stage of triode Q3 after resistance R 14, the collector of described triode Q3 links to each other with high level VCC through resistance R 20, the emitter of described triode Q3 links to each other with the emitter of Q5 through resistance R 10, the emitter of described triode Q3 links to each other with the base stage of triode Q4, the collector of described triode Q4 links to each other with high level VCC through resistance R 20, the emitter of described triode Q4 links to each other with the base stage of triode Q5, the collector of described triode Q5 links to each other with high level VCC, the emitter of described triode Q5 is through resistance R 23 ground connection, and the emitter of described triode Q5 links to each other with test node A through resistance R 24.
Principle of work of the present utility model:
During use, with terminal box to be measured by test node A and the test node B tester that accesses terminal; In use, resistance R 24 is made as 1 ohm, regulate R19 by digital display voltage table control input voltage, according to Ohm law I=U/R, input current is numerically equal to input voltage as can be known, thereby has promptly realized control to electric current by regulating R19 control voltage, and when adjusting electric current, whether electric current is chosen for the rated current of used diode, and the rated current butted line box of input detects by moment, normal to determine the internal wiring welding; Set comparative voltage by regulating R34 subsequently, as being in series with 3 schottky diodes in the terminal box to be measured, its PN junction forward voltage summation is 1.5V, promptly regulate R34 and make that comparative voltage is 1.5V, observe the voltage registration of terminal box subsequently, if registration is about 1.5V, then diode all is connected normally with circuit in the terminal box; If the diode positive-negative polarity connects anti-or there are problems such as rosin joint in circuit, then trigger CD4013 control loudspeaker LS2 and report to the police, at this moment, the testing staff opens terminal box and can observe by the interior circuit of butted line box, finds out particular problem and is solved.
The beneficial effects of the utility model are:
Series diode carries out the detection of polarity or welding situation in the butted line box easily, during use, test node A and test node B can be drawn as terminal, only needs when needing to detect can finish detection easily to inserting, and has improved work efficiency greatly.
(4) description of drawings
Fig. 1 is the utility model circuit diagram.
Among the figure:
Circuit 15, differential amplifier circuit 16, electric current generation control circuit 17 are preserved in test circuit 1, time base circuit 11, sequential circuit 12, warning circuit 13, voltage comparator circuit 14, measurement;
Digital display voltage table 2.
(5) embodiment
Referring to Fig. 1, the utility model relates to a kind of terminal tester, include test circuit 1 and digital display voltage table 2, described test circuit 1 includes time base circuit 11, sequential circuit 12, warning circuit 13, voltage comparator circuit 14, measures and preserve circuit 15, differential amplifier circuit 16 and electric current generation control circuit 17
Described time base circuit 11 constitutes multivibrator by 555 timer JP1, be the 1 pin ground connection of described 555 timer JP1, the 2 pin back one tunnel that links to each other with 6 pin links to each other with 7 pin through resistance R 1, another road is through capacitor C 2 ground connection, 4 pin link to each other with high level VCC with 8 pin, 5 foot meridian capacitor C1 ground connection, 7 pin link to each other with high level VCC through resistance R 2;
Described sequential circuit 12 includes timing sequencer CD4017JP2,5 pin of described timing sequencer CD4017JP2 link to each other with the positive pole of diode D1 and D2 respectively with 6 pin, the negative pole of described diode D1 and the D2 back one tunnel that links to each other links to each other with the negative pole of diode D3, another road links to each other with the base stage of triode Q1 through R37, the positive pole of described diode D3 links to each other with 9 pin, the grounded emitter of described Q3, collector one tunnel links to each other with loudspeaker LS1 power cathode, another road links to each other with the negative pole of light emitting diode D4 after resistance R 4, the positive pole of D4 links to each other with the positive pole of loudspeaker LS1, and the positive pole of loudspeaker LS1 links to each other with high level VCC, 8 pin of described JP2 and the equal ground connection of 13 pin, 16 pin link to each other with high level VCC, and 14 pin link to each other with 3 pin of JP1,15 pin one tunnel link to each other with 3 pin through R3, another road links to each other with the collector of triode Q6, the grounded emitter of triode Q6, and base stage links to each other with the end of two-way switch S2 through resistance R 35, the other end ground connection of S2, described two-way switch S1 is through capacitor C 3 ground connection;
Described warning circuit 13 includes CD4013JP3,3 pin of described JP3,5 pin, 7 pin, 9 pin and the equal ground connection of 11 pin, 4 pin respectively with diode D5, one end of the negative pole of D6 and resistance R 7 links to each other, described D5, the positive pole of D6 links to each other with 1 pin with 3 pin of JP2 respectively, described resistance R 7 ground connection, 6 pin one tunnel of described JP3 link to each other with 4 pin of JP2, another road is through resistance R 6 ground connection, 10 pin one tunnel of described JP3 link to each other with 2 pin of JP2, one the tunnel through resistance R 5 ground connection, 14 pin of described JP3 link to each other with high level VCC, 13 pin link to each other through the base stage of resistance R 8 with triode Q2, the grounded emitter of described triode Q2, and collector one tunnel links to each other through the negative pole of resistance R 9 with light emitting diode D7, another road links to each other with the power cathode of loudspeaker LS2, and the positive pole of the positive source of described loudspeaker LS2 and light emitting diode D7 all links to each other with high level VCC;
Described voltage comparator circuit 14 includes LM358JP7,4 pin of described JP7 all link to each other with high level VCC with 8 pin, 6 pin one tunnel link to each other with digital display voltage table 2, another road links to each other with the slide plate of slide rheostat R34, described slide rheostat R34 one end ground connection, another termination high level VCC, 7 pin of described JJP7 link to each other with the positive pole of diode D20, the negative pole one tunnel of described diode D20 is through resistance R 29 ground connection, and another road links to each other with 8 pin of JP3;
Described measurement is preserved circuit 15 and is included LF398JP8,1 pin of described JP8 links to each other with high level VCC with 4 pin, 2 pin and 6 pin are respectively through capacitor C 4 and C7 ground connection, 3 pin link to each other with 5 pin of JP7 through resistance R 32,5 pin of described JP8 link to each other with digital display voltage table 2 through resistance R 33, and 8 pin of described JP8 link to each other with 10 pin of JP2;
Described differential amplifier circuit 16 includes LM358JP6,1 pin one tunnel of described JP6 links to each other with 6 pin through R25, another road links to each other with 2 pin through R39,2 pin of described JP6 link to each other with test node A after resistance R 26,2 pin of described JP6 link to each other with the negative pole of diode D16 and the positive pole of D17, the positive pole of described diode D16 links to each other back one tunnel through R30 ground connection with the negative pole of D17, another road directly links to each other with 3 pin, 3 pin of described JP7 link to each other with test node B through resistance R 27, described test node B ground connection, 4 pin of described JP6 link to each other with high level VCC with 8 pin, 7 pin one tunnel link to each other with 6 pin through resistance R 28, another road directly links to each other with 5 pin of JP7,6 pin of described JP6 link to each other with the negative pole of diode D18 and the positive pole of D19, the positive pole of the described diode D18 negative pole of D19 links to each other back one tunnel through resistance R 31 ground connection, and another road links to each other with 5 pin of JP6;
Described electric current generation control circuit 17 includes LM358JP4 and LM358JP5,1 pin of described JP4 links to each other with 2 pin through resistance R 18,2 pin link to each other with 2 pin of JP5 through resistance R 17,3 pin one tunnel of described JP4 link to each other with digital display voltage table 2, another road links to each other with the slide plate of slide rheostat R19, described slide rheostat R19 one end ground connection, and the other end links to each other with high level VCC, 4 pin of described JP4 all link to each other with high level VCC with 8 pin
1 pin one tunnel of described JP5 links to each other with 2 pin through resistance R 15, another road links to each other with 6 pin with resistance R 16,2 pin of described JP5 link to each other with the negative pole of the positive pole of diode D13 and D14, after linking to each other with the positive pole of D14, the negative pole of described diode D13 links to each other with 3 pin of JP5,3 pin of described JP5 are through resistance R 12 ground connection, 4 pin of described JP5 link to each other with high level VCC with 8 pin, 5 pin of described JP5 link to each other with the positive pole of the negative pole of diode D10 and D12, after linking to each other with the negative pole of D12, the positive pole of described D10 links to each other with 6 pin of JP5,5 pin of described JP5 are through resistance R 11 ground connection, be parallel with a capacitor C 5 on this resistance R 11,5 pin of described JP5 link to each other with test node A through resistance R 38,6 pin of described JP5 link to each other with the negative pole of diode D15, the positive pole of described diode D16 links to each other with 2 pin of JP3,6 pin of described JP5 link to each other through the emitter of resistance R 13 with triode Q5,7 pin of described JP5 link to each other with the base stage of triode Q3 after resistance R 14, the collector of described triode Q3 links to each other with high level VCC through resistance R 20, the emitter of described triode Q3 links to each other with the emitter of Q5 through resistance R 10, the emitter of described triode Q3 links to each other with the base stage of triode Q4, the collector of described triode Q4 links to each other with high level VCC through resistance R 20, the emitter of described triode Q4 links to each other with the base stage of triode Q5, the collector of described triode Q5 links to each other with high level VCC, the emitter of described triode Q5 is through resistance R 23 ground connection, and the emitter of described triode Q5 links to each other with test node A through resistance R 24.
Claims (1)
1. terminal tester, it is characterized in that: described terminal tester includes test circuit (1) and digital display voltage table (2), described test circuit (1) includes time base circuit (11), sequential circuit (12), warning circuit (13), voltage comparator circuit (14), measures and preserve circuit (15), differential amplifier circuit (16) and electric current generation control circuit (17)
Described time base circuit (11) constitutes multivibrator by 555 timer JP1, be the 1 pin ground connection of described 555 timer JP1, the 2 pin back one tunnel that links to each other with 6 pin links to each other with 7 pin through resistance R 1, another road is through capacitor C 2 ground connection, 4 pin link to each other with high level VCC with 8 pin, 5 foot meridian capacitor C1 ground connection, 7 pin link to each other with high level VCC through resistance R 2;
Described sequential circuit (12) includes timing sequencer CD4017JP2,5 pin of described timing sequencer CD4017JP2 link to each other with the positive pole of diode D1 and D2 respectively with 6 pin, the negative pole of described diode D1 and the D2 back one tunnel that links to each other links to each other with the negative pole of diode D3, another road links to each other with the base stage of triode Q1 through R37, the positive pole of described diode D3 links to each other with 9 pin, the grounded emitter of described Q3, collector one tunnel links to each other with loudspeaker LS1 power cathode, another road links to each other with the negative pole of light emitting diode D4 after resistance R 4, the positive pole of D4 links to each other with the positive pole of loudspeaker LS1, and the positive pole of loudspeaker LS1 links to each other with high level VCC, 8 pin of described JP2 and the equal ground connection of 13 pin, 16 pin link to each other with high level VCC, and 14 pin link to each other with 3 pin of JP1,15 pin one tunnel link to each other with 3 pin through R3, another road links to each other with the collector of triode Q6, the grounded emitter of triode Q6, and base stage links to each other with the end of two-way switch S2 through resistance R 35, the other end ground connection of S2, described two-way switch S1 is through capacitor C 3 ground connection;
Described warning circuit (13) includes CD4013JP3,3 pin of described JP3,5 pin, 7 pin, 9 pin and the equal ground connection of 11 pin, 4 pin respectively with diode D5, one end of the negative pole of D6 and resistance R 7 links to each other, described D5, the positive pole of D6 links to each other with 1 pin with 3 pin of JP2 respectively, described resistance R 7 ground connection, 6 pin one tunnel of described JP3 link to each other with 4 pin of JP2, another road is through resistance R 6 ground connection, 10 pin one tunnel of described JP3 link to each other with 2 pin of JP2, one the tunnel through resistance R 5 ground connection, 14 pin of described JP3 link to each other with high level VCC, 13 pin link to each other through the base stage of resistance R 8 with triode Q2, the grounded emitter of described triode Q2, and collector one tunnel links to each other through the negative pole of resistance R 9 with light emitting diode D7, another road links to each other with the power cathode of loudspeaker LS2, and the positive pole of the positive source of described loudspeaker LS2 and light emitting diode D7 all links to each other with high level VCC;
Described voltage comparator circuit (14) includes LM358JP7,4 pin of described JP7 all link to each other with high level VCC with 8 pin, 6 pin one tunnel link to each other with digital display voltage table (2), another road links to each other with the slide plate of slide rheostat R34, described slide rheostat R34 one end ground connection, another termination high level VCC, 7 pin of described JJP7 link to each other with the positive pole of diode D20, the negative pole one tunnel of described diode D20 is through resistance R 29 ground connection, and another road links to each other with 8 pin of JP3;
Described measurement is preserved circuit (15) and is included LF398 JP8,1 pin of described JP8 links to each other with high level VCC with 4 pin, 2 pin and 6 pin are respectively through capacitor C 4 and C7 ground connection, 3 pin link to each other with 5 pin of JP7 through resistance R 32,5 pin of described JP8 link to each other with digital display voltage table (2) through resistance R 33, and 8 pin of described JP8 link to each other with 10 pin of JP2;
Described differential amplifier circuit (16) includes LM358 JP6,1 pin one tunnel of described JP6 links to each other with 6 pin through R25, another road links to each other with 2 pin through R39,2 pin of described JP6 link to each other with test node A after resistance R 26,2 pin of described JP6 link to each other with the negative pole of diode D16 and the positive pole of D17, the positive pole of described diode D16 links to each other back one tunnel through R30 ground connection with the negative pole of D17, another road directly links to each other with 3 pin, 3 pin of described JP7 link to each other with test node B through resistance R 27, described test node B ground connection, 4 pin of described JP6 link to each other with high level VCC with 8 pin, 7 pin one tunnel link to each other with 6 pin through resistance R 28, another road directly links to each other with 5 pin of JP7,6 pin of described JP6 link to each other with the negative pole of diode D18 and the positive pole of D19, the positive pole of the described diode D18 negative pole of D19 links to each other back one tunnel through resistance R 31 ground connection, and another road links to each other with 5 pin of JP6;
Described electric current generation control circuit (17) includes LM358JP4 and LM358JP5,1 pin of described JP4 links to each other with 2 pin through resistance R 18,2 pin link to each other with 2 pin of JP5 through resistance R 17,3 pin one tunnel of described JP4 link to each other with digital display voltage table (2), another road links to each other with the slide plate of slide rheostat R19, described slide rheostat R19 one end ground connection, the other end links to each other with high level VCC, 4 pin of described JP4 all link to each other with high level VCC with 8 pin, 1 pin one tunnel of described JP5 links to each other with 2 pin through resistance R 15, another road links to each other with 6 pin with resistance R 16,2 pin of described JP5 link to each other with the negative pole of the positive pole of diode D13 and D14, after linking to each other with the positive pole of D14, the negative pole of described diode D13 links to each other with 3 pin of JP5,3 pin of described JP5 are through resistance R 12 ground connection, 4 pin of described JP5 link to each other with high level VCC with 8 pin, 5 pin of described JP5 link to each other with the positive pole of the negative pole of diode D10 and D12, after linking to each other with the negative pole of D12, the positive pole of described D10 links to each other with 6 pin of JP5,5 pin of described JP5 are through resistance R 11 ground connection, be parallel with a capacitor C 5 on this resistance R 11,5 pin of described JP5 link to each other with test node A through resistance R 38,6 pin of described JP5 link to each other with the negative pole of diode D15, the positive pole of described diode D16 links to each other with 2 pin of JP3,6 pin of described JP5 link to each other through the emitter of resistance R 13 with triode Q5,7 pin of described JP5 link to each other with the base stage of triode Q3 after resistance R 14, the collector of described triode Q3 links to each other with high level VCC through resistance R 20, the emitter of described triode Q3 links to each other with the emitter of Q5 through resistance R 10, the emitter of described triode Q3 links to each other with the base stage of triode Q4, the collector of described triode Q4 links to each other with high level VCC through resistance R 20, the emitter of described triode Q4 links to each other with the base stage of triode Q5, the collector of described triode Q5 links to each other with high level VCC, the emitter of described triode Q5 is through resistance R 23 ground connection, and the emitter of described triode Q5 links to each other with test node A through resistance R 24.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201557081U CN201732133U (en) | 2010-03-31 | 2010-03-31 | Terminal tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201557081U CN201732133U (en) | 2010-03-31 | 2010-03-31 | Terminal tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201732133U true CN201732133U (en) | 2011-02-02 |
Family
ID=43523292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201557081U Expired - Lifetime CN201732133U (en) | 2010-03-31 | 2010-03-31 | Terminal tester |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201732133U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101846713A (en) * | 2010-03-31 | 2010-09-29 | 江苏爱康太阳能科技有限公司 | Terminal test instrument |
-
2010
- 2010-03-31 CN CN2010201557081U patent/CN201732133U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101846713A (en) * | 2010-03-31 | 2010-09-29 | 江苏爱康太阳能科技有限公司 | Terminal test instrument |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20110202 Effective date of abandoning: 20120606 |