CN101846713B - Terminal test instrument - Google Patents
Terminal test instrument Download PDFInfo
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- CN101846713B CN101846713B CN2010101424313A CN201010142431A CN101846713B CN 101846713 B CN101846713 B CN 101846713B CN 2010101424313 A CN2010101424313 A CN 2010101424313A CN 201010142431 A CN201010142431 A CN 201010142431A CN 101846713 B CN101846713 B CN 101846713B
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Abstract
The invention relates to a terminal test instrument, which is used for detecting the polarity or the welding condition of a diode in a junction box through specified current and comprises a test circuit and a digital display voltmeter. The test circuit comprises a time base circuit, a sequence circuit, an alarm circuit, a voltage comparison circuit, a measuring and storing circuit, a differential amplification circuit and a current generation control circuit. The terminal test instrument can accurately detect the positive polarities and the negative polarities as well as the welding conditions of the serial diodes in the junction box.
Description
(1) technical field
The present invention relates to a kind of terminal tester, be used for detecting the whole conduction of terminal box through specified current flow.
(2) background technology
At present; Adopt multimeter to carry out single detection for the detection of diode more; To confirm its positive-negative polarity or welding situation; But the situation for a plurality of diodes series connection in the terminal box can't effectively detect, and can't confirm whether the diode both positive and negative polarity connects correctly or do not have the rosin joint phenomenon, and whether more can't detect the internal wiring welding normal.
(3) summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, a kind of terminal tester that can accurately detect diode in series positive-negative polarity in the terminal box and welding situation through specified current flow is provided.
The objective of the invention is to realize like this: terminal tester; Include test circuit and digital display voltage table; Said test circuit includes time base circuit, sequential circuit, warning circuit, voltage comparator circuit, measurement preservation circuit, differential amplifier circuit and electric current generation control circuit
Said time base circuit constitutes multivibrator by 555 timer JP1; Be the 1 pin ground connection of said 555 timer JP1; The 2 pin back one tunnel that links to each other with 6 pin links to each other with 7 pin through resistance R 1, and another road is through capacitor C 2 ground connection, and 4 pin link to each other with high level VCC with 8 pin; 5 foot meridian capacitor C1 ground connection, 7 pin link to each other with high level VCC through resistance R 2;
Said sequential circuit includes CD4017 timing sequencer JP2, and 5 pin of said CD4017 timing sequencer JP2 link to each other with the positive pole of diode D1 and D2 respectively with 6 pin, and the negative pole of said diode D1 and the D2 back one tunnel that links to each other links to each other with the negative pole of diode D3; Another road links to each other with the base stage of triode Q1 through R37, and the positive pole of said diode D3 links to each other with 9 pin, the grounded emitter of said Q3; Collector one tunnel links to each other with loudspeaker LS1 power cathode, and another road links to each other with the negative pole of light emitting diode D4 after resistance R 4, and the positive pole of D4 links to each other with the positive pole of loudspeaker LS1; And the positive pole of loudspeaker LS1 links to each other with high level VCC, 8 pin of said JP2 and the equal ground connection of 13 pin, and 16 pin link to each other with high level VCC; 14 pin link to each other with 3 pin of JP1, and 15 pin one tunnel link to each other with 3 pin through R3, and another road links to each other with the collector of triode Q6; The grounded emitter of triode Q6; Base stage links to each other with the end of two-way switch S2 through resistance R 35, the other end ground connection of S2, and said two-way switch S1 is through capacitor C 3 ground connection;
Said warning circuit includes CD4013 double D trigger JP3,3 pin of said JP3,5 pin, 7 pin, 9 pin and the equal ground connection of 11 pin, and 4 pin link to each other with the negative pole of diode D5, D6 and an end of resistance R 7 respectively; The positive pole of said D5, D6 links to each other with 1 pin with 3 pin of JP2 respectively; Said resistance R 7 ground connection, 6 pin one tunnel of said JP3 link to each other with 4 pin of JP2, and another road is through resistance R 6 ground connection; 10 pin one tunnel of said JP3 link to each other with 2 pin of JP2; One the tunnel through resistance R 5 ground connection, and 14 pin of said JP3 link to each other with high level VCC, and 13 pin link to each other through the base stage of resistance R 8 with triode Q2; The grounded emitter of said triode Q2; Collector one tunnel links to each other through the negative pole of resistance R 9 with light emitting diode D7, and another road links to each other with the power cathode of loudspeaker LS2, and the positive pole of the positive source of said loudspeaker LS2 and light emitting diode D7 all links to each other with high level VCC;
Said voltage comparator circuit includes LM358 operational amplifier JP7, and 4 pin of said JP7 all link to each other with high level VCC with 8 pin, and 6 pin one tunnel link to each other with the digital display voltage table; Another road links to each other with the slide plate of slide rheostat R34; Said slide rheostat R34 one end ground connection, another termination high level VCC, 7 pin of said JP7 link to each other with the positive pole of diode D20; The negative pole one tunnel of said diode D20 is through resistance R 29 ground connection, and another road links to each other with 8 pin of JP3;
Said measurement preserve circuit include the LF398 sampling retainer JP8; 1 pin of said JP8 links to each other with high level VCC with 4 pin; 2 pin and 6 pin are respectively through capacitor C 4 and C7 ground connection; 3 pin link to each other with 5 pin of JP7 through resistance R 32, and 5 pin of said JP8 link to each other with the digital display voltage table through resistance R 33, and 8 pin of said JP8 link to each other with 10 pin of JP2;
Said differential amplifier circuit includes LM358 operational amplifier JP6, and 1 pin one tunnel of said JP6 links to each other with 6 pin through R25, and another road links to each other with 2 pin through R39; 2 pin of said JP6 link to each other with test node A after resistance R 26; 2 pin of said JP6 link to each other with the negative pole of diode D16 and the positive pole of D17, and the positive pole of said diode D16 links to each other back one tunnel through R30 ground connection with the negative pole of D17, and another road directly links to each other with 3 pin; 3 pin of said JP7 link to each other with test node B through resistance R 27; Said test node B ground connection, 4 pin of said JP6 link to each other with high level VCC with 8 pin, and 7 pin one tunnel link to each other with 6 pin through resistance R 28; Another road directly links to each other with 5 pin of JP7; 6 pin of said JP6 link to each other with the negative pole of diode D18 and the positive pole of D19, and the positive pole of the said diode D18 negative pole of D19 links to each other back one tunnel through resistance R 31 ground connection, and another road links to each other with 5 pin of JP6;
Said electric current generation control circuit includes LM358 operational amplifier JP4 and LM358 operational amplifier JP5, and 1 pin of said JP4 links to each other with 2 pin through resistance R 18, and 2 pin link to each other with 2 pin of JP5 through resistance R 17; 3 pin one tunnel of said JP4 link to each other with the digital display voltage table, and another road links to each other with the slide plate of slide rheostat R19, said slide rheostat R19 one end ground connection; The other end links to each other with high level VCC, and 4 pin of said JP4 all link to each other with high level VCC with 8 pin, and 1 pin one tunnel of said JP5 links to each other with 2 pin through resistance R 15; Another road links to each other with 6 pin with resistance R 16, and 2 pin of said JP5 link to each other with the negative pole of the positive pole of diode D13 and D14, links to each other with 3 pin of JP5 after the negative pole of said diode D13 links to each other with the positive pole of D14; 3 pin of said JP5 are through resistance R 12 ground connection, and 4 pin of said JP5 link to each other with high level VCC with 8 pin, and 5 pin of said JP5 link to each other with the positive pole of the negative pole of diode D10 and D12; After linking to each other with the negative pole of D12, the positive pole of said D10 links to each other with 6 pin of JP5; 5 pin of said JP5 are parallel with a capacitor C 5 through resistance R 11 ground connection on this resistance R 11,5 pin of said JP5 link to each other with test node A through resistance R 38; 6 pin of said JP5 link to each other with the negative pole of diode D15; The positive pole of said diode D16 links to each other with 2 pin of JP3, and 6 pin of said JP5 link to each other through the emitter of resistance R 13 with triode Q5, and 7 pin of said JP5 link to each other with the base stage of triode Q3 after resistance R 14; The collector of said triode Q3 links to each other with high level VCC through resistance R 20; The emitter of said triode Q3 links to each other with the emitter of Q5 through resistance R 10, and the emitter of said triode Q3 links to each other with the base stage of triode Q4, and the collector of said triode Q4 links to each other with high level VCC through resistance R 20; The emitter of said triode Q4 links to each other with the base stage of triode Q5; The collector of said triode Q5 links to each other with high level VCC, and the emitter of said triode Q5 is through resistance R 23 ground connection, and the emitter of said triode Q5 links to each other with test node A through resistance R 24.
Principle of work of the present invention:
During use, with terminal box to be measured through test node A and the test node B tester that accesses terminal; In use, resistance R 24 is made as 1 ohm, regulates R19 through digital display voltage table control input voltage; According to Ohm law I=U/R, can know that input current is numerically equal to input voltage, thereby promptly realize control electric current through regulating R19 control voltage; And when the adjustment electric current; Whether electric current is chosen for the rated current of used diode, and the rated current butted line box of input detects through moment, normal to confirm the internal wiring welding; Set comparative voltage through regulating R34 subsequently; As being in series with 3 schottky diodes in the terminal box to be measured; Its PN junction forward voltage summation is 1.5V, promptly regulates R34 and makes that comparative voltage is 1.5V, observes the voltage registration of terminal box subsequently; If registration is about 1.5V, then diode all is connected normally with circuit in the terminal box; If the diode positive-negative polarity connects anti-or there are problems such as rosin joint in circuit, then trigger CD4013 control loudspeaker LS2 and report to the police, at this moment, the testing staff opens terminal box and can observe by the interior circuit of butted line box, finds out particular problem and solves.
The invention has the beneficial effects as follows:
Series diode carries out the detection of polarity or welding situation in the butted line box easily, during use, can test node A and test node B be drawn as terminal, only needs when needing to detect can accomplish detection easily to inserting, and has improved work efficiency greatly.
(4) description of drawings
Fig. 1 is a circuit diagram of the present invention.
(5) embodiment
Referring to Fig. 1; The present invention relates to a kind of terminal tester; Include test circuit and digital display voltage table, said test circuit includes time base circuit, sequential circuit, warning circuit, voltage comparator circuit, measurement preservation circuit, differential amplifier circuit and electric current generation control circuit
Said time base circuit constitutes multivibrator by 555 timer JP1; Be the 1 pin ground connection of said 555 timer JP1; The 2 pin back one tunnel that links to each other with 6 pin links to each other with 7 pin through resistance R 1, and another road is through capacitor C 2 ground connection, and 4 pin link to each other with high level VCC with 8 pin; 5 foot meridian capacitor C1 ground connection, 7 pin link to each other with high level VCC through resistance R 2;
Said sequential circuit includes CD4017 timing sequencer JP2, and 5 pin of said CD4017 timing sequencer JP2 link to each other with the positive pole of diode D1 and D2 respectively with 6 pin, and the negative pole of said diode D1 and the D2 back one tunnel that links to each other links to each other with the negative pole of diode D3; Another road links to each other with the base stage of triode Q1 through R37, and the positive pole of said diode D3 links to each other with 9 pin, the grounded emitter of said Q3; Collector one tunnel links to each other with loudspeaker LS1 power cathode, and another road links to each other with the negative pole of light emitting diode D4 after resistance R 4, and the positive pole of D4 links to each other with the positive pole of loudspeaker LS1; And the positive pole of loudspeaker LS1 links to each other with high level VCC, 8 pin of said JP2 and the equal ground connection of 13 pin, and 16 pin link to each other with high level VCC; 14 pin link to each other with 3 pin of JP1, and 15 pin one tunnel link to each other with 3 pin through R3, and another road links to each other with the collector of triode Q6; The grounded emitter of triode Q6; Base stage links to each other with the end of two-way switch S2 through resistance R 35, the other end ground connection of S2, and said two-way switch S1 is through capacitor C 3 ground connection;
Said warning circuit includes CD4013 double D trigger JP3,3 pin of said JP3,5 pin, 7 pin, 9 pin and the equal ground connection of 11 pin, and 4 pin link to each other with the negative pole of diode D5, D6 and an end of resistance R 7 respectively; The positive pole of said D5, D6 links to each other with 1 pin with 3 pin of JP2 respectively; Said resistance R 7 ground connection, 6 pin one tunnel of said JP3 link to each other with 4 pin of JP2, and another road is through resistance R 6 ground connection; 10 pin one tunnel of said JP3 link to each other with 2 pin of JP2; One the tunnel through resistance R 5 ground connection, and 14 pin of said JP3 link to each other with high level VCC, and 13 pin link to each other through the base stage of resistance R 8 with triode Q2; The grounded emitter of said triode Q2; Collector one tunnel links to each other through the negative pole of resistance R 9 with light emitting diode D7, and another road links to each other with the power cathode of loudspeaker LS2, and the positive pole of the positive source of said loudspeaker LS2 and light emitting diode D7 all links to each other with high level VCC;
Said voltage comparator circuit includes LM358 operational amplifier JP7, and 4 pin of said JP7 all link to each other with high level VCC with 8 pin, and 6 pin one tunnel link to each other with the digital display voltage table; Another road links to each other with the slide plate of slide rheostat R34; Said slide rheostat R34 one end ground connection, another termination high level VCC, 7 pin of said JP7 link to each other with the positive pole of diode D20; The negative pole one tunnel of said diode D20 is through resistance R 29 ground connection, and another road links to each other with 8 pin of JP3;
Said measurement preserve circuit include the LF398 sampling retainer JP8; 1 pin of said JP8 links to each other with high level VCC with 4 pin; 2 pin and 6 pin are respectively through capacitor C 4 and C7 ground connection; 3 pin link to each other with 5 pin of JP7 through resistance R 32, and 5 pin of said JP8 link to each other with the digital display voltage table through resistance R 33, and 8 pin of said JP8 link to each other with 10 pin of JP2;
Said differential amplifier circuit includes LM358 operational amplifier JP6, and 1 pin one tunnel of said JP6 links to each other with 6 pin through R25, and another road links to each other with 2 pin through R39; 2 pin of said JP6 link to each other with test node A after resistance R 26; 2 pin of said JP6 link to each other with the negative pole of diode D16 and the positive pole of D17, and the positive pole of said diode D16 links to each other back one tunnel through R30 ground connection with the negative pole of D17, and another road directly links to each other with 3 pin; 3 pin of said JP7 link to each other with test node B through resistance R 27; Said test node B ground connection, 4 pin of said JP6 link to each other with high level VCC with 8 pin, and 7 pin one tunnel link to each other with 6 pin through resistance R 28; Another road directly links to each other with 5 pin of JP7; 6 pin of said JP6 link to each other with the negative pole of diode D18 and the positive pole of D19, and the positive pole of the said diode D18 negative pole of D19 links to each other back one tunnel through resistance R 31 ground connection, and another road links to each other with 5 pin of JP6;
Said electric current generation control circuit includes LM358 operational amplifier JP4 and LM358 operational amplifier JP5, and 1 pin of said JP4 links to each other with 2 pin through resistance R 18, and 2 pin link to each other with 2 pin of JP5 through resistance R 17; 3 pin one tunnel of said JP4 link to each other with the digital display voltage table; Another road links to each other with the slide plate of slide rheostat R19, said slide rheostat R19 one end ground connection, and the other end links to each other with high level VCC; 4 pin of said JP4 all link to each other with high level VCC with 8 pin
1 pin one tunnel of said JP5 links to each other with 2 pin through resistance R 15, and another road links to each other with 6 pin with resistance R 16, and 2 pin of said JP5 link to each other with the negative pole of the positive pole of diode D13 and D14; After linking to each other with the positive pole of D14, the negative pole of said diode D13 links to each other with 3 pin of JP5; 3 pin of said JP5 are through resistance R 12 ground connection, and 4 pin of said JP5 link to each other with high level VCC with 8 pin, and 5 pin of said JP5 link to each other with the positive pole of the negative pole of diode D10 and D12; After linking to each other with the negative pole of D12, the positive pole of said D10 links to each other with 6 pin of JP5; 5 pin of said JP5 are parallel with a capacitor C 5 through resistance R 11 ground connection on this resistance R 11,5 pin of said JP5 through resistance R 38 and test node A mutually
Connect, 6 pin of said JP5 link to each other with the negative pole of diode D15, and the positive pole of said diode D16 links to each other with 2 pin of JP3; 6 pin of said JP5 link to each other through the emitter of resistance R 13 with triode Q5; 7 pin of said JP5 link to each other with the base stage of triode Q3 after resistance R 14, and the collector of said triode Q3 links to each other with high level VCC through resistance R 20, and the emitter of said triode Q3 links to each other with the emitter of Q5 through resistance R 10; The emitter of said triode Q3 links to each other with the base stage of triode Q4; The collector of said triode Q4 links to each other with high level VCC through resistance R 20, and the emitter of said triode Q4 links to each other with the base stage of triode Q5, and the collector of said triode Q5 links to each other with high level VCC; The emitter of said triode Q5 is through resistance R 23 ground connection, and the emitter of said triode Q5 links to each other with test node A through resistance R 24.
Claims (1)
1. terminal tester; It is characterized in that: said terminal tester includes test circuit and digital display voltage table; Said test circuit includes time base circuit, sequential circuit, warning circuit, voltage comparator circuit, measurement preservation circuit, differential amplifier circuit and electric current generation control circuit
Said time base circuit constitutes multivibrator by 555 timer JP1; Be the 1 pin ground connection of said 555 timer JP1; The 2 pin back one tunnel that links to each other with 6 pin links to each other with 7 pin through resistance R 1, and another road is through capacitor C 2 ground connection, and 4 pin link to each other with high level VCC with 8 pin; 5 foot meridian capacitor C1 ground connection, 7 pin link to each other with high level VCC through resistance R 2;
Said sequential circuit includes CD4017 timing sequencer JP2, and 5 pin of said CD4017 timing sequencer JP2 link to each other with the positive pole of diode D1 and D2 respectively with 6 pin, and the negative pole of said diode D1 and the D2 back one tunnel that links to each other links to each other with the negative pole of diode D3; Another road links to each other with the base stage of triode Q1 through R37, and the positive pole of said diode D3 links to each other with 9 pin, the grounded emitter of said Q3; Collector one tunnel links to each other with loudspeaker LS1 power cathode, and another road links to each other with the negative pole of light emitting diode D4 after resistance R 4, and the positive pole of D4 links to each other with the positive pole of loudspeaker LS1; And the positive pole of loudspeaker LS1 links to each other with high level VCC, 8 pin of said JP2 and the equal ground connection of 13 pin, and 16 pin link to each other with high level VCC; 14 pin link to each other with 3 pin of JP1, and 15 pin one tunnel link to each other with 3 pin through R3, and another road links to each other with the collector of triode Q6; The grounded emitter of triode Q6; Base stage links to each other with the end of two-way switch S2 through resistance R 35, the other end ground connection of S2, and said two-way switch S1 is through capacitor C 3 ground connection;
Said warning circuit includes CD4013 double D trigger JP3,3 pin of said JP3,5 pin, 7 pin, 9 pin and the equal ground connection of 11 pin, and 4 pin link to each other with the negative pole of diode D5, D6 and an end of resistance R 7 respectively; The positive pole of said D5, D6 links to each other with 1 pin with 3 pin of JP2 respectively; Said resistance R 7 ground connection, 6 pin one tunnel of said JP3 link to each other with 4 pin of JP2, and another road is through resistance R 6 ground connection; 10 pin one tunnel of said JP3 link to each other with 2 pin of JP2; One the tunnel through resistance R 5 ground connection, and 14 pin of said JP3 link to each other with high level VCC, and 13 pin link to each other through the base stage of resistance R 8 with triode Q2; The grounded emitter of said triode Q2; Collector one tunnel links to each other through the negative pole of resistance R 9 with light emitting diode D7, and another road links to each other with the power cathode of loudspeaker LS2, and the positive pole of the positive source of said loudspeaker LS2 and light emitting diode D7 all links to each other with high level VCC;
Said voltage comparator circuit includes LM358 operational amplifier JP7, and 4 pin of said JP7 all link to each other with high level VCC with 8 pin, and 6 pin one tunnel link to each other with the digital display voltage table; Another road links to each other with the slide plate of slide rheostat R34; Said slide rheostat R34 one end ground connection, another termination high level VCC, 7 pin of said JP7 link to each other with the positive pole of diode D20; The negative pole one tunnel of said diode D20 is through resistance R 29 ground connection, and another road links to each other with 8 pin of JP3;
Said measurement preserve circuit include the LF398 sampling retainer JP8; 1 pin of said JP8 links to each other with high level VCC with 4 pin; 2 pin and 6 pin are respectively through capacitor C 4 and C7 ground connection; 3 pin link to each other with 5 pin of JP7 through resistance R 32, and 5 pin of said JP8 link to each other with the digital display voltage table through resistance R 33, and 8 pin of said JP8 link to each other with 10 pin of JP2;
Said differential amplifier circuit includes LM358 operational amplifier JP6, and 1 pin one tunnel of said JP6 links to each other with 6 pin through R25, and another road links to each other with 2 pin through R39; 2 pin of said JP6 link to each other with test node A after resistance R 26; 2 pin of said JP6 link to each other with the negative pole of diode D16 and the positive pole of D17, and the positive pole of said diode D16 links to each other back one tunnel through R30 ground connection with the negative pole of D17, and another road directly links to each other with 3 pin; 3 pin of said JP7 link to each other with test node B through resistance R 27; Said test node B ground connection, 4 pin of said JP6 link to each other with high level VCC with 8 pin, and 7 pin one tunnel link to each other with 6 pin through resistance R 28; Another road directly links to each other with 5 pin of JP7; 6 pin of said JP6 link to each other with the negative pole of diode D18 and the positive pole of D19, and the positive pole of the said diode D18 negative pole of D19 links to each other back one tunnel through resistance R 31 ground connection, and another road links to each other with 5 pin of JP6;
Said electric current generation control circuit includes LM358 operational amplifier JP4 and LM358 operational amplifier JP5, and 1 pin of said JP4 links to each other with 2 pin through resistance R 18, and 2 pin link to each other with 2 pin of JP5 through resistance R 17; 3 pin one tunnel of said JP4 link to each other with the digital display voltage table, and another road links to each other with the slide plate of slide rheostat R19, said slide rheostat R19 one end ground connection; The other end links to each other with high level VCC, and 4 pin of said JP4 all link to each other with high level VCC with 8 pin, and 1 pin one tunnel of said JP5 links to each other with 2 pin through resistance R 15; Another road links to each other with 6 pin with resistance R 16, and 2 pin of said JP5 link to each other with the negative pole of the positive pole of diode D13 and D14, links to each other with 3 pin of JP5 after the negative pole of said diode D13 links to each other with the positive pole of D14; 3 pin of said JP5 are through resistance R 12 ground connection; 4 pin of said JP5 link to each other with high level VCC with 8 pin, and 5 pin of said JP5 link to each other with the positive pole of the negative pole of diode D10 and D12, link to each other with 6 pin of JP5 after the positive pole of said D10 links to each other with the negative pole of D12; 5 pin of said JP5 are through resistance R 11 ground connection; Be parallel with a capacitor C 5 on this resistance R 11,5 pin of said JP5 link to each other with test node A through resistance R 38, and 6 pin of said JP5 link to each other with the negative pole of diode D15; The positive pole of said diode D16 links to each other with 2 pin of JP3; 6 pin of said JP5 link to each other through the emitter of resistance R 13 with triode Q5, and 7 pin of said JP5 link to each other with the base stage of triode Q3 after resistance R 14, and the collector of said triode Q3 is through resistance R 20 and high level VCC
Link to each other; The emitter of said triode Q3 links to each other with the emitter of Q5 through resistance R 10, and the emitter of said triode Q3 links to each other with the base stage of triode Q4, and the collector of said triode Q4 links to each other with high level VCC through resistance R 20; The emitter of said triode Q4 links to each other with the base stage of triode Q5; The collector of said triode Q5 links to each other with high level VCC, and the emitter of said triode Q5 is through resistance R 23 ground connection, and the emitter of said triode Q5 links to each other with test node A through resistance R 24.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101424313A CN101846713B (en) | 2010-03-31 | 2010-03-31 | Terminal test instrument |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101424313A CN101846713B (en) | 2010-03-31 | 2010-03-31 | Terminal test instrument |
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| Publication Number | Publication Date |
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| CN101846713A CN101846713A (en) | 2010-09-29 |
| CN101846713B true CN101846713B (en) | 2012-06-06 |
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| CN2010101424313A Expired - Fee Related CN101846713B (en) | 2010-03-31 | 2010-03-31 | Terminal test instrument |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2537015Y (en) * | 2002-01-09 | 2003-02-19 | 顺德市顺达电脑厂有限公司 | Double color diode inspector |
| CN100432685C (en) * | 2003-12-22 | 2008-11-12 | 威宇科技测试封装有限公司 | Chip pin open circuit and short circuit tester and method therefor |
| DE102008022298B3 (en) * | 2008-03-13 | 2009-04-16 | Fpe Fischer Gmbh | Junction box for solar module of solar plant, has electrical component e.g. bypass diode, and electrical connection, which are arranged in housing, where component firmly lies on interior sides of chamber and at housing cover |
| CN101308191B (en) * | 2008-07-03 | 2011-01-19 | 金天 | Diode electrical characteristics test system |
| CN201732133U (en) * | 2010-03-31 | 2011-02-02 | 江苏爱康太阳能科技股份有限公司 | Terminal tester |
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