CN212675136U - Fault detection device for line load - Google Patents
Fault detection device for line load Download PDFInfo
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- CN212675136U CN212675136U CN202020089429.3U CN202020089429U CN212675136U CN 212675136 U CN212675136 U CN 212675136U CN 202020089429 U CN202020089429 U CN 202020089429U CN 212675136 U CN212675136 U CN 212675136U
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Abstract
The utility model provides a fault detection device of line load belongs to load detection's circuit improvement technical field, include: a processor; the signal generating circuit is connected with the load circuit after amplifying the detection signal by the first signal amplifier; the current acquisition circuit consists of a second signal amplifier, one input end of the second signal amplifier is connected with the working voltage and the signal generation circuit through a resistor, and the output end of the second signal amplifier is connected with the processor; the short-circuit voltage acquisition circuit is composed of a third signal amplifier, and one input end of the third signal amplifier is connected with the load circuit; and the load operation voltage acquisition circuit consists of a fourth signal amplifier, and one input end of the fourth signal amplifier is connected with the load circuit through a divider resistor. The utility model discloses, through inputing detected signal to load circuit, then be connected with current acquisition circuit, short-circuit voltage acquisition circuit and load operating voltage acquisition circuit through the treater, obtain the detected value to acquire the detected value through the treater is automatic.
Description
Technical Field
The utility model belongs to the technical field of the circuit detects, especially, relate to a fault detection device of circuit load.
Background
At present, the common technology of circuit load detection is manual segmented detection, a target circuit state is segmented and detected by adopting equipment such as an electroprobe, a universal meter and the like, and a damaged part of a load circuit is obtained by combining a circuit principle. With the technical progress, the reliability and the efficiency of the power supply circuit are required to be higher and higher by users.
The traditional detection technology has low detection efficiency, excessively depends on manual detection, and easily causes a large amount of economic loss under the condition of manual detection error. In the process of maintenance, real-time fault alarm cannot be realized, reliable and timely alarm cannot be provided for electrical faults, and potential safety hazards exist in a power grid.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a fault detection device for a line load, which is connected to a load circuit via a processor, a current collection circuit, a short-circuit voltage collection circuit and a load operation voltage collection circuit to obtain a detection value, thereby automatically acquiring the detection value via the processor.
To achieve the above and other related objects, the present invention provides a fault detection device for a line load, the device including:
a processor for generating a detection signal;
the signal generating circuit consists of a first signal amplifier, amplifies the detection signal by the first signal amplifier and then is connected with a load circuit;
the current acquisition circuit consists of a second signal amplifier, one input end of the second signal amplifier is connected with the working voltage and the signal generation circuit through a resistor, the other input end of the second signal amplifier is grounded, and the output end of the second signal amplifier is connected with the processor;
the short-circuit voltage acquisition circuit consists of a third signal amplifier, the output end of the third signal amplifier is connected with the processor, one input end of the third signal amplifier is connected with the load circuit, and the other input end of the third signal amplifier is grounded;
the load operation voltage acquisition circuit is composed of a fourth signal amplifier, one input end of the fourth signal amplifier is connected with the load circuit through a divider resistor, the other input end of the fourth signal amplifier is connected with the output end of the fourth signal amplifier, and the output end of the third signal amplifier is connected with the processor.
In one implementation, the signal generation circuit further includes: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor;
one end of the first resistor is connected with a detection signal generation end of the processor, and the other end of the first resistor is connected with a positive input end of the first signal amplifier;
one end of the second resistor is connected with the processor, and the other end of the second resistor is connected with the positive input end of the first signal amplifier;
one end of the third resistor is grounded, the other end of the third resistor is connected with the positive input end of the first signal amplifier, and the third resistor is connected with the first capacitor in parallel;
one end of the fourth resistor is grounded, and the other end of the fourth resistor is connected with the reverse input end of the first signal amplifier;
the output end of the first signal amplifier is connected with the first end of the load circuit.
In one implementation, the current collection circuit further includes: a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor;
the working voltage VDDA is connected with one end of the fifth resistor, and the other end of the fifth resistor is connected with the reverse input end of the first signal amplifier, the forward input end of the second signal amplifier and the second end of the load circuit; the inverting input end of the second signal amplifier is grounded through the sixth resistor;
the inverting input end of the second signal amplifier is connected with the output end of the second signal amplifier through the seventh resistor, and the output end of the second signal amplifier is connected with the processor through the eighth resistor.
In one implementation, the short-circuit voltage acquisition circuit further includes: a ninth resistor, a tenth resistor, and an eleventh resistor;
the processor is connected with the output end of the third signal amplifier through the ninth resistor, the output end of the third signal amplifier is connected with the reverse input end of the third signal amplifier through the tenth resistor, the reverse input end of the third signal amplifier is grounded through the eleventh resistor, and the forward input end of the third signal amplifier is connected with the first end of the load circuit.
In one implementation, the load operation voltage acquisition circuit further includes: a twelfth resistor, a thirteenth resistor, and a fourteenth resistor;
the processor is connected with the output end and the reverse input end of the fourth signal amplifier through the twelfth resistor, the forward input end of the fourth signal amplifier is connected with one end of the thirteenth resistor and one end of the fourteenth resistor, the other end of the thirteenth resistor is connected with the first end of the load circuit, and the other end of the fourteenth resistor is grounded.
In one implementation, the device further comprises a circuit state detection circuit, which is composed of a current detection chip, wherein the input end of the circuit state detection circuit is connected with the load circuit, the output end of the circuit state detection circuit is connected with the processor, the load circuit is connected with the drain electrode of the MOS tube, the source electrode of the MOS tube is grounded, and the gate electrode of the MOS tube is connected with the processor.
In one implementation, the circuit state detection circuit further includes: a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor and a second capacitor;
the first input end of the current detection chip is connected with the second end of the load circuit through the sixteenth resistor;
a second input end of the current detection chip is connected with one end of the fifteenth resistor, the other end of the fifteenth resistor is connected with one end of the seventeenth resistor, and the other end of the seventeenth resistor is connected with a second end of the load circuit;
the first input end of the current detection chip is connected with one end of the second capacitor, and the other end of the second capacitor is connected with the second input end of the current detection chip;
and the output end of the current detection chip is connected with the processor through the eighteenth resistor.
In one implementation, the circuit further comprises a nineteenth resistor; the other end of the seventeenth resistor is connected with the drain electrode of the MOS tube, the source electrode of the MOS tube is grounded, the gate electrode of the MOS tube is grounded through the eighteenth resistor, and the gate electrode of the MOS tube is connected with the processor;
the model of the current detection chip is INA 213.
In one implementation, the first signal amplifier, the second signal amplifier, the third signal amplifier, and the fourth signal amplifier are all OPA4192 in type.
In one implementation mode, the system further comprises a buzzer, wherein the buzzer is connected with the processor;
and further comprising a display, the display being connected to the processor;
the model of the processor is STM32F 405.
As described above, the utility model discloses a fault detection device of line load has following beneficial effect:
the detection value is obtained by inputting the detection signal into the load circuit and then connecting the detection signal with the current acquisition circuit, the short-circuit voltage acquisition circuit and the load operation voltage acquisition circuit through the processor, so that the detection value is automatically obtained through the processor.
Drawings
Fig. 1 shows a circuit diagram of a line load fault detection device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic concept of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
Specifically, please refer to fig. 1, fig. 1 shows that the utility model discloses a fault detection device of line load connects between treater and load circuit, the utility model discloses in, the treater specifically is the singlechip realization, and the device includes:
a processor for generating a detection signal; the utility model discloses in, the circuit during operation takes place sinusoidal and square wave's detected signal respectively through the A5 pin earlier by the singlechip, and 3.3V offset voltage is added to rethread A4 pin. The signal is input into a load circuit to be tested through a signal generating circuit, and the signal flows through the load circuit; and the signal generating circuit consists of a first signal amplifier, amplifies the detection signal by the first signal amplifier and then is connected with the load circuit.
Specifically, the signal generating circuit further includes: the circuit comprises a first resistor R8, a second resistor R9, a third resistor R10, a fourth resistor R11 and a first capacitor C20; one end of the first resistor R8 is connected with the detection signal generating end of the processor, and the other end of the first resistor R8 is connected with the positive input end of the first signal amplifier IC 7C; one end of the second resistor R9 is connected with the processor, and the other end of the second resistor R9 is connected with the positive input end of the first signal amplifier IC 7C; one end of the third resistor R10 is connected to ground, the other end is connected to the positive input terminal of the first signal amplifier IC7C, and the third resistor R10 is connected in parallel with the first capacitor C20; one end of the fourth resistor R11 is grounded, and the other end is connected with the inverted input end of the first signal amplifier IC 7C; the output of the first signal amplifier IC7C is connected to a first terminal of a load circuit. Wherein, the PA5 port is provided with sine and square waves by a singlechip; the voltage of 3.3V is connected to the port PA4, and the AC voltage of the port PA5 is partially increased to a positive half shaft as a bias voltage. Because the single chip microcomputer can only collect positive voltage. The current acquisition circuit consists of a second signal amplifier IC7D, one input end of the second signal amplifier IC7D is connected with the working voltage VDDA and the signal generation circuit through a resistor, the other input end is grounded, and the output end is connected with the processor; the current acquisition circuit is used for acquiring the current of the equipment, the positive input of the operational amplifier IC7D is connected with the 2 port of the terminal test, and the voltage of the negative input end of the operational amplifier follows the positive input voltage. Since GNDA forms a loop to PA0, the negative voltage is pinned and the voltage at B-terminal is divided by a resistor.
The current acquisition circuit further includes: a fifth resistor R12, a sixth resistor R13, a seventh resistor R14 and an eighth resistor R15;
the working voltage VDDA is connected with one end of a fifth resistor R12, and the other end of the fifth resistor R12 is connected with the inverting input terminal of the first signal amplifier, the forward input terminal of the second signal amplifier IC7D and the second end of the load circuit; the inverting input terminal of the second signal amplifier IC7D is grounded through a sixth resistor R13; the inverting input terminal of the second signal amplifier IC7D is connected to the output terminal of the second signal amplifier IC7D through a seventh resistor R14, and the output terminal of the second signal amplifier IC7D is connected to the processor through an eighth resistor R15.
PA0 voltage value:
Ub＝UB×(R13+R14+R15)/R13
wherein, UbIs the voltage, U, collected at port PA0BThe voltage value at port 2 of the J3 terminal is shown.
And obtaining a current sampling value through calculation after obtaining the voltage value.
The short-circuit voltage acquisition circuit is composed of a third signal amplifier IC7B, an output end PA2 of the third signal amplifier IC7B is connected with the processor, one input end of the third signal amplifier is connected with a load circuit test (namely a load connected with J3), and the other input end of the third signal amplifier is grounded. When the voltage of the 1 port of the load network test is short-circuited, the loop current is very small, so that the voltage needs to be acquired after being amplified.
Specifically, the load operation voltage acquisition circuit is composed of a fourth signal amplifier IC7A, one input end of the fourth signal amplifier IC7A is connected with the load circuit through a voltage dividing resistor, the other input end of the fourth signal amplifier IC7A is connected with the output end of the fourth signal amplifier IC7A, and the output end of the third signal amplifier IC7B is connected with the processor.
The short-circuit voltage acquisition circuit still includes: a ninth resistor R6, a tenth resistor R23, and an eleventh resistor R24; the processor is connected to the output terminal of the third signal amplifier IC7B through a ninth resistor R6, the output terminal of the third signal amplifier IC7B is connected to the inverting input terminal of the third signal amplifier IC7B through a tenth resistor R23, the inverting input terminal of the third signal amplifier IC7B is connected to ground through an eleventh resistor R24, and the forward input terminal of the third signal amplifier IC7B is connected to the first terminal of the load circuit.
The positive and negative poles of the third signal amplifier IC7B form an amplifier due to the virtual short voltage. Since a closed loop is formed from the port of PA2 to GND, and the voltage of the negative pole of the operational amplifier is synchronous with the voltage of the port 1, the voltage value of the amplified output of the operational amplifier obtained by dividing the voltage by the resistors is about:
u is the acquisition voltage at the PA2 terminal, and U1 is the J3 terminal port 1 voltage.
And the R23 selects a 47K conventional resistor, and after verification, when the R24 selects a 560R resistor, namely the voltage is amplified by about 85 times, the position of a short-circuit point can be accurately determined in short circuit, the accuracy is 1cm, and the R6 selects a conventional circuit protection resistor 22R.
The load operation voltage acquisition circuit consists of a fourth signal amplifier IC7A, one input end of the fourth signal amplifier IC7A is connected with the load circuit through a voltage dividing resistor, the other input end of the fourth signal amplifier IC7A is connected with the output end of the fourth signal amplifier IC7A, and the output end of the third signal amplifier IC7B is connected with the processor.
Different from the open circuit state, the load network voltage is higher when the load is loaded, and R22 and R21 are introduced for collecting after voltage division in order to ensure the accuracy of collected voltage. The operational amplifier is used as a follower, and is sampled by a single chip microcomputer through a protective resistor R7, wherein the load voltage of the circuit is the voltage difference between a port 1 and a port 2 of the test.
The load operation voltage acquisition circuit further comprises: a twelfth resistor R7, a thirteenth resistor R21, a fourteenth resistor R22; the processor is connected with the output end and the reverse input end of a fourth signal amplifier through a twelfth resistor R7, the forward input end of the fourth signal amplifier is connected with one end of a thirteenth resistor R21 and one end of a fourteenth resistor R22, the other end of the thirteenth resistor R21 is connected with the first end of the load circuit, and the other end of the fourteenth resistor R22 is grounded.
The device also comprises a circuit state detection circuit which consists of a current detection chip, wherein the input end of the circuit state detection circuit is connected with a load circuit, the output end of the circuit state detection circuit is connected with the processor, the load circuit is connected with the drain electrode of the MOS tube Q1, the source electrode of the MOS tube Q1 is grounded, and the gate electrode of the MOS tube Q1 is connected with the processor.
Specifically, the circuit state detection circuit further includes: a fifteenth resistor R17, a sixteenth resistor R18, a seventeenth resistor R19, an eighteenth resistor R16 and a second capacitor C36; the first input end of the current detection chip is connected with the second end of the load circuit through a sixteenth resistor R18; the second input end of the current detection chip is connected with one end of a fifteenth resistor R17, the other end of the fifteenth resistor R17 is connected with one end of a seventeenth resistor R19, and the other end of the seventeenth resistor R19 is connected with the second end of the load circuit; the first input end of the current detection chip is connected with one end of a second capacitor C36, and the other end of the second capacitor C36 is connected with the second input end of the current detection chip; the output end of the current detection chip is connected with the processor through an eighteenth resistor R16.
The circuit uses an INA213 current sense chip. The current state of the loop can be achieved through the single chip microcomputer. The MOS tube connected with PB9 is used for verifying the short circuit parameter. When PB9 goes high, the transistor Q1 is turned on, and the voltage between R17 and R19 becomes 0V. The IN + gets the corresponding voltage, and the OUT port outputs the corresponding voltage due to the virtual short and the virtual break. The load circuit can be judged to be in the approximate state according to the output value.
Specifically, the resistance voltage regulator further comprises a nineteenth resistor R125; the other end of the seventeenth resistor R19 is connected with the drain electrode of the MOS transistor Q1, the source electrode of the MOS transistor Q1 is grounded, the gate electrode of the MOS transistor Q1 is grounded through the eighteenth resistor R125, and the gate electrode of the MOS transistor Q1 is connected with the processor; the model of the current detection chip is INA 213.
The first signal amplifier, the second signal amplifier, the third signal amplifier and the fourth signal amplifier are all OPA 4192.
Specifically, the system also comprises a buzzer, wherein the buzzer is connected with the processor; the display is connected with the processor; the processor is model number STM32F 405.
The buzzer alarm module for equipment alarm adopts a buzzer module, is driven by low level and is controlled by a single chip microcomputer. The display screen module adopts a serial port screen. The circuit structure is used for displaying the load state. Is directly controlled by a singlechip.
This circuit function realizes that line load and fault detection device who is main body frame with STM32F407ZET6 minimum system board and operational amplifier OPA4192 chip can real-time detection and demonstration load network structure, and the load is opened a way, short circuit fault reports to the police to and short circuit fault point position measures. The STM32F407ZET6 singlechip sends out the different sinusoidal wave of three routes frequency, passes through the load after the operational amplifier is handled, and the voltage and the current variation of the circuit that the load is located are gathered by STM32F407ZET6 singlechip ADC after the operational amplifier is enlargied and are obtained, obtain the line impedance according to the change value of voltage and current, the line load and the line fault point of being qualified for the next round of competitions that the relation calculation of frequency and impedance again. The buzzer alarms, and the display screen displays circuit faults.
The whole equipment consists of a singlechip, an integrated circuit board, a display screen, a buzzer module and the like. Simple structure, the consumption is little, and the peripheral hardware kind is few, receives environmental impact little.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A fault detection device for a line load, the device comprising:
a processor for generating a detection signal;
the signal generating circuit consists of a first signal amplifier, amplifies the detection signal by the first signal amplifier and then is connected with a load circuit;
the current acquisition circuit consists of a second signal amplifier, one input end of the second signal amplifier is connected with the working voltage and the signal generation circuit through a resistor, the other input end of the second signal amplifier is grounded, and the output end of the second signal amplifier is connected with the processor;
the short-circuit voltage acquisition circuit consists of a third signal amplifier, the output end of the third signal amplifier is connected with the processor, one input end of the third signal amplifier is connected with the load circuit, and the other input end of the third signal amplifier is grounded;
the load operation voltage acquisition circuit is composed of a fourth signal amplifier, one input end of the fourth signal amplifier is connected with the load circuit through a divider resistor, the other input end of the fourth signal amplifier is connected with the output end of the fourth signal amplifier, and the output end of the third signal amplifier is connected with the processor.
2. The line load fault detection device of claim 1, wherein the signal generation circuit further comprises: the circuit comprises a first resistor (R8), a second resistor (R9), a third resistor (R10), a fourth resistor (R11) and a first capacitor (C20);
one end of the first resistor (R8) is connected with the detection signal generation end of the processor, and the other end of the first resistor (R8) is connected with the positive input end of the first signal amplifier;
one end of the second resistor (R9) is connected with the processor, and the other end of the second resistor (R9) is connected with the positive input end of the first signal amplifier;
one end of the third resistor (R10) is connected with the ground, the other end of the third resistor is connected with the positive input end of the first signal amplifier, and the third resistor (R10) is connected with the first capacitor (C20) in parallel;
one end of the fourth resistor (R11) is grounded, and the other end of the fourth resistor (R11) is connected with the inverting input end of the first signal amplifier;
the output end of the first signal amplifier is connected with the first end of the load circuit.
3. The line load fault detection device of claim 2, wherein the current collection circuit further comprises: a fifth resistor (R12), a sixth resistor (R13), a seventh resistor (R14), and an eighth resistor (R15);
the working voltage is connected with one end of a fifth resistor (R12), and the other end of the fifth resistor (R12) is connected with the inverting input end of the first signal amplifier, the forward input end of the second signal amplifier and the second end of the load circuit; the inverting input terminal of the second signal amplifier is grounded through the sixth resistor (R13);
the inverting input end of the second signal amplifier is connected with the output end of the second signal amplifier through the seventh resistor (R14), and the output end of the second signal amplifier is connected with the processor through the eighth resistor (R15).
4. The line load fault detection device of claim 3, wherein the short circuit voltage acquisition circuit further comprises: a ninth resistor (R6), a tenth resistor (R23), and an eleventh resistor (R24);
the processor is connected with the output end of the third signal amplifier through the ninth resistor (R6), the output end of the third signal amplifier is connected with the inverting input end of the third signal amplifier through the tenth resistor (R23), the inverting input end of the third signal amplifier is grounded through the eleventh resistor (R24), and the forward input end of the third signal amplifier is connected with the first end of the load circuit.
5. The line load fault detection device of claim 4, wherein the load operating voltage acquisition circuit further comprises: a twelfth resistor (R7), a thirteenth resistor (R21), and a fourteenth resistor (R22);
the processor is connected with the output end and the reverse input end of the fourth signal amplifier through the twelfth resistor (R7), the forward input end of the fourth signal amplifier is connected with one end of the thirteenth resistor (R21) and one end of the fourteenth resistor (R22), the other end of the thirteenth resistor (R21) is connected with the first end of the load circuit, and the other end of the fourteenth resistor (R22) is grounded.
6. The device for detecting the fault of the line load according to any one of claims 1 to 5, wherein the device further comprises a circuit state detection circuit, which is composed of a current detection chip, and the input end of the circuit state detection circuit is connected with the load circuit, the output end of the circuit state detection circuit is connected with the processor, the load circuit is connected with the drain electrode of the MOS tube (Q1), the source electrode of the MOS tube (Q1) is grounded, and the gate electrode of the MOS tube (Q1) is connected with the processor.
7. The line load fault detection device of claim 6, wherein the circuit state detection circuit further comprises: a fifteenth resistor (R17), a sixteenth resistor (R18), a seventeenth resistor (R19), an eighteenth resistor (R16) and a second capacitor (C36);
the first input end of the current detection chip is connected with the second end of the load circuit through the sixteenth resistor (R18);
a second input terminal of the current detection chip is connected to one end of the fifteenth resistor (R17), the other end of the fifteenth resistor (R17) is connected to one end of the seventeenth resistor (R19), and the other end of the seventeenth resistor (R19) is connected to a second terminal of the load circuit;
the first input end of the current detection chip is connected with one end of the second capacitor (C36), and the other end of the second capacitor (C36) is connected with the second input end of the current detection chip;
the output end of the current detection chip is connected with the processor through the eighteenth resistor (R16).
8. The line load fault detection device of claim 7, further comprising a nineteenth resistor (R125); the other end of the seventeenth resistor (R19) is connected with the drain electrode of the MOS transistor (Q1), the source electrode of the MOS transistor (Q1) is grounded, the gate electrode of the MOS transistor (Q1) is grounded through the eighteenth resistor (R125), and the gate electrode of the MOS transistor (Q1) is connected with the processor;
the model of the current detection chip is INA 213.
9. The line load fault detection device of claim 7, wherein the first signal amplifier, the second signal amplifier, the third signal amplifier, and the fourth signal amplifier are all OPA4192 in model number.
10. The line load fault detection device according to any one of claims 1-5 and 7-9, further comprising a buzzer, wherein the buzzer is connected to the processor;
and further comprising a display coupled to the processor
The model of the processor is STM32F 405.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020089429.3U CN212675136U (en) | 2020-01-15 | 2020-01-15 | Fault detection device for line load |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020089429.3U CN212675136U (en) | 2020-01-15 | 2020-01-15 | Fault detection device for line load |
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| CN212675136U true CN212675136U (en) | 2021-03-09 |
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| CN202020089429.3U Expired - Fee Related CN212675136U (en) | 2020-01-15 | 2020-01-15 | Fault detection device for line load |
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